^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Min.Guo <min.guo@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <dt-bindings/pinctrl/mt65xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pinctrl-mtk-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-mtk-mt8167.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static const struct mtk_drv_group_desc mt8167_drv_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* 0E4E8SR 4/8/12/16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MTK_DRV_GRP(4, 16, 1, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* 0E2E4SR 2/4/6/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MTK_DRV_GRP(2, 8, 1, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* E8E4E2 2/4/6/8/10/12/14/16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MTK_DRV_GRP(2, 16, 0, 2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const struct mtk_pin_drv_grp mt8167_pin_drv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MTK_PIN_DRV_GRP(0, 0xd00, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MTK_PIN_DRV_GRP(1, 0xd00, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MTK_PIN_DRV_GRP(2, 0xd00, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MTK_PIN_DRV_GRP(3, 0xd00, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MTK_PIN_DRV_GRP(4, 0xd00, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MTK_PIN_DRV_GRP(5, 0xd00, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MTK_PIN_DRV_GRP(6, 0xd00, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MTK_PIN_DRV_GRP(7, 0xd00, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MTK_PIN_DRV_GRP(8, 0xd00, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MTK_PIN_DRV_GRP(9, 0xd00, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MTK_PIN_DRV_GRP(10, 0xd00, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MTK_PIN_DRV_GRP(11, 0xd00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MTK_PIN_DRV_GRP(12, 0xd00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MTK_PIN_DRV_GRP(13, 0xd00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MTK_PIN_DRV_GRP(14, 0xd00, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MTK_PIN_DRV_GRP(15, 0xd00, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MTK_PIN_DRV_GRP(16, 0xd00, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MTK_PIN_DRV_GRP(17, 0xd00, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MTK_PIN_DRV_GRP(18, 0xd10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MTK_PIN_DRV_GRP(19, 0xd10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MTK_PIN_DRV_GRP(20, 0xd10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MTK_PIN_DRV_GRP(21, 0xd00, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MTK_PIN_DRV_GRP(22, 0xd00, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MTK_PIN_DRV_GRP(23, 0xd00, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MTK_PIN_DRV_GRP(24, 0xd00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MTK_PIN_DRV_GRP(25, 0xd00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MTK_PIN_DRV_GRP(26, 0xd10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MTK_PIN_DRV_GRP(27, 0xd10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MTK_PIN_DRV_GRP(28, 0xd10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MTK_PIN_DRV_GRP(29, 0xd10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MTK_PIN_DRV_GRP(30, 0xd10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MTK_PIN_DRV_GRP(31, 0xd10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MTK_PIN_DRV_GRP(32, 0xd10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MTK_PIN_DRV_GRP(33, 0xd10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MTK_PIN_DRV_GRP(34, 0xd10, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MTK_PIN_DRV_GRP(35, 0xd10, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MTK_PIN_DRV_GRP(36, 0xd20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MTK_PIN_DRV_GRP(37, 0xd20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MTK_PIN_DRV_GRP(38, 0xd20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MTK_PIN_DRV_GRP(39, 0xd20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MTK_PIN_DRV_GRP(40, 0xd20, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MTK_PIN_DRV_GRP(41, 0xd20, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MTK_PIN_DRV_GRP(42, 0xd20, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MTK_PIN_DRV_GRP(43, 0xd20, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MTK_PIN_DRV_GRP(44, 0xd20, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MTK_PIN_DRV_GRP(45, 0xd20, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MTK_PIN_DRV_GRP(46, 0xd20, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MTK_PIN_DRV_GRP(47, 0xd20, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MTK_PIN_DRV_GRP(48, 0xd30, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MTK_PIN_DRV_GRP(49, 0xd30, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MTK_PIN_DRV_GRP(50, 0xd30, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MTK_PIN_DRV_GRP(51, 0xd30, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MTK_PIN_DRV_GRP(54, 0xd30, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MTK_PIN_DRV_GRP(55, 0xd30, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MTK_PIN_DRV_GRP(56, 0xd30, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MTK_PIN_DRV_GRP(57, 0xd30, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MTK_PIN_DRV_GRP(62, 0xd40, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MTK_PIN_DRV_GRP(63, 0xd40, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MTK_PIN_DRV_GRP(64, 0xd40, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MTK_PIN_DRV_GRP(65, 0xd40, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MTK_PIN_DRV_GRP(66, 0xd40, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MTK_PIN_DRV_GRP(67, 0xd40, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MTK_PIN_DRV_GRP(68, 0xd40, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MTK_PIN_DRV_GRP(69, 0xd50, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MTK_PIN_DRV_GRP(70, 0xd50, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MTK_PIN_DRV_GRP(71, 0xd50, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MTK_PIN_DRV_GRP(72, 0xd50, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MTK_PIN_DRV_GRP(73, 0xd50, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MTK_PIN_DRV_GRP(100, 0xd50, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MTK_PIN_DRV_GRP(101, 0xd50, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MTK_PIN_DRV_GRP(102, 0xd50, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MTK_PIN_DRV_GRP(103, 0xd50, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MTK_PIN_DRV_GRP(104, 0xd50, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MTK_PIN_DRV_GRP(105, 0xd60, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MTK_PIN_DRV_GRP(106, 0xd60, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MTK_PIN_DRV_GRP(107, 0xd60, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MTK_PIN_DRV_GRP(108, 0xd60, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MTK_PIN_DRV_GRP(109, 0xd60, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MTK_PIN_DRV_GRP(110, 0xd70, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MTK_PIN_DRV_GRP(111, 0xd70, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MTK_PIN_DRV_GRP(112, 0xd70, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MTK_PIN_DRV_GRP(113, 0xd70, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MTK_PIN_DRV_GRP(114, 0xd70, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MTK_PIN_DRV_GRP(115, 0xd60, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MTK_PIN_DRV_GRP(116, 0xd60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MTK_PIN_DRV_GRP(117, 0xd70, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MTK_PIN_DRV_GRP(118, 0xd70, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MTK_PIN_DRV_GRP(119, 0xd70, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MTK_PIN_DRV_GRP(120, 0xd70, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct mtk_pin_spec_pupd_set_samereg mt8167_spec_pupd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int mt8167_spec_pull_set(struct regmap *regmap, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned char align, bool isup, unsigned int r1r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return mtk_pctrl_spec_pull_set_samereg(regmap, mt8167_spec_pupd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ARRAY_SIZE(mt8167_spec_pupd), pin, align, isup, r1r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int mt8167_ies_smt_set(struct regmap *regmap, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned char align, int value, enum pin_config_param arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (arg == PIN_CONFIG_INPUT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_ies_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ARRAY_SIZE(mt8167_ies_set), pin, align, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_smt_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ARRAY_SIZE(mt8167_smt_set), pin, align, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .pins = mtk_pins_mt8167,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .npins = ARRAY_SIZE(mtk_pins_mt8167),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .grp_desc = mt8167_drv_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .n_grp_cls = ARRAY_SIZE(mt8167_drv_grp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .pin_drv_grp = mt8167_pin_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .spec_pull_set = mt8167_spec_pull_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .spec_ies_smt_set = mt8167_ies_smt_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .dir_offset = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .pullen_offset = 0x0500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .pullsel_offset = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .dout_offset = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .din_offset = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .pinmux_offset = 0x0300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .type1_start = 125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .type1_end = 125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .port_shf = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .port_mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .port_align = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .eint_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .port_mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .ports = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .ap_num = 169,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .db_cnt = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int mt8167_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return mtk_pctrl_init(pdev, &mt8167_pinctrl_data, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct of_device_id mt8167_pctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .compatible = "mediatek,mt8167-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MODULE_DEVICE_TABLE(of, mt8167_pctrl_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static struct platform_driver mtk_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .probe = mt8167_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .name = "mediatek-mt8167-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .of_match_table = mt8167_pctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .pm = &mtk_eint_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int __init mtk_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return platform_driver_register(&mtk_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) arch_initcall(mtk_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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