^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/pinctrl/mt65xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pinctrl-mtk-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-mtk-mt8135.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DRV_BASE1 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DRV_BASE2 0x510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PUPD_BASE1 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PUPD_BASE2 0x450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R0_BASE1 0x4d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R1_BASE1 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R1_BASE2 0x250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct mtk_spec_pull_set {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned char pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned char pupd_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned short pupd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned short r0_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned short r1_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned char r0_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned char r1_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPEC_PULL(_pin, _pupd_offset, _pupd_bit, _r0_offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) _r0_bit, _r1_offset, _r1_bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .pin = _pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .pupd_offset = _pupd_offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .pupd_bit = _pupd_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .r0_offset = _r0_offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .r0_bit = _r0_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .r1_offset = _r1_offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .r1_bit = _r1_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const struct mtk_drv_group_desc mt8135_drv_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* E8E4E2 2/4/6/8/10/12/14/16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MTK_DRV_GRP(2, 16, 0, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* E8E4 4/8/12/16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MTK_DRV_GRP(4, 16, 1, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* E4E2 2/4/6/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MTK_DRV_GRP(2, 8, 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* E16E8E4 4/8/12/16/20/24/28/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MTK_DRV_GRP(4, 32, 0, 2, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct mtk_pin_drv_grp mt8135_pin_drv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MTK_PIN_DRV_GRP(10, DRV_BASE1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MTK_PIN_DRV_GRP(11, DRV_BASE1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MTK_PIN_DRV_GRP(12, DRV_BASE1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MTK_PIN_DRV_GRP(13, DRV_BASE1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MTK_PIN_DRV_GRP(14, DRV_BASE1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MTK_PIN_DRV_GRP(15, DRV_BASE1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MTK_PIN_DRV_GRP(16, DRV_BASE1, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MTK_PIN_DRV_GRP(17, DRV_BASE1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MTK_PIN_DRV_GRP(18, DRV_BASE1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MTK_PIN_DRV_GRP(19, DRV_BASE1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MTK_PIN_DRV_GRP(20, DRV_BASE1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MTK_PIN_DRV_GRP(21, DRV_BASE1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MTK_PIN_DRV_GRP(22, DRV_BASE1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MTK_PIN_DRV_GRP(23, DRV_BASE1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MTK_PIN_DRV_GRP(24, DRV_BASE1, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MTK_PIN_DRV_GRP(33, DRV_BASE1, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MTK_PIN_DRV_GRP(34, DRV_BASE2, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MTK_PIN_DRV_GRP(37, DRV_BASE2, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MTK_PIN_DRV_GRP(38, DRV_BASE2, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MTK_PIN_DRV_GRP(39, DRV_BASE2, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MTK_PIN_DRV_GRP(40, DRV_BASE2, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MTK_PIN_DRV_GRP(41, DRV_BASE2, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MTK_PIN_DRV_GRP(42, DRV_BASE2, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MTK_PIN_DRV_GRP(43, DRV_BASE2, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MTK_PIN_DRV_GRP(44, DRV_BASE2, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MTK_PIN_DRV_GRP(45, DRV_BASE2, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MTK_PIN_DRV_GRP(46, DRV_BASE2, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MTK_PIN_DRV_GRP(47, DRV_BASE2, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MTK_PIN_DRV_GRP(49, DRV_BASE2+0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MTK_PIN_DRV_GRP(50, DRV_BASE2+0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MTK_PIN_DRV_GRP(51, DRV_BASE2+0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MTK_PIN_DRV_GRP(52, DRV_BASE2+0x10, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MTK_PIN_DRV_GRP(53, DRV_BASE2+0x10, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MTK_PIN_DRV_GRP(54, DRV_BASE2+0x10, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MTK_PIN_DRV_GRP(55, DRV_BASE2+0x10, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MTK_PIN_DRV_GRP(56, DRV_BASE2+0x10, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MTK_PIN_DRV_GRP(57, DRV_BASE2+0x20, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MTK_PIN_DRV_GRP(58, DRV_BASE2+0x20, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MTK_PIN_DRV_GRP(59, DRV_BASE2+0x20, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MTK_PIN_DRV_GRP(60, DRV_BASE2+0x20, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MTK_PIN_DRV_GRP(61, DRV_BASE2+0x20, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MTK_PIN_DRV_GRP(62, DRV_BASE2+0x20, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MTK_PIN_DRV_GRP(63, DRV_BASE2+0x20, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MTK_PIN_DRV_GRP(64, DRV_BASE2+0x20, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MTK_PIN_DRV_GRP(65, DRV_BASE2+0x20, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MTK_PIN_DRV_GRP(66, DRV_BASE2+0x20, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MTK_PIN_DRV_GRP(67, DRV_BASE2+0x20, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MTK_PIN_DRV_GRP(68, DRV_BASE2+0x20, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MTK_PIN_DRV_GRP(69, DRV_BASE2+0x20, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MTK_PIN_DRV_GRP(70, DRV_BASE2+0x30, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MTK_PIN_DRV_GRP(71, DRV_BASE2+0x30, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MTK_PIN_DRV_GRP(72, DRV_BASE2+0x30, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MTK_PIN_DRV_GRP(73, DRV_BASE2+0x30, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MTK_PIN_DRV_GRP(74, DRV_BASE2+0x30, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MTK_PIN_DRV_GRP(75, DRV_BASE2+0x30, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MTK_PIN_DRV_GRP(76, DRV_BASE2+0x30, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MTK_PIN_DRV_GRP(77, DRV_BASE2+0x30, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MTK_PIN_DRV_GRP(78, DRV_BASE2+0x30, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MTK_PIN_DRV_GRP(79, DRV_BASE2+0x40, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MTK_PIN_DRV_GRP(80, DRV_BASE2+0x40, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MTK_PIN_DRV_GRP(81, DRV_BASE2+0x30, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MTK_PIN_DRV_GRP(82, DRV_BASE2+0x30, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MTK_PIN_DRV_GRP(83, DRV_BASE2+0x40, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MTK_PIN_DRV_GRP(84, DRV_BASE2+0x40, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MTK_PIN_DRV_GRP(85, DRV_BASE2+0x40, 12, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MTK_PIN_DRV_GRP(86, DRV_BASE2+0x40, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MTK_PIN_DRV_GRP(87, DRV_BASE2+0x40, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MTK_PIN_DRV_GRP(88, DRV_BASE2+0x40, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MTK_PIN_DRV_GRP(96, DRV_BASE1+0xb0, 28, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MTK_PIN_DRV_GRP(102, DRV_BASE2+0x50, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MTK_PIN_DRV_GRP(103, DRV_BASE2+0x50, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MTK_PIN_DRV_GRP(104, DRV_BASE2+0x60, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MTK_PIN_DRV_GRP(105, DRV_BASE2+0x60, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MTK_PIN_DRV_GRP(106, DRV_BASE2+0x60, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MTK_PIN_DRV_GRP(107, DRV_BASE2+0x60, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MTK_PIN_DRV_GRP(108, DRV_BASE2+0x60, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MTK_PIN_DRV_GRP(109, DRV_BASE2+0x60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MTK_PIN_DRV_GRP(110, DRV_BASE2+0x60, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MTK_PIN_DRV_GRP(111, DRV_BASE2+0x60, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MTK_PIN_DRV_GRP(112, DRV_BASE2+0x60, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MTK_PIN_DRV_GRP(113, DRV_BASE2+0x60, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MTK_PIN_DRV_GRP(114, DRV_BASE2+0x60, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MTK_PIN_DRV_GRP(115, DRV_BASE2+0x70, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MTK_PIN_DRV_GRP(116, DRV_BASE2+0x70, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MTK_PIN_DRV_GRP(117, DRV_BASE2+0x70, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MTK_PIN_DRV_GRP(118, DRV_BASE2+0x70, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MTK_PIN_DRV_GRP(119, DRV_BASE2+0x70, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MTK_PIN_DRV_GRP(120, DRV_BASE2+0x70, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MTK_PIN_DRV_GRP(181, DRV_BASE1+0xa0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MTK_PIN_DRV_GRP(182, DRV_BASE1+0xa0, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MTK_PIN_DRV_GRP(183, DRV_BASE1+0xa0, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MTK_PIN_DRV_GRP(184, DRV_BASE1+0xa0, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MTK_PIN_DRV_GRP(185, DRV_BASE1+0xa0, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MTK_PIN_DRV_GRP(186, DRV_BASE1+0xb0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MTK_PIN_DRV_GRP(187, DRV_BASE1+0xb0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MTK_PIN_DRV_GRP(188, DRV_BASE1+0xb0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MTK_PIN_DRV_GRP(189, DRV_BASE1+0xb0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MTK_PIN_DRV_GRP(190, DRV_BASE1+0xb0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MTK_PIN_DRV_GRP(191, DRV_BASE1+0xb0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MTK_PIN_DRV_GRP(192, DRV_BASE1+0xb0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MTK_PIN_DRV_GRP(197, DRV_BASE1+0xb0, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MTK_PIN_DRV_GRP(198, DRV_BASE1+0xb0, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MTK_PIN_DRV_GRP(199, DRV_BASE1+0xb0, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MTK_PIN_DRV_GRP(200, DRV_BASE1+0xb0, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MTK_PIN_DRV_GRP(201, DRV_BASE1+0xb0, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MTK_PIN_DRV_GRP(202, DRV_BASE1+0xb0, 16, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct mtk_spec_pull_set spec_pupd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) SPEC_PULL(0, PUPD_BASE1, 0, R0_BASE1, 9, R1_BASE1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SPEC_PULL(1, PUPD_BASE1, 1, R0_BASE1, 8, R1_BASE1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SPEC_PULL(2, PUPD_BASE1, 2, R0_BASE1, 7, R1_BASE1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) SPEC_PULL(3, PUPD_BASE1, 3, R0_BASE1, 6, R1_BASE1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SPEC_PULL(4, PUPD_BASE1, 4, R0_BASE1, 1, R1_BASE1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) SPEC_PULL(5, PUPD_BASE1, 5, R0_BASE1, 0, R1_BASE1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SPEC_PULL(6, PUPD_BASE1, 6, R0_BASE1, 5, R1_BASE1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) SPEC_PULL(7, PUPD_BASE1, 7, R0_BASE1, 4, R1_BASE1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SPEC_PULL(8, PUPD_BASE1, 8, R0_BASE1, 3, R1_BASE1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) SPEC_PULL(9, PUPD_BASE1, 9, R0_BASE1, 2, R1_BASE1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SPEC_PULL(89, PUPD_BASE2, 9, R0_BASE1, 18, R1_BASE2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SPEC_PULL(90, PUPD_BASE2, 10, R0_BASE1, 19, R1_BASE2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SPEC_PULL(91, PUPD_BASE2, 11, R0_BASE1, 23, R1_BASE2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SPEC_PULL(92, PUPD_BASE2, 12, R0_BASE1, 24, R1_BASE2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SPEC_PULL(93, PUPD_BASE2, 13, R0_BASE1, 25, R1_BASE2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SPEC_PULL(94, PUPD_BASE2, 14, R0_BASE1, 22, R1_BASE2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SPEC_PULL(95, PUPD_BASE2, 15, R0_BASE1, 20, R1_BASE2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SPEC_PULL(96, PUPD_BASE2+0x10, 0, R0_BASE1, 16, R1_BASE2+0x10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SPEC_PULL(97, PUPD_BASE2+0x10, 1, R0_BASE1, 21, R1_BASE2+0x10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SPEC_PULL(98, PUPD_BASE2+0x10, 2, R0_BASE1, 17, R1_BASE2+0x10, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SPEC_PULL(197, PUPD_BASE1+0xc0, 5, R0_BASE1, 13, R1_BASE2+0xc0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SPEC_PULL(198, PUPD_BASE2+0xc0, 6, R0_BASE1, 14, R1_BASE2+0xc0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SPEC_PULL(199, PUPD_BASE2+0xc0, 7, R0_BASE1, 11, R1_BASE2+0xc0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SPEC_PULL(200, PUPD_BASE2+0xc0, 8, R0_BASE1, 10, R1_BASE2+0xc0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SPEC_PULL(201, PUPD_BASE2+0xc0, 9, R0_BASE1, 13, R1_BASE2+0xc0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int spec_pull_set(struct regmap *regmap, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned char align, bool isup, unsigned int r1r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int reg_pupd, reg_set_r0, reg_set_r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int reg_rst_r0, reg_rst_r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bool find = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (pin == spec_pupd[i].pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) find = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!find)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (isup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) reg_pupd = spec_pupd[i].pupd_offset + align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) reg_pupd = spec_pupd[i].pupd_offset + (align << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) regmap_write(regmap, reg_pupd, spec_pupd[i].pupd_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) reg_set_r0 = spec_pupd[i].r0_offset + align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) reg_rst_r0 = spec_pupd[i].r0_offset + (align << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) reg_set_r1 = spec_pupd[i].r1_offset + align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) reg_rst_r1 = spec_pupd[i].r1_offset + (align << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) switch (r1r0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case MTK_PUPD_SET_R1R0_00:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case MTK_PUPD_SET_R1R0_01:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case MTK_PUPD_SET_R1R0_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case MTK_PUPD_SET_R1R0_11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .pins = mtk_pins_mt8135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .npins = ARRAY_SIZE(mtk_pins_mt8135),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .grp_desc = mt8135_drv_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .n_grp_cls = ARRAY_SIZE(mt8135_drv_grp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .pin_drv_grp = mt8135_pin_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .n_pin_drv_grps = ARRAY_SIZE(mt8135_pin_drv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .spec_pull_set = spec_pull_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .dir_offset = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .ies_offset = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .pullen_offset = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .smt_offset = 0x0300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .pullsel_offset = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .dout_offset = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .din_offset = 0x0A00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .pinmux_offset = 0x0C00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .type1_start = 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .type1_end = 149,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .port_shf = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .port_mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .port_align = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .eint_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .port_mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .ports = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .ap_num = 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .db_cnt = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int mt8135_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct of_device_id mt8135_pctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .compatible = "mediatek,mt8135-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static struct platform_driver mtk_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .probe = mt8135_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .name = "mediatek-mt8135-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .of_match_table = mt8135_pctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int __init mtk_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return platform_driver_register(&mtk_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) arch_initcall(mtk_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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