Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * The MT7629 driver based on Linux generic pinctrl binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Ryder Lee <ryder.lee@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include "pinctrl-moore.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define MT7629_PIN(_number, _name, _eint_n)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	MTK_PIN(_number, _name, 0, _eint_n, DRV_GRP1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static const struct mtk_pin_field_calc mt7629_pin_di_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static const struct mtk_pin_field_calc mt7629_pin_do_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	PIN_FIELD(70, 78, 0x7000, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static const struct mtk_pin_field_calc mt7629_pin_smt_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	PIN_FIELD(0, 10, 0x1100, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	PIN_FIELD(11, 18, 0x2100, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	PIN_FIELD(19, 32, 0x3100, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	PIN_FIELD(33, 48, 0x4100, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	PIN_FIELD(49, 50, 0x5100, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	PIN_FIELD(51, 69, 0x6100, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	PIN_FIELD(70, 78, 0x7100, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static const struct mtk_pin_field_calc mt7629_pin_pullen_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	PIN_FIELD(0, 10, 0x1400, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	PIN_FIELD(11, 18, 0x2400, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	PIN_FIELD(19, 32, 0x3400, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	PIN_FIELD(33, 48, 0x4400, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	PIN_FIELD(49, 50, 0x5400, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	PIN_FIELD(51, 69, 0x6400, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	PIN_FIELD(70, 78, 0x7400, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static const struct mtk_pin_field_calc mt7629_pin_pullsel_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	PIN_FIELD(0, 10, 0x1500, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	PIN_FIELD(11, 18, 0x2500, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	PIN_FIELD(19, 32, 0x3500, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	PIN_FIELD(33, 48, 0x4500, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	PIN_FIELD(49, 50, 0x5500, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	PIN_FIELD(51, 69, 0x6500, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	PIN_FIELD(70, 78, 0x7500, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	PIN_FIELD(0, 10, 0x1600, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	PIN_FIELD(11, 18, 0x2600, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	PIN_FIELD(19, 32, 0x3600, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	PIN_FIELD(33, 48, 0x4600, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	PIN_FIELD(49, 50, 0x5600, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	PIN_FIELD(51, 69, 0x6600, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) static const struct mtk_pin_field_calc mt7629_pin_tdsel_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	PIN_FIELD(0, 10, 0x1200, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	PIN_FIELD(11, 18, 0x2200, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	PIN_FIELD(19, 32, 0x3200, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	PIN_FIELD(33, 48, 0x4200, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	PIN_FIELD(49, 50, 0x5200, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	PIN_FIELD(51, 69, 0x6200, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	PIN_FIELD(70, 78, 0x7200, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static const struct mtk_pin_field_calc mt7629_pin_rdsel_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	PIN_FIELD(0, 10, 0x1300, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	PIN_FIELD(11, 18, 0x2300, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	PIN_FIELD(19, 32, 0x3300, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	PIN_FIELD(33, 48, 0x4300, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	PIN_FIELD(49, 50, 0x5300, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	PIN_FIELD(51, 69, 0x6300, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	PIN_FIELD(70, 78, 0x7300, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct mtk_pin_reg_calc mt7629_reg_cals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7629_pin_do_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	[PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7629_pin_ies_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	[PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7629_pin_smt_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	[PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7629_pin_pullsel_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	[PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7629_pin_pullen_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	[PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7629_pin_drv_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	[PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7629_pin_tdsel_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	[PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7629_pin_rdsel_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct mtk_pin_desc mt7629_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	MT7629_PIN(0, "TOP_5G_CLK", 53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	MT7629_PIN(1, "TOP_5G_DATA", 54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	MT7629_PIN(2, "WF0_5G_HB0", 55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	MT7629_PIN(3, "WF0_5G_HB1", 56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	MT7629_PIN(4, "WF0_5G_HB2", 57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	MT7629_PIN(5, "WF0_5G_HB3", 58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	MT7629_PIN(6, "WF0_5G_HB4", 59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	MT7629_PIN(7, "WF0_5G_HB5", 60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	MT7629_PIN(8, "WF0_5G_HB6", 61),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	MT7629_PIN(9, "XO_REQ", 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	MT7629_PIN(10, "TOP_RST_N", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	MT7629_PIN(11, "SYS_WATCHDOG", 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	MT7629_PIN(12, "EPHY_LED0_N_JTDO", 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	MT7629_PIN(13, "EPHY_LED1_N_JTDI", 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	MT7629_PIN(14, "EPHY_LED2_N_JTMS", 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	MT7629_PIN(15, "EPHY_LED3_N_JTCLK", 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	MT7629_PIN(16, "EPHY_LED4_N_JTRST_N", 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	MT7629_PIN(17, "WF2G_LED_N", 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	MT7629_PIN(18, "WF5G_LED_N", 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	MT7629_PIN(19, "I2C_SDA", 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	MT7629_PIN(20, "I2C_SCL", 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	MT7629_PIN(21, "GPIO_9", 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	MT7629_PIN(22, "GPIO_10", 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	MT7629_PIN(23, "GPIO_11", 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	MT7629_PIN(24, "GPIO_12", 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	MT7629_PIN(25, "UART1_TXD", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	MT7629_PIN(26, "UART1_RXD", 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	MT7629_PIN(27, "UART1_CTS", 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	MT7629_PIN(28, "UART1_RTS", 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	MT7629_PIN(29, "UART2_TXD", 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	MT7629_PIN(30, "UART2_RXD", 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	MT7629_PIN(31, "UART2_CTS", 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	MT7629_PIN(32, "UART2_RTS", 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	MT7629_PIN(33, "MDI_TP_P1", 33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	MT7629_PIN(34, "MDI_TN_P1", 34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	MT7629_PIN(35, "MDI_RP_P1", 35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	MT7629_PIN(36, "MDI_RN_P1", 36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	MT7629_PIN(37, "MDI_RP_P2", 37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	MT7629_PIN(38, "MDI_RN_P2", 38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	MT7629_PIN(39, "MDI_TP_P2", 39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	MT7629_PIN(40, "MDI_TN_P2", 40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	MT7629_PIN(41, "MDI_TP_P3", 41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	MT7629_PIN(42, "MDI_TN_P3", 42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	MT7629_PIN(43, "MDI_RP_P3", 43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	MT7629_PIN(44, "MDI_RN_P3", 44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	MT7629_PIN(45, "MDI_RP_P4", 45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	MT7629_PIN(46, "MDI_RN_P4", 46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	MT7629_PIN(47, "MDI_TP_P4", 47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	MT7629_PIN(48, "MDI_TN_P4", 48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	MT7629_PIN(49, "SMI_MDC", 49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	MT7629_PIN(50, "SMI_MDIO", 50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	MT7629_PIN(51, "PCIE_PERESET_N", 51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	MT7629_PIN(52, "PWM_0", 52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	MT7629_PIN(53, "GPIO_0", 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	MT7629_PIN(54, "GPIO_1", 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	MT7629_PIN(55, "GPIO_2", 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	MT7629_PIN(56, "GPIO_3", 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	MT7629_PIN(57, "GPIO_4", 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	MT7629_PIN(58, "GPIO_5", 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	MT7629_PIN(59, "GPIO_6", 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	MT7629_PIN(60, "GPIO_7", 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	MT7629_PIN(61, "GPIO_8", 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	MT7629_PIN(62, "SPI_CLK", 62),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	MT7629_PIN(63, "SPI_CS", 63),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	MT7629_PIN(64, "SPI_MOSI", 64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	MT7629_PIN(65, "SPI_MISO", 65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	MT7629_PIN(66, "SPI_WP", 66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	MT7629_PIN(67, "SPI_HOLD", 67),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	MT7629_PIN(68, "UART0_TXD", 68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	MT7629_PIN(69, "UART0_RXD", 69),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	MT7629_PIN(70, "TOP_2G_CLK", 70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	MT7629_PIN(71, "TOP_2G_DATA", 71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	MT7629_PIN(72, "WF0_2G_HB0", 72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	MT7629_PIN(73, "WF0_2G_HB1", 73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	MT7629_PIN(74, "WF0_2G_HB2", 74),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	MT7629_PIN(75, "WF0_2G_HB3", 75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	MT7629_PIN(76, "WF0_2G_HB4", 76),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	MT7629_PIN(77, "WF0_2G_HB5", 77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	MT7629_PIN(78, "WF0_2G_HB6", 78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* List all groups consisting of these pins dedicated to the enablement of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  * certain hardware block and the corresponding mode for all of the pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  * The hardware probably has multiple combinations of these pinouts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* LED for EPHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int mt7629_ephy_leds_pins[] = { 12, 13, 14, 15, 16, 17, 18, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int mt7629_ephy_leds_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int mt7629_ephy_led0_pins[] = { 12, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int mt7629_ephy_led0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int mt7629_ephy_led1_pins[] = { 13, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int mt7629_ephy_led1_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int mt7629_ephy_led2_pins[] = { 14, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int mt7629_ephy_led2_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int mt7629_ephy_led3_pins[] = { 15, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static int mt7629_ephy_led3_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int mt7629_ephy_led4_pins[] = { 16, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int mt7629_ephy_led4_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int mt7629_wf2g_led_pins[] = { 17, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int mt7629_wf2g_led_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int mt7629_wf5g_led_pins[] = { 18, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int mt7629_wf5g_led_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int mt7629_watchdog_pins[] = { 11, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int mt7629_watchdog_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* LED for GPHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int mt7629_gphy_leds_0_pins[] = { 21, 22, 23, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int mt7629_gphy_leds_0_funcs[] = { 2, 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int mt7629_gphy_led1_0_pins[] = { 21, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int mt7629_gphy_led1_0_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int mt7629_gphy_led2_0_pins[] = { 22, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int mt7629_gphy_led2_0_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int mt7629_gphy_led3_0_pins[] = { 23, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int mt7629_gphy_led3_0_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int mt7629_gphy_leds_1_pins[] = { 57, 58, 59, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int mt7629_gphy_leds_1_funcs[] = { 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int mt7629_gphy_led1_1_pins[] = { 57, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int mt7629_gphy_led1_1_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int mt7629_gphy_led2_1_pins[] = { 58, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int mt7629_gphy_led2_1_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int mt7629_gphy_led3_1_pins[] = { 59, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int mt7629_gphy_led3_1_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int mt7629_i2c_0_pins[] = { 19, 20, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int mt7629_i2c_0_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int mt7629_i2c_1_pins[] = { 53, 54, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int mt7629_i2c_1_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int mt7629_spi_0_pins[] = { 21, 22, 23, 24, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int mt7629_spi_0_funcs[] = { 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int mt7629_spi_1_pins[] = { 62, 63, 64, 65, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int mt7629_spi_1_funcs[] = { 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int mt7629_spi_wp_pins[] = { 66, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int mt7629_spi_wp_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int mt7629_spi_hold_pins[] = { 67, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int mt7629_spi_hold_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int mt7629_uart1_0_txd_rxd_pins[] = { 25, 26, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int mt7629_uart1_0_txd_rxd_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static int mt7629_uart1_1_txd_rxd_pins[] = { 53, 54, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int mt7629_uart1_1_txd_rxd_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int mt7629_uart2_0_txd_rxd_pins[] = { 29, 30, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int mt7629_uart2_0_txd_rxd_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int mt7629_uart2_1_txd_rxd_pins[] = { 57, 58, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int mt7629_uart2_1_txd_rxd_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int mt7629_uart1_0_cts_rts_pins[] = { 27, 28, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int mt7629_uart1_0_cts_rts_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int mt7629_uart1_1_cts_rts_pins[] = { 55, 56, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int mt7629_uart1_1_cts_rts_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int mt7629_uart2_0_cts_rts_pins[] = { 31, 32, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int mt7629_uart2_0_cts_rts_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int mt7629_uart2_1_cts_rts_pins[] = { 59, 60, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int mt7629_uart2_1_cts_rts_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int mt7629_uart0_txd_rxd_pins[] = { 68, 69, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int mt7629_uart0_txd_rxd_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* MDC/MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int mt7629_mdc_mdio_pins[] = { 49, 50, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int mt7629_mdc_mdio_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int mt7629_pcie_pereset_pins[] = { 51, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int mt7629_pcie_pereset_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int mt7629_pcie_wake_pins[] = { 55, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int mt7629_pcie_wake_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int mt7629_pcie_clkreq_pins[] = { 56, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int mt7629_pcie_clkreq_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int mt7629_pwm_0_pins[] = { 52, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int mt7629_pwm_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int mt7629_pwm_1_pins[] = { 61, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int mt7629_pwm_1_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* WF 2G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int mt7629_wf0_2g_pins[] = { 70, 71, 72, 73, 74, 75, 76, 77, 78, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int mt7629_wf0_2g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* WF 5G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int mt7629_wf0_5g_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int mt7629_wf0_5g_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* SNFI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int mt7629_snfi_pins[] = { 62, 63, 64, 65, 66, 67 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int mt7629_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* SPI NOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int mt7629_snor_pins[] = { 62, 63, 64, 65, 66, 67 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int mt7629_snor_funcs[] = { 1, 1, 1, 1, 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct group_desc mt7629_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	PINCTRL_PIN_GROUP("ephy_leds", mt7629_ephy_leds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	PINCTRL_PIN_GROUP("ephy_led0", mt7629_ephy_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	PINCTRL_PIN_GROUP("ephy_led1", mt7629_ephy_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	PINCTRL_PIN_GROUP("gphy_leds_0", mt7629_gphy_leds_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	PINCTRL_PIN_GROUP("gphy_led1_0", mt7629_gphy_led1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	PINCTRL_PIN_GROUP("gphy_led2_0", mt7629_gphy_led2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	PINCTRL_PIN_GROUP("gphy_led3_0", mt7629_gphy_led3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	PINCTRL_PIN_GROUP("gphy_leds_1", mt7629_gphy_leds_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	PINCTRL_PIN_GROUP("gphy_led1_1", mt7629_gphy_led1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	PINCTRL_PIN_GROUP("gphy_led2_1", mt7629_gphy_led2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	PINCTRL_PIN_GROUP("gphy_led3_1", mt7629_gphy_led3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	PINCTRL_PIN_GROUP("i2c_0", mt7629_i2c_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	PINCTRL_PIN_GROUP("i2c_1", mt7629_i2c_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	PINCTRL_PIN_GROUP("spi_0", mt7629_spi_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	PINCTRL_PIN_GROUP("spi_1", mt7629_spi_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	PINCTRL_PIN_GROUP("spi_wp", mt7629_spi_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	PINCTRL_PIN_GROUP("spi_hold", mt7629_spi_hold),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7629_uart1_0_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7629_uart1_1_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7629_uart2_0_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7629_uart2_1_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	PINCTRL_PIN_GROUP("uart1_0_cts_rts", mt7629_uart1_0_cts_rts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	PINCTRL_PIN_GROUP("uart1_1_cts_rts", mt7629_uart1_1_cts_rts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	PINCTRL_PIN_GROUP("uart2_0_cts_rts", mt7629_uart2_0_cts_rts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	PINCTRL_PIN_GROUP("uart2_1_cts_rts", mt7629_uart2_1_cts_rts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	PINCTRL_PIN_GROUP("uart0_txd_rxd", mt7629_uart0_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	PINCTRL_PIN_GROUP("mdc_mdio", mt7629_mdc_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	PINCTRL_PIN_GROUP("pcie_pereset", mt7629_pcie_pereset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	PINCTRL_PIN_GROUP("pcie_wake", mt7629_pcie_wake),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	PINCTRL_PIN_GROUP("pcie_clkreq", mt7629_pcie_clkreq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	PINCTRL_PIN_GROUP("pwm_0", mt7629_pwm_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	PINCTRL_PIN_GROUP("pwm_1", mt7629_pwm_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	PINCTRL_PIN_GROUP("wf0_5g", mt7629_wf0_5g),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	PINCTRL_PIN_GROUP("wf0_2g", mt7629_wf0_2g),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	PINCTRL_PIN_GROUP("snfi", mt7629_snfi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	PINCTRL_PIN_GROUP("spi_nor", mt7629_snor),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Joint those groups owning the same capability in user point of view which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)  * allows that people tend to use through the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const char *mt7629_ethernet_groups[] = { "mdc_mdio", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const char *mt7629_i2c_groups[] = { "i2c_0", "i2c_1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const char *mt7629_led_groups[] = { "ephy_leds", "ephy_led0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 					   "ephy_led1", "ephy_led2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 					   "ephy_led3", "ephy_led4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 					   "wf2g_led", "wf5g_led",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 					   "gphy_leds_0", "gphy_led1_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 					   "gphy_led2_0", "gphy_led3_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 					   "gphy_leds_1", "gphy_led1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 					   "gphy_led2_1", "gphy_led3_1",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const char *mt7629_pcie_groups[] = { "pcie_pereset", "pcie_wake",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 					    "pcie_clkreq", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const char *mt7629_pwm_groups[] = { "pwm_0", "pwm_1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const char *mt7629_spi_groups[] = { "spi_0", "spi_1", "spi_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 					   "spi_hold", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const char *mt7629_uart_groups[] = { "uart1_0_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 					    "uart1_1_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 					    "uart2_0_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 					    "uart2_1_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 					    "uart1_0_cts_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 					    "uart1_1_cts_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 					    "uart2_0_cts_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 					    "uart2_1_cts_rts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 					    "uart0_txd_rxd", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const char *mt7629_wdt_groups[] = { "watchdog", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const char *mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const char *mt7629_flash_groups[] = { "snfi", "spi_nor" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct function_desc mt7629_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	{"eth",	mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	{"i2c", mt7629_i2c_groups, ARRAY_SIZE(mt7629_i2c_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	{"led",	mt7629_led_groups, ARRAY_SIZE(mt7629_led_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	{"pcie", mt7629_pcie_groups, ARRAY_SIZE(mt7629_pcie_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	{"pwm",	mt7629_pwm_groups, ARRAY_SIZE(mt7629_pwm_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	{"spi",	mt7629_spi_groups, ARRAY_SIZE(mt7629_spi_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	{"uart", mt7629_uart_groups, ARRAY_SIZE(mt7629_uart_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	{"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	{"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	{"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct mtk_eint_hw mt7629_eint_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	.port_mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	.ports     = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.ap_num    = ARRAY_SIZE(mt7629_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.db_cnt    = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static struct mtk_pin_soc mt7629_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	.reg_cal = mt7629_reg_cals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.pins = mt7629_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.npins = ARRAY_SIZE(mt7629_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.grps = mt7629_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.ngrps = ARRAY_SIZE(mt7629_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.funcs = mt7629_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.nfuncs = ARRAY_SIZE(mt7629_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	.eint_hw = &mt7629_eint_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	.gpio_m = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	.ies_present = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	.base_names = mtk_default_register_base_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	.nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	.bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	.bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	.bias_set = mtk_pinconf_bias_set_rev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	.bias_get = mtk_pinconf_bias_get_rev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	.drive_set = mtk_pinconf_drive_set_rev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	.drive_get = mtk_pinconf_drive_get_rev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const struct of_device_id mt7629_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	{ .compatible = "mediatek,mt7629-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int mt7629_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	return mtk_moore_pinctrl_probe(pdev, &mt7629_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static struct platform_driver mt7629_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		.name = "mt7629-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		.of_match_table = mt7629_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	.probe = mt7629_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int __init mt7629_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	return platform_driver_register(&mt7629_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) arch_initcall(mt7629_pinctrl_init);