^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * The MT7623 driver based on Linux generic pinctrl binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 - 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Biao Huang <biao.huang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Ryder Lee <ryder.lee@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "pinctrl-moore.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PIN_BOND_REG0 0xb10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PIN_BOND_REG1 0xf20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PIN_BOND_REG2 0xef0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BOND_PCIE_CLR (0x77 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BOND_I2S_CLR 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BOND_MSDC0E_CLR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) _x_bits, 15, false)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) _x_bits, 16, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) _x_bits, 16, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MT7623_PIN(_number, _name, _eint_n, _drv_grp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MTK_PIN(_number, _name, 0, _eint_n, _drv_grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static const struct mtk_pin_field_calc mt7623_pin_di_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const struct mtk_pin_field_calc mt7623_pin_do_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PIN_FIELD16(116, 116, 0xcd0, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PIN_FIELD16(117, 117, 0xcc0, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINS_FIELD16(118, 121, 0xce0, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINS_FIELD16(122, 125, 0xb30, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PIN_FIELD16(126, 126, 0xb20, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINS_FIELD16(127, 142, 0xb30, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINS_FIELD16(143, 160, 0xb30, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINS_FIELD16(161, 168, 0xb30, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINS_FIELD16(169, 183, 0xb30, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINS_FIELD16(184, 186, 0xb30, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PIN_FIELD16(187, 187, 0xb30, 0x10, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PIN_FIELD16(188, 188, 0xb20, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINS_FIELD16(189, 193, 0xb30, 0x10, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINS_FIELD16(194, 198, 0xb40, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PIN_FIELD16(199, 199, 0xb20, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINS_FIELD16(200, 202, 0xb40, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINS_FIELD16(203, 207, 0xb40, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINS_FIELD16(208, 209, 0xb40, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PIN_FIELD16(210, 210, 0xb40, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINS_FIELD16(211, 235, 0xb40, 0x10, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINS_FIELD16(236, 241, 0xb40, 0x10, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINS_FIELD16(242, 243, 0xb40, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINS_FIELD16(244, 247, 0xb40, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PIN_FIELD16(248, 248, 0xb40, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINS_FIELD16(249, 257, 0xfc0, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PIN_FIELD16(258, 258, 0xcb0, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PIN_FIELD16(259, 259, 0xc90, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PIN_FIELD16(260, 260, 0x3a0, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PIN_FIELD16(261, 261, 0xd50, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINS_FIELD16(262, 277, 0xb40, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PIN_FIELD16(278, 278, 0xb40, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const struct mtk_pin_field_calc mt7623_pin_smt_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINS_FIELD16(0, 6, 0xb50, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINS_FIELD16(7, 9, 0xb50, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINS_FIELD16(10, 13, 0xb60, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINS_FIELD16(14, 15, 0xb60, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINS_FIELD16(16, 17, 0xb70, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINS_FIELD16(18, 29, 0xb70, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINS_FIELD16(30, 32, 0xb70, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINS_FIELD16(33, 37, 0xb70, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PIN_FIELD16(38, 38, 0xb50, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINS_FIELD16(39, 42, 0xb70, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINS_FIELD16(43, 45, 0xb50, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINS_FIELD16(47, 48, 0xb50, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PIN_FIELD16(49, 49, 0xb50, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINS_FIELD16(50, 52, 0xb50, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINS_FIELD16(53, 56, 0xb50, 0x10, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINS_FIELD16(57, 58, 0xb50, 0x10, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PIN_FIELD16(59, 59, 0xb60, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINS_FIELD16(60, 62, 0xb60, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINS_FIELD16(63, 65, 0xb60, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINS_FIELD16(66, 71, 0xb60, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINS_FIELD16(72, 74, 0xb50, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINS_FIELD16(75, 76, 0xb60, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINS_FIELD16(77, 78, 0xb60, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINS_FIELD16(79, 82, 0xb60, 0x10, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINS_FIELD16(83, 84, 0xb60, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PIN_FIELD16(85, 85, 0xda0, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PIN_FIELD16(86, 86, 0xd90, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PIN_FIELD16(87, 87, 0xdc0, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PIN_FIELD16(88, 88, 0xdc0, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PIN_FIELD16(89, 89, 0xdc0, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PIN_FIELD16(90, 90, 0xdc0, 0x10, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINS_FIELD16(101, 104, 0xb60, 0x10, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PIN_FIELD16(105, 105, 0xd40, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PIN_FIELD16(106, 106, 0xd30, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PIN_FIELD16(107, 107, 0xd60, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PIN_FIELD16(108, 108, 0xd60, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PIN_FIELD16(109, 109, 0xd60, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PIN_FIELD16(110, 110, 0xd60, 0x10, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PIN_FIELD16(111, 111, 0xd00, 0x10, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PIN_FIELD16(112, 112, 0xd00, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PIN_FIELD16(113, 113, 0xd00, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PIN_FIELD16(114, 114, 0xd00, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PIN_FIELD16(115, 115, 0xd10, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PIN_FIELD16(116, 116, 0xcd0, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PIN_FIELD16(117, 117, 0xcc0, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PIN_FIELD16(118, 118, 0xcf0, 0x10, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PIN_FIELD16(119, 119, 0xcf0, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PIN_FIELD16(120, 120, 0xcf0, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PIN_FIELD16(121, 121, 0xcf0, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINS_FIELD16(122, 125, 0xb60, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PIN_FIELD16(126, 126, 0xb50, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINS_FIELD16(127, 142, 0xb60, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINS_FIELD16(143, 160, 0xb60, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINS_FIELD16(161, 168, 0xb60, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINS_FIELD16(169, 183, 0xb60, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINS_FIELD16(184, 186, 0xb60, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PIN_FIELD16(187, 187, 0xb60, 0x10, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PIN_FIELD16(188, 188, 0xb50, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINS_FIELD16(189, 193, 0xb60, 0x10, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINS_FIELD16(194, 198, 0xb70, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PIN_FIELD16(199, 199, 0xb50, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINS_FIELD16(200, 202, 0xb70, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINS_FIELD16(203, 207, 0xb70, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINS_FIELD16(208, 209, 0xb70, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PIN_FIELD16(210, 210, 0xb70, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINS_FIELD16(211, 235, 0xb70, 0x10, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINS_FIELD16(236, 241, 0xb70, 0x10, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINS_FIELD16(242, 243, 0xb70, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINS_FIELD16(244, 247, 0xb70, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PIN_FIELD16(248, 248, 0xb70, 0x10, 9, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PIN_FIELD16(249, 249, 0x140, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PIN_FIELD16(250, 250, 0x130, 0x10, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PIN_FIELD16(251, 251, 0x130, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PIN_FIELD16(252, 252, 0x130, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PIN_FIELD16(253, 253, 0x130, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PIN_FIELD16(254, 254, 0xf40, 0x10, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PIN_FIELD16(255, 255, 0xf40, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PIN_FIELD16(256, 256, 0xf40, 0x10, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PIN_FIELD16(257, 257, 0xf40, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PIN_FIELD16(258, 258, 0xcb0, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PIN_FIELD16(259, 259, 0xc90, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PIN_FIELD16(260, 260, 0x3a0, 0x10, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PIN_FIELD16(261, 261, 0x0b0, 0x10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINS_FIELD16(262, 277, 0xb70, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PIN_FIELD16(278, 278, 0xb70, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct mtk_pin_field_calc mt7623_pin_pullen_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PIN_FIELD16(0, 278, 0x150, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const struct mtk_pin_field_calc mt7623_pin_pullsel_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PIN_FIELD16(0, 278, 0x280, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct mtk_pin_field_calc mt7623_pin_drv_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINS_FIELD16(0, 6, 0xf50, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINS_FIELD16(7, 9, 0xf50, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINS_FIELD16(10, 13, 0xf50, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINS_FIELD16(14, 15, 0xf50, 0x10, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINS_FIELD16(16, 17, 0xf60, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINS_FIELD16(18, 21, 0xf60, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINS_FIELD16(22, 26, 0xf60, 0x10, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINS_FIELD16(27, 29, 0xf60, 0x10, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINS_FIELD16(30, 32, 0xf60, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINS_FIELD16(33, 37, 0xf70, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PIN_FIELD16(38, 38, 0xf70, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINS_FIELD16(39, 42, 0xf70, 0x10, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINS_FIELD16(43, 45, 0xf70, 0x10, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINS_FIELD16(47, 48, 0xf80, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PIN_FIELD16(49, 49, 0xf80, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINS_FIELD16(50, 52, 0xf70, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINS_FIELD16(53, 56, 0xf80, 0x10, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINS_FIELD16(60, 62, 0xf90, 0x10, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINS_FIELD16(63, 65, 0xf90, 0x10, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINS_FIELD16(66, 71, 0xfa0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINS_FIELD16(72, 74, 0xf80, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PIN_FIELD16(85, 85, 0xda0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PIN_FIELD16(86, 86, 0xd90, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINS_FIELD16(87, 90, 0xdb0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PIN_FIELD16(105, 105, 0xd40, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PIN_FIELD16(106, 106, 0xd30, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINS_FIELD16(107, 110, 0xd50, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINS_FIELD16(111, 115, 0xce0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PIN_FIELD16(116, 116, 0xcd0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PIN_FIELD16(117, 117, 0xcc0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINS_FIELD16(118, 121, 0xce0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PIN_FIELD16(126, 126, 0xf80, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PIN_FIELD16(188, 188, 0xf70, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINS_FIELD16(189, 193, 0xfe0, 0x10, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINS_FIELD16(194, 198, 0xfe0, 0x10, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PIN_FIELD16(199, 199, 0xf50, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINS_FIELD16(200, 202, 0xfd0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINS_FIELD16(203, 207, 0xfd0, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINS_FIELD16(208, 209, 0xfd0, 0x10, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PIN_FIELD16(210, 210, 0xfd0, 0x10, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINS_FIELD16(211, 235, 0xff0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINS_FIELD16(236, 241, 0xff0, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINS_FIELD16(242, 243, 0xff0, 0x10, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PIN_FIELD16(248, 248, 0xf00, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINS_FIELD16(249, 256, 0xfc0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PIN_FIELD16(257, 257, 0xce0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PIN_FIELD16(258, 258, 0xcb0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PIN_FIELD16(259, 259, 0xc90, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PIN_FIELD16(260, 260, 0x3a0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PIN_FIELD16(261, 261, 0xd50, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINS_FIELD16(262, 277, 0xf00, 0x10, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PIN_FIELD16(278, 278, 0xf70, 0x10, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct mtk_pin_field_calc mt7623_pin_tdsel_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINS_FIELD16(262, 276, 0x4c0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct mtk_pin_field_calc mt7623_pin_pupd_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* MSDC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PIN_FIELD16(111, 111, 0xd00, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PIN_FIELD16(112, 112, 0xd00, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PIN_FIELD16(113, 113, 0xd00, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PIN_FIELD16(114, 114, 0xd00, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PIN_FIELD16(115, 115, 0xd10, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PIN_FIELD16(116, 116, 0xcd0, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PIN_FIELD16(117, 117, 0xcc0, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PIN_FIELD16(118, 118, 0xcf0, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PIN_FIELD16(119, 119, 0xcf0, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PIN_FIELD16(120, 120, 0xcf0, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PIN_FIELD16(121, 121, 0xcf0, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* MSDC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PIN_FIELD16(105, 105, 0xd40, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PIN_FIELD16(106, 106, 0xd30, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PIN_FIELD16(107, 107, 0xd60, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PIN_FIELD16(108, 108, 0xd60, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PIN_FIELD16(109, 109, 0xd60, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PIN_FIELD16(110, 110, 0xc60, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* MSDC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PIN_FIELD16(85, 85, 0xda0, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PIN_FIELD16(86, 86, 0xd90, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PIN_FIELD16(87, 87, 0xdc0, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PIN_FIELD16(88, 88, 0xdc0, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PIN_FIELD16(89, 89, 0xdc0, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PIN_FIELD16(90, 90, 0xdc0, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* MSDC0E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PIN_FIELD16(249, 249, 0x140, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PIN_FIELD16(250, 250, 0x130, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PIN_FIELD16(251, 251, 0x130, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PIN_FIELD16(252, 252, 0x130, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PIN_FIELD16(253, 253, 0x130, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PIN_FIELD16(254, 254, 0xf40, 0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PIN_FIELD16(255, 255, 0xf40, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PIN_FIELD16(256, 256, 0xf40, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PIN_FIELD16(257, 257, 0xf40, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PIN_FIELD16(258, 258, 0xcb0, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PIN_FIELD16(259, 259, 0xc90, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PIN_FIELD16(261, 261, 0x140, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct mtk_pin_field_calc mt7623_pin_r1_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* MSDC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PIN_FIELD16(111, 111, 0xd00, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PIN_FIELD16(112, 112, 0xd00, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PIN_FIELD16(113, 113, 0xd00, 0x10, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PIN_FIELD16(114, 114, 0xd00, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PIN_FIELD16(115, 115, 0xd10, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PIN_FIELD16(116, 116, 0xcd0, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PIN_FIELD16(117, 117, 0xcc0, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PIN_FIELD16(118, 118, 0xcf0, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PIN_FIELD16(119, 119, 0xcf0, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PIN_FIELD16(120, 120, 0xcf0, 0x10, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PIN_FIELD16(121, 121, 0xcf0, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* MSDC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PIN_FIELD16(105, 105, 0xd40, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PIN_FIELD16(106, 106, 0xd30, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PIN_FIELD16(107, 107, 0xd60, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PIN_FIELD16(108, 108, 0xd60, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PIN_FIELD16(109, 109, 0xd60, 0x10, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PIN_FIELD16(110, 110, 0xc60, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* MSDC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PIN_FIELD16(85, 85, 0xda0, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PIN_FIELD16(86, 86, 0xd90, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PIN_FIELD16(87, 87, 0xdc0, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PIN_FIELD16(88, 88, 0xdc0, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PIN_FIELD16(89, 89, 0xdc0, 0x10, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PIN_FIELD16(90, 90, 0xdc0, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* MSDC0E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PIN_FIELD16(249, 249, 0x140, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PIN_FIELD16(250, 250, 0x130, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PIN_FIELD16(251, 251, 0x130, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PIN_FIELD16(252, 252, 0x130, 0x10, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PIN_FIELD16(253, 253, 0x130, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PIN_FIELD16(254, 254, 0xf40, 0x10, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PIN_FIELD16(255, 255, 0xf40, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PIN_FIELD16(256, 256, 0xf40, 0x10, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PIN_FIELD16(257, 257, 0xf40, 0x10, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PIN_FIELD16(258, 258, 0xcb0, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PIN_FIELD16(259, 259, 0xc90, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PIN_FIELD16(261, 261, 0x140, 0x10, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const struct mtk_pin_field_calc mt7623_pin_r0_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* MSDC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PIN_FIELD16(111, 111, 0xd00, 0x10, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PIN_FIELD16(112, 112, 0xd00, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PIN_FIELD16(113, 113, 0xd00, 0x10, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PIN_FIELD16(114, 114, 0xd00, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PIN_FIELD16(115, 115, 0xd10, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PIN_FIELD16(116, 116, 0xcd0, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PIN_FIELD16(117, 117, 0xcc0, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PIN_FIELD16(118, 118, 0xcf0, 0x10, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PIN_FIELD16(119, 119, 0xcf0, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PIN_FIELD16(120, 120, 0xcf0, 0x10, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PIN_FIELD16(121, 121, 0xcf0, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* MSDC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PIN_FIELD16(105, 105, 0xd40, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PIN_FIELD16(106, 106, 0xd30, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PIN_FIELD16(107, 107, 0xd60, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PIN_FIELD16(108, 108, 0xd60, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PIN_FIELD16(109, 109, 0xd60, 0x10, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PIN_FIELD16(110, 110, 0xc60, 0x10, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* MSDC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PIN_FIELD16(85, 85, 0xda0, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PIN_FIELD16(86, 86, 0xd90, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PIN_FIELD16(87, 87, 0xdc0, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PIN_FIELD16(88, 88, 0xdc0, 0x10, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PIN_FIELD16(89, 89, 0xdc0, 0x10, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PIN_FIELD16(90, 90, 0xdc0, 0x10, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* MSDC0E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PIN_FIELD16(249, 249, 0x140, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PIN_FIELD16(250, 250, 0x130, 0x10, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PIN_FIELD16(251, 251, 0x130, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PIN_FIELD16(252, 252, 0x130, 0x10, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PIN_FIELD16(253, 253, 0x130, 0x10, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PIN_FIELD16(254, 254, 0xf40, 0x10, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PIN_FIELD16(255, 255, 0xf40, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PIN_FIELD16(256, 256, 0xf40, 0x10, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PIN_FIELD16(257, 257, 0xf40, 0x10, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PIN_FIELD16(258, 258, 0xcb0, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PIN_FIELD16(259, 259, 0xc90, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PIN_FIELD16(261, 261, 0x140, 0x10, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct mtk_pin_reg_calc mt7623_reg_cals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7623_pin_di_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7623_pin_do_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7623_pin_smt_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) [PINCTRL_PIN_REG_PULLSEL] = MTK_RANGE(mt7623_pin_pullsel_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) [PINCTRL_PIN_REG_PULLEN] = MTK_RANGE(mt7623_pin_pullen_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7623_pin_drv_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7623_pin_tdsel_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7623_pin_ies_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7623_pin_pupd_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7623_pin_r0_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7623_pin_r1_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const struct mtk_pin_desc mt7623_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MT7623_PIN(0, "PWRAP_SPI0_MI", 148, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MT7623_PIN(1, "PWRAP_SPI0_MO", 149, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MT7623_PIN(2, "PWRAP_INT", 150, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MT7623_PIN(3, "PWRAP_SPI0_CK", 151, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MT7623_PIN(4, "PWRAP_SPI0_CSN", 152, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MT7623_PIN(5, "PWRAP_SPI0_CK2", 153, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MT7623_PIN(6, "PWRAP_SPI0_CSN2", 154, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MT7623_PIN(7, "SPI1_CSN", 155, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MT7623_PIN(8, "SPI1_MI", 156, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MT7623_PIN(9, "SPI1_MO", 157, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MT7623_PIN(10, "RTC32K_CK", 158, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MT7623_PIN(11, "WATCHDOG", 159, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MT7623_PIN(12, "SRCLKENA", 160, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MT7623_PIN(13, "SRCLKENAI", 161, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MT7623_PIN(14, "URXD2", 162, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MT7623_PIN(15, "UTXD2", 163, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MT7623_PIN(16, "I2S5_DATA_IN", 164, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MT7623_PIN(17, "I2S5_BCK", 165, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MT7623_PIN(18, "PCM_CLK", 166, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MT7623_PIN(19, "PCM_SYNC", 167, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MT7623_PIN(20, "PCM_RX", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MT7623_PIN(21, "PCM_TX", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MT7623_PIN(22, "EINT0", 0, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MT7623_PIN(23, "EINT1", 1, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MT7623_PIN(24, "EINT2", 2, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MT7623_PIN(25, "EINT3", 3, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MT7623_PIN(26, "EINT4", 4, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MT7623_PIN(27, "EINT5", 5, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MT7623_PIN(28, "EINT6", 6, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MT7623_PIN(29, "EINT7", 7, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MT7623_PIN(30, "I2S5_LRCK", 12, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MT7623_PIN(31, "I2S5_MCLK", 13, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MT7623_PIN(32, "I2S5_DATA", 14, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MT7623_PIN(33, "I2S1_DATA", 15, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MT7623_PIN(34, "I2S1_DATA_IN", 16, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MT7623_PIN(35, "I2S1_BCK", 17, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MT7623_PIN(36, "I2S1_LRCK", 18, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MT7623_PIN(37, "I2S1_MCLK", 19, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MT7623_PIN(38, "I2S2_DATA", 20, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MT7623_PIN(39, "JTMS", 21, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MT7623_PIN(40, "JTCK", 22, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MT7623_PIN(41, "JTDI", 23, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MT7623_PIN(42, "JTDO", 24, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MT7623_PIN(43, "NCLE", 25, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MT7623_PIN(44, "NCEB1", 26, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MT7623_PIN(45, "NCEB0", 27, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MT7623_PIN(46, "IR", 28, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MT7623_PIN(47, "NREB", 29, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MT7623_PIN(48, "NRNB", 30, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MT7623_PIN(49, "I2S0_DATA", 31, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MT7623_PIN(50, "I2S2_BCK", 32, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MT7623_PIN(51, "I2S2_DATA_IN", 33, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MT7623_PIN(52, "I2S2_LRCK", 34, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MT7623_PIN(53, "SPI0_CSN", 35, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MT7623_PIN(54, "SPI0_CK", 36, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MT7623_PIN(55, "SPI0_MI", 37, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MT7623_PIN(56, "SPI0_MO", 38, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MT7623_PIN(57, "SDA1", 39, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MT7623_PIN(58, "SCL1", 40, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MT7623_PIN(59, "RAMBUF_I_CLK", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MT7623_PIN(60, "WB_RSTB", 41, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MT7623_PIN(61, "F2W_DATA", 42, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MT7623_PIN(62, "F2W_CLK", 43, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MT7623_PIN(63, "WB_SCLK", 44, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MT7623_PIN(64, "WB_SDATA", 45, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MT7623_PIN(65, "WB_SEN", 46, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MT7623_PIN(66, "WB_CRTL0", 47, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MT7623_PIN(67, "WB_CRTL1", 48, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MT7623_PIN(68, "WB_CRTL2", 49, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MT7623_PIN(69, "WB_CRTL3", 50, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MT7623_PIN(70, "WB_CRTL4", 51, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MT7623_PIN(71, "WB_CRTL5", 52, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MT7623_PIN(72, "I2S0_DATA_IN", 53, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MT7623_PIN(73, "I2S0_LRCK", 54, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MT7623_PIN(74, "I2S0_BCK", 55, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MT7623_PIN(75, "SDA0", 56, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MT7623_PIN(76, "SCL0", 57, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MT7623_PIN(77, "SDA2", 58, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MT7623_PIN(78, "SCL2", 59, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MT7623_PIN(79, "URXD0", 60, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MT7623_PIN(80, "UTXD0", 61, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MT7623_PIN(81, "URXD1", 62, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MT7623_PIN(82, "UTXD1", 63, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MT7623_PIN(83, "LCM_RST", 64, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MT7623_PIN(84, "DSI_TE", 65, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MT7623_PIN(85, "MSDC2_CMD", 66, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MT7623_PIN(86, "MSDC2_CLK", 67, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MT7623_PIN(87, "MSDC2_DAT0", 68, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MT7623_PIN(88, "MSDC2_DAT1", 69, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MT7623_PIN(89, "MSDC2_DAT2", 70, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MT7623_PIN(90, "MSDC2_DAT3", 71, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MT7623_PIN(91, "TDN3", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MT7623_PIN(92, "TDP3", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MT7623_PIN(93, "TDN2", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MT7623_PIN(94, "TDP2", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MT7623_PIN(95, "TCN", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MT7623_PIN(96, "TCP", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MT7623_PIN(97, "TDN1", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MT7623_PIN(98, "TDP1", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MT7623_PIN(99, "TDN0", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MT7623_PIN(100, "TDP0", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MT7623_PIN(101, "SPI2_CSN", 74, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MT7623_PIN(102, "SPI2_MI", 75, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) MT7623_PIN(103, "SPI2_MO", 76, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MT7623_PIN(104, "SPI2_CLK", 77, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MT7623_PIN(105, "MSDC1_CMD", 78, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MT7623_PIN(106, "MSDC1_CLK", 79, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MT7623_PIN(107, "MSDC1_DAT0", 80, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MT7623_PIN(108, "MSDC1_DAT1", 81, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MT7623_PIN(109, "MSDC1_DAT2", 82, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MT7623_PIN(110, "MSDC1_DAT3", 83, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MT7623_PIN(111, "MSDC0_DAT7", 84, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MT7623_PIN(112, "MSDC0_DAT6", 85, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MT7623_PIN(113, "MSDC0_DAT5", 86, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MT7623_PIN(114, "MSDC0_DAT4", 87, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MT7623_PIN(115, "MSDC0_RSTB", 88, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MT7623_PIN(116, "MSDC0_CMD", 89, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MT7623_PIN(117, "MSDC0_CLK", 90, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MT7623_PIN(118, "MSDC0_DAT3", 91, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MT7623_PIN(119, "MSDC0_DAT2", 92, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MT7623_PIN(120, "MSDC0_DAT1", 93, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MT7623_PIN(121, "MSDC0_DAT0", 94, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MT7623_PIN(122, "CEC", 95, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MT7623_PIN(123, "HTPLG", 96, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MT7623_PIN(124, "HDMISCK", 97, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MT7623_PIN(125, "HDMISD", 98, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MT7623_PIN(126, "I2S0_MCLK", 99, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MT7623_PIN(127, "RAMBUF_IDATA0", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MT7623_PIN(128, "RAMBUF_IDATA1", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MT7623_PIN(129, "RAMBUF_IDATA2", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MT7623_PIN(130, "RAMBUF_IDATA3", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MT7623_PIN(131, "RAMBUF_IDATA4", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MT7623_PIN(132, "RAMBUF_IDATA5", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MT7623_PIN(133, "RAMBUF_IDATA6", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MT7623_PIN(134, "RAMBUF_IDATA7", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MT7623_PIN(135, "RAMBUF_IDATA8", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MT7623_PIN(136, "RAMBUF_IDATA9", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MT7623_PIN(137, "RAMBUF_IDATA10", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MT7623_PIN(138, "RAMBUF_IDATA11", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MT7623_PIN(139, "RAMBUF_IDATA12", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MT7623_PIN(140, "RAMBUF_IDATA13", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MT7623_PIN(141, "RAMBUF_IDATA14", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MT7623_PIN(142, "RAMBUF_IDATA15", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MT7623_PIN(143, "RAMBUF_ODATA0", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MT7623_PIN(144, "RAMBUF_ODATA1", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MT7623_PIN(145, "RAMBUF_ODATA2", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MT7623_PIN(146, "RAMBUF_ODATA3", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MT7623_PIN(147, "RAMBUF_ODATA4", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MT7623_PIN(148, "RAMBUF_ODATA5", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MT7623_PIN(149, "RAMBUF_ODATA6", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MT7623_PIN(150, "RAMBUF_ODATA7", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MT7623_PIN(151, "RAMBUF_ODATA8", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MT7623_PIN(152, "RAMBUF_ODATA9", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MT7623_PIN(153, "RAMBUF_ODATA10", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MT7623_PIN(154, "RAMBUF_ODATA11", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MT7623_PIN(155, "RAMBUF_ODATA12", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MT7623_PIN(156, "RAMBUF_ODATA13", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MT7623_PIN(157, "RAMBUF_ODATA14", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MT7623_PIN(158, "RAMBUF_ODATA15", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MT7623_PIN(159, "RAMBUF_BE0", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MT7623_PIN(160, "RAMBUF_BE1", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) MT7623_PIN(161, "AP2PT_INT", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) MT7623_PIN(162, "AP2PT_INT_CLR", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) MT7623_PIN(163, "PT2AP_INT", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MT7623_PIN(164, "PT2AP_INT_CLR", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) MT7623_PIN(165, "AP2UP_INT", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) MT7623_PIN(166, "AP2UP_INT_CLR", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) MT7623_PIN(167, "UP2AP_INT", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MT7623_PIN(168, "UP2AP_INT_CLR", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MT7623_PIN(169, "RAMBUF_ADDR0", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MT7623_PIN(170, "RAMBUF_ADDR1", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) MT7623_PIN(171, "RAMBUF_ADDR2", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) MT7623_PIN(172, "RAMBUF_ADDR3", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) MT7623_PIN(173, "RAMBUF_ADDR4", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MT7623_PIN(174, "RAMBUF_ADDR5", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) MT7623_PIN(175, "RAMBUF_ADDR6", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) MT7623_PIN(176, "RAMBUF_ADDR7", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) MT7623_PIN(177, "RAMBUF_ADDR8", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) MT7623_PIN(178, "RAMBUF_ADDR9", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) MT7623_PIN(179, "RAMBUF_ADDR10", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MT7623_PIN(180, "RAMBUF_RW", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MT7623_PIN(181, "RAMBUF_LAST", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MT7623_PIN(182, "RAMBUF_HP", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) MT7623_PIN(183, "RAMBUF_REQ", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) MT7623_PIN(184, "RAMBUF_ALE", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MT7623_PIN(185, "RAMBUF_DLE", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MT7623_PIN(186, "RAMBUF_WDLE", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MT7623_PIN(187, "RAMBUF_O_CLK", EINT_NA, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MT7623_PIN(188, "I2S2_MCLK", 100, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MT7623_PIN(189, "I2S3_DATA", 101, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MT7623_PIN(190, "I2S3_DATA_IN", 102, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MT7623_PIN(191, "I2S3_BCK", 103, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) MT7623_PIN(192, "I2S3_LRCK", 104, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MT7623_PIN(193, "I2S3_MCLK", 105, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) MT7623_PIN(194, "I2S4_DATA", 106, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) MT7623_PIN(195, "I2S4_DATA_IN", 107, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MT7623_PIN(196, "I2S4_BCK", 108, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MT7623_PIN(197, "I2S4_LRCK", 109, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MT7623_PIN(198, "I2S4_MCLK", 110, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MT7623_PIN(199, "SPI1_CLK", 111, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MT7623_PIN(200, "SPDIF_OUT", 112, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) MT7623_PIN(201, "SPDIF_IN0", 113, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MT7623_PIN(202, "SPDIF_IN1", 114, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MT7623_PIN(203, "PWM0", 115, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) MT7623_PIN(204, "PWM1", 116, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) MT7623_PIN(205, "PWM2", 117, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MT7623_PIN(206, "PWM3", 118, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) MT7623_PIN(207, "PWM4", 119, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) MT7623_PIN(208, "AUD_EXT_CK1", 120, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) MT7623_PIN(209, "AUD_EXT_CK2", 121, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) MT7623_PIN(210, "AUD_CLOCK", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) MT7623_PIN(211, "DVP_RESET", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) MT7623_PIN(212, "DVP_CLOCK", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) MT7623_PIN(213, "DVP_CS", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MT7623_PIN(214, "DVP_CK", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MT7623_PIN(215, "DVP_DI", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MT7623_PIN(216, "DVP_DO", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MT7623_PIN(217, "AP_CS", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MT7623_PIN(218, "AP_CK", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MT7623_PIN(219, "AP_DI", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MT7623_PIN(220, "AP_DO", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MT7623_PIN(221, "DVD_BCLK", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) MT7623_PIN(222, "T8032_CLK", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MT7623_PIN(223, "AP_BCLK", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MT7623_PIN(224, "HOST_CS", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MT7623_PIN(225, "HOST_CK", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MT7623_PIN(226, "HOST_DO0", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) MT7623_PIN(227, "HOST_DO1", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) MT7623_PIN(228, "SLV_CS", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) MT7623_PIN(229, "SLV_CK", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) MT7623_PIN(230, "SLV_DI0", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) MT7623_PIN(231, "SLV_DI1", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) MT7623_PIN(232, "AP2DSP_INT", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) MT7623_PIN(233, "AP2DSP_INT_CLR", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MT7623_PIN(234, "DSP2AP_INT", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) MT7623_PIN(235, "DSP2AP_INT_CLR", EINT_NA, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) MT7623_PIN(236, "EXT_SDIO3", 122, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) MT7623_PIN(237, "EXT_SDIO2", 123, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) MT7623_PIN(238, "EXT_SDIO1", 124, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) MT7623_PIN(239, "EXT_SDIO0", 125, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) MT7623_PIN(240, "EXT_XCS", 126, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) MT7623_PIN(241, "EXT_SCK", 127, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) MT7623_PIN(242, "URTS2", 128, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) MT7623_PIN(243, "UCTS2", 129, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) MT7623_PIN(244, "HDMI_SDA_RX", 130, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) MT7623_PIN(245, "HDMI_SCL_RX", 131, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) MT7623_PIN(246, "MHL_SENCE", 132, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) MT7623_PIN(247, "HDMI_HPD_CBUS_RX", 69, DRV_FIXED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) MT7623_PIN(248, "HDMI_TESTOUTP_RX", 133, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) MT7623_PIN(249, "MSDC0E_RSTB", 134, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) MT7623_PIN(250, "MSDC0E_DAT7", 135, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) MT7623_PIN(251, "MSDC0E_DAT6", 136, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) MT7623_PIN(252, "MSDC0E_DAT5", 137, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) MT7623_PIN(253, "MSDC0E_DAT4", 138, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) MT7623_PIN(254, "MSDC0E_DAT3", 139, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) MT7623_PIN(255, "MSDC0E_DAT2", 140, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) MT7623_PIN(256, "MSDC0E_DAT1", 141, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) MT7623_PIN(257, "MSDC0E_DAT0", 142, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MT7623_PIN(258, "MSDC0E_CMD", 143, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MT7623_PIN(259, "MSDC0E_CLK", 144, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MT7623_PIN(260, "MSDC0E_DSL", 145, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) MT7623_PIN(261, "MSDC1_INS", 146, DRV_GRP4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) MT7623_PIN(262, "G2_TXEN", 8, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) MT7623_PIN(263, "G2_TXD3", 9, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) MT7623_PIN(264, "G2_TXD2", 10, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) MT7623_PIN(265, "G2_TXD1", 11, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) MT7623_PIN(266, "G2_TXD0", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) MT7623_PIN(267, "G2_TXC", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) MT7623_PIN(268, "G2_RXC", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) MT7623_PIN(269, "G2_RXD0", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) MT7623_PIN(270, "G2_RXD1", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) MT7623_PIN(271, "G2_RXD2", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MT7623_PIN(272, "G2_RXD3", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) MT7623_PIN(273, "ESW_INT", 168, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MT7623_PIN(274, "G2_RXDV", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) MT7623_PIN(275, "MDC", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) MT7623_PIN(276, "MDIO", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) MT7623_PIN(277, "ESW_RST", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) MT7623_PIN(278, "JTAG_RESET", 147, DRV_GRP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MT7623_PIN(279, "USB3_RES_BOND", EINT_NA, DRV_GRP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* List all groups consisting of these pins dedicated to the enablement of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * certain hardware block and the corresponding mode for all of the pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * The hardware probably has multiple combinations of these pinouts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* AUDIO EXT CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int mt7623_aud_ext_clk0_pins[] = { 208, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int mt7623_aud_ext_clk0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int mt7623_aud_ext_clk1_pins[] = { 209, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int mt7623_aud_ext_clk1_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* DISP PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int mt7623_disp_pwm_0_pins[] = { 72, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int mt7623_disp_pwm_0_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int mt7623_disp_pwm_1_pins[] = { 203, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int mt7623_disp_pwm_1_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int mt7623_disp_pwm_2_pins[] = { 208, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int mt7623_disp_pwm_2_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* ESW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int mt7623_esw_int_pins[] = { 273, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int mt7623_esw_int_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static int mt7623_esw_rst_pins[] = { 277, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int mt7623_esw_rst_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* EPHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static int mt7623_ephy_pins[] = { 262, 263, 264, 265, 266, 267, 268,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 269, 270, 271, 272, 274, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static int mt7623_ephy_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* EXT_SDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int mt7623_ext_sdio_pins[] = { 236, 237, 238, 239, 240, 241, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static int mt7623_ext_sdio_funcs[] = { 1, 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* HDMI RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int mt7623_hdmi_rx_pins[] = { 247, 248, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int mt7623_hdmi_rx_funcs[] = { 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static int mt7623_hdmi_rx_i2c_pins[] = { 244, 245, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int mt7623_hdmi_rx_i2c_funcs[] = { 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* HDMI TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int mt7623_hdmi_cec_pins[] = { 122, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int mt7623_hdmi_cec_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static int mt7623_hdmi_htplg_pins[] = { 123, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static int mt7623_hdmi_htplg_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int mt7623_hdmi_i2c_pins[] = { 124, 125, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static int mt7623_hdmi_i2c_funcs[] = { 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static int mt7623_i2c0_pins[] = { 75, 76, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static int mt7623_i2c0_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int mt7623_i2c1_0_pins[] = { 57, 58, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int mt7623_i2c1_0_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int mt7623_i2c1_1_pins[] = { 242, 243, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int mt7623_i2c1_1_funcs[] = { 4, 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static int mt7623_i2c1_2_pins[] = { 85, 86, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int mt7623_i2c1_2_funcs[] = { 3, 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static int mt7623_i2c1_3_pins[] = { 105, 106, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static int mt7623_i2c1_3_funcs[] = { 3, 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int mt7623_i2c1_4_pins[] = { 124, 125, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static int mt7623_i2c1_4_funcs[] = { 4, 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static int mt7623_i2c2_0_pins[] = { 77, 78, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static int mt7623_i2c2_0_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int mt7623_i2c2_1_pins[] = { 89, 90, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static int mt7623_i2c2_1_funcs[] = { 3, 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int mt7623_i2c2_2_pins[] = { 109, 110, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int mt7623_i2c2_2_funcs[] = { 3, 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int mt7623_i2c2_3_pins[] = { 122, 123, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int mt7623_i2c2_3_funcs[] = { 4, 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int mt7623_i2s0_pins[] = { 49, 72, 73, 74, 126, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static int mt7623_i2s0_funcs[] = { 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static int mt7623_i2s1_pins[] = { 33, 34, 35, 36, 37, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static int mt7623_i2s1_funcs[] = { 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int mt7623_i2s2_bclk_lrclk_mclk_pins[] = { 50, 52, 188, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static int mt7623_i2s2_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int mt7623_i2s2_data_in_pins[] = { 51, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static int mt7623_i2s2_data_in_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static int mt7623_i2s2_data_0_pins[] = { 203, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int mt7623_i2s2_data_0_funcs[] = { 9, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static int mt7623_i2s2_data_1_pins[] = { 38, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int mt7623_i2s2_data_1_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int mt7623_i2s3_bclk_lrclk_mclk_pins[] = { 191, 192, 193, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int mt7623_i2s3_bclk_lrclk_mclk_funcs[] = { 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int mt7623_i2s3_data_in_pins[] = { 190, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int mt7623_i2s3_data_in_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static int mt7623_i2s3_data_0_pins[] = { 204, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int mt7623_i2s3_data_0_funcs[] = { 9, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int mt7623_i2s3_data_1_pins[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int mt7623_i2s3_data_1_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static int mt7623_i2s4_pins[] = { 194, 195, 196, 197, 198, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int mt7623_i2s4_funcs[] = { 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int mt7623_i2s5_pins[] = { 16, 17, 30, 31, 32, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int mt7623_i2s5_funcs[] = { 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int mt7623_ir_pins[] = { 46, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static int mt7623_ir_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int mt7623_mipi_tx_pins[] = { 91, 92, 93, 94, 95, 96, 97, 98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) 99, 100, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static int mt7623_mipi_tx_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static int mt7623_dsi_te_pins[] = { 84, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int mt7623_dsi_te_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int mt7623_lcm_rst_pins[] = { 83, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static int mt7623_lcm_rst_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* MDC/MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static int mt7623_mdc_mdio_pins[] = { 275, 276, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static int mt7623_mdc_mdio_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* MSDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int mt7623_msdc0_pins[] = { 111, 112, 113, 114, 115, 116, 117, 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 119, 120, 121, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static int mt7623_msdc0_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int mt7623_msdc1_pins[] = { 105, 106, 107, 108, 109, 110, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int mt7623_msdc1_funcs[] = { 1, 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static int mt7623_msdc1_ins_pins[] = { 261, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static int mt7623_msdc1_ins_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static int mt7623_msdc1_wp_0_pins[] = { 29, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int mt7623_msdc1_wp_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int mt7623_msdc1_wp_1_pins[] = { 55, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static int mt7623_msdc1_wp_1_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int mt7623_msdc1_wp_2_pins[] = { 209, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int mt7623_msdc1_wp_2_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int mt7623_msdc2_pins[] = { 85, 86, 87, 88, 89, 90, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static int mt7623_msdc2_funcs[] = { 1, 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int mt7623_msdc3_pins[] = { 249, 250, 251, 252, 253, 254, 255, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) 257, 258, 259, 260, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int mt7623_msdc3_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static int mt7623_nandc_pins[] = { 43, 47, 48, 111, 112, 113, 114, 115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) 116, 117, 118, 119, 120, 121, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int mt7623_nandc_funcs[] = { 1, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 4, 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int mt7623_nandc_ceb0_pins[] = { 45, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int mt7623_nandc_ceb0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int mt7623_nandc_ceb1_pins[] = { 44, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int mt7623_nandc_ceb1_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static int mt7623_rtc_pins[] = { 10, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static int mt7623_rtc_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* OTG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static int mt7623_otg_iddig0_0_pins[] = { 29, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int mt7623_otg_iddig0_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static int mt7623_otg_iddig0_1_pins[] = { 44, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int mt7623_otg_iddig0_1_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int mt7623_otg_iddig0_2_pins[] = { 236, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int mt7623_otg_iddig0_2_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static int mt7623_otg_iddig1_0_pins[] = { 27, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static int mt7623_otg_iddig1_0_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int mt7623_otg_iddig1_1_pins[] = { 47, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int mt7623_otg_iddig1_1_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static int mt7623_otg_iddig1_2_pins[] = { 238, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static int mt7623_otg_iddig1_2_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int mt7623_otg_drv_vbus0_0_pins[] = { 28, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int mt7623_otg_drv_vbus0_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int mt7623_otg_drv_vbus0_1_pins[] = { 45, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int mt7623_otg_drv_vbus0_1_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static int mt7623_otg_drv_vbus0_2_pins[] = { 237, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int mt7623_otg_drv_vbus0_2_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static int mt7623_otg_drv_vbus1_0_pins[] = { 26, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static int mt7623_otg_drv_vbus1_0_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static int mt7623_otg_drv_vbus1_1_pins[] = { 48, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int mt7623_otg_drv_vbus1_1_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static int mt7623_otg_drv_vbus1_2_pins[] = { 239, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static int mt7623_otg_drv_vbus1_2_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int mt7623_pcie0_0_perst_pins[] = { 208, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int mt7623_pcie0_0_perst_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static int mt7623_pcie0_1_perst_pins[] = { 22, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int mt7623_pcie0_1_perst_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static int mt7623_pcie1_0_perst_pins[] = { 209, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static int mt7623_pcie1_0_perst_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static int mt7623_pcie1_1_perst_pins[] = { 23, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static int mt7623_pcie1_1_perst_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int mt7623_pcie2_0_perst_pins[] = { 24, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static int mt7623_pcie2_0_perst_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static int mt7623_pcie2_1_perst_pins[] = { 29, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int mt7623_pcie2_1_perst_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static int mt7623_pcie0_0_wake_pins[] = { 28, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static int mt7623_pcie0_0_wake_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static int mt7623_pcie0_1_wake_pins[] = { 251, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int mt7623_pcie0_1_wake_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int mt7623_pcie1_0_wake_pins[] = { 27, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int mt7623_pcie1_0_wake_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static int mt7623_pcie1_1_wake_pins[] = { 253, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int mt7623_pcie1_1_wake_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static int mt7623_pcie2_0_wake_pins[] = { 26, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int mt7623_pcie2_0_wake_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int mt7623_pcie2_1_wake_pins[] = { 255, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int mt7623_pcie2_1_wake_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static int mt7623_pcie0_clkreq_pins[] = { 250, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int mt7623_pcie0_clkreq_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int mt7623_pcie1_clkreq_pins[] = { 252, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static int mt7623_pcie1_clkreq_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int mt7623_pcie2_clkreq_pins[] = { 254, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int mt7623_pcie2_clkreq_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* the pcie_*_rev are only used for MT7623 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static int mt7623_pcie0_0_rev_perst_pins[] = { 208, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static int mt7623_pcie0_0_rev_perst_funcs[] = { 11, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static int mt7623_pcie0_1_rev_perst_pins[] = { 22, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int mt7623_pcie0_1_rev_perst_funcs[] = { 10, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static int mt7623_pcie1_0_rev_perst_pins[] = { 209, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static int mt7623_pcie1_0_rev_perst_funcs[] = { 11, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int mt7623_pcie1_1_rev_perst_pins[] = { 23, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static int mt7623_pcie1_1_rev_perst_funcs[] = { 10, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static int mt7623_pcie2_0_rev_perst_pins[] = { 24, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static int mt7623_pcie2_0_rev_perst_funcs[] = { 11, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int mt7623_pcie2_1_rev_perst_pins[] = { 29, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int mt7623_pcie2_1_rev_perst_funcs[] = { 14, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* PCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static int mt7623_pcm_clk_0_pins[] = { 18, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static int mt7623_pcm_clk_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static int mt7623_pcm_clk_1_pins[] = { 17, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static int mt7623_pcm_clk_1_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static int mt7623_pcm_clk_2_pins[] = { 35, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int mt7623_pcm_clk_2_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static int mt7623_pcm_clk_3_pins[] = { 50, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static int mt7623_pcm_clk_3_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static int mt7623_pcm_clk_4_pins[] = { 74, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static int mt7623_pcm_clk_4_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static int mt7623_pcm_clk_5_pins[] = { 191, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int mt7623_pcm_clk_5_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static int mt7623_pcm_clk_6_pins[] = { 196, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static int mt7623_pcm_clk_6_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int mt7623_pcm_sync_0_pins[] = { 19, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static int mt7623_pcm_sync_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static int mt7623_pcm_sync_1_pins[] = { 30, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static int mt7623_pcm_sync_1_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static int mt7623_pcm_sync_2_pins[] = { 36, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static int mt7623_pcm_sync_2_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static int mt7623_pcm_sync_3_pins[] = { 52, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int mt7623_pcm_sync_3_funcs[] = { 31, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static int mt7623_pcm_sync_4_pins[] = { 73, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static int mt7623_pcm_sync_4_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static int mt7623_pcm_sync_5_pins[] = { 192, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static int mt7623_pcm_sync_5_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static int mt7623_pcm_sync_6_pins[] = { 197, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static int mt7623_pcm_sync_6_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static int mt7623_pcm_rx_0_pins[] = { 20, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int mt7623_pcm_rx_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int mt7623_pcm_rx_1_pins[] = { 16, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static int mt7623_pcm_rx_1_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static int mt7623_pcm_rx_2_pins[] = { 34, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static int mt7623_pcm_rx_2_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static int mt7623_pcm_rx_3_pins[] = { 51, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static int mt7623_pcm_rx_3_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static int mt7623_pcm_rx_4_pins[] = { 72, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static int mt7623_pcm_rx_4_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int mt7623_pcm_rx_5_pins[] = { 190, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int mt7623_pcm_rx_5_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static int mt7623_pcm_rx_6_pins[] = { 195, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int mt7623_pcm_rx_6_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int mt7623_pcm_tx_0_pins[] = { 21, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static int mt7623_pcm_tx_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static int mt7623_pcm_tx_1_pins[] = { 32, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static int mt7623_pcm_tx_1_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int mt7623_pcm_tx_2_pins[] = { 33, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static int mt7623_pcm_tx_2_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int mt7623_pcm_tx_3_pins[] = { 38, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int mt7623_pcm_tx_3_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static int mt7623_pcm_tx_4_pins[] = { 49, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int mt7623_pcm_tx_4_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static int mt7623_pcm_tx_5_pins[] = { 189, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static int mt7623_pcm_tx_5_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int mt7623_pcm_tx_6_pins[] = { 194, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static int mt7623_pcm_tx_6_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static int mt7623_pwm_ch1_0_pins[] = { 203, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static int mt7623_pwm_ch1_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static int mt7623_pwm_ch1_1_pins[] = { 208, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int mt7623_pwm_ch1_1_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static int mt7623_pwm_ch1_2_pins[] = { 72, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static int mt7623_pwm_ch1_2_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static int mt7623_pwm_ch1_3_pins[] = { 88, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int mt7623_pwm_ch1_3_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int mt7623_pwm_ch1_4_pins[] = { 108, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int mt7623_pwm_ch1_4_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static int mt7623_pwm_ch2_0_pins[] = { 204, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static int mt7623_pwm_ch2_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int mt7623_pwm_ch2_1_pins[] = { 53, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static int mt7623_pwm_ch2_1_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static int mt7623_pwm_ch2_2_pins[] = { 88, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static int mt7623_pwm_ch2_2_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static int mt7623_pwm_ch2_3_pins[] = { 108, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static int mt7623_pwm_ch2_3_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int mt7623_pwm_ch2_4_pins[] = { 209, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int mt7623_pwm_ch2_4_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static int mt7623_pwm_ch3_0_pins[] = { 205, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static int mt7623_pwm_ch3_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static int mt7623_pwm_ch3_1_pins[] = { 55, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static int mt7623_pwm_ch3_1_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static int mt7623_pwm_ch3_2_pins[] = { 89, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int mt7623_pwm_ch3_2_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static int mt7623_pwm_ch3_3_pins[] = { 109, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static int mt7623_pwm_ch3_3_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static int mt7623_pwm_ch4_0_pins[] = { 206, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static int mt7623_pwm_ch4_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static int mt7623_pwm_ch4_1_pins[] = { 90, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static int mt7623_pwm_ch4_1_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static int mt7623_pwm_ch4_2_pins[] = { 110, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static int mt7623_pwm_ch4_2_funcs[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static int mt7623_pwm_ch4_3_pins[] = { 124, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static int mt7623_pwm_ch4_3_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static int mt7623_pwm_ch5_0_pins[] = { 207, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static int mt7623_pwm_ch5_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static int mt7623_pwm_ch5_1_pins[] = { 125, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static int mt7623_pwm_ch5_1_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* PWRAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static int mt7623_pwrap_pins[] = { 0, 1, 2, 3, 4, 5, 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static int mt7623_pwrap_funcs[] = { 1, 1, 1, 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int mt7623_spdif_in0_0_pins[] = { 56, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static int mt7623_spdif_in0_0_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static int mt7623_spdif_in0_1_pins[] = { 201, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static int mt7623_spdif_in0_1_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static int mt7623_spdif_in1_0_pins[] = { 54, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int mt7623_spdif_in1_0_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int mt7623_spdif_in1_1_pins[] = { 202, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static int mt7623_spdif_in1_1_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static int mt7623_spdif_out_pins[] = { 202, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static int mt7623_spdif_out_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static int mt7623_spi0_pins[] = { 53, 54, 55, 56, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static int mt7623_spi0_funcs[] = { 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static int mt7623_spi1_pins[] = { 7, 199, 8, 9, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static int mt7623_spi1_funcs[] = { 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static int mt7623_spi2_pins[] = { 101, 104, 102, 103, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static int mt7623_spi2_funcs[] = { 1, 1, 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static int mt7623_uart0_0_txd_rxd_pins[] = { 79, 80, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static int mt7623_uart0_0_txd_rxd_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int mt7623_uart0_1_txd_rxd_pins[] = { 87, 88, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static int mt7623_uart0_1_txd_rxd_funcs[] = { 5, 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static int mt7623_uart0_2_txd_rxd_pins[] = { 107, 108, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static int mt7623_uart0_2_txd_rxd_funcs[] = { 5, 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static int mt7623_uart0_3_txd_rxd_pins[] = { 123, 122, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static int mt7623_uart0_3_txd_rxd_funcs[] = { 5, 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static int mt7623_uart0_rts_cts_pins[] = { 22, 23, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static int mt7623_uart0_rts_cts_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static int mt7623_uart1_0_txd_rxd_pins[] = { 81, 82, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static int mt7623_uart1_0_txd_rxd_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static int mt7623_uart1_1_txd_rxd_pins[] = { 89, 90, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static int mt7623_uart1_1_txd_rxd_funcs[] = { 5, 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static int mt7623_uart1_2_txd_rxd_pins[] = { 109, 110, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static int mt7623_uart1_2_txd_rxd_funcs[] = { 5, 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static int mt7623_uart1_rts_cts_pins[] = { 24, 25, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int mt7623_uart1_rts_cts_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static int mt7623_uart2_0_txd_rxd_pins[] = { 14, 15, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static int mt7623_uart2_0_txd_rxd_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static int mt7623_uart2_1_txd_rxd_pins[] = { 200, 201, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static int mt7623_uart2_1_txd_rxd_funcs[] = { 6, 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static int mt7623_uart2_rts_cts_pins[] = { 242, 243, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static int mt7623_uart2_rts_cts_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static int mt7623_uart3_txd_rxd_pins[] = { 242, 243, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int mt7623_uart3_txd_rxd_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int mt7623_uart3_rts_cts_pins[] = { 26, 27, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static int mt7623_uart3_rts_cts_funcs[] = { 1, 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* Watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static int mt7623_watchdog_0_pins[] = { 11, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static int mt7623_watchdog_0_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static int mt7623_watchdog_1_pins[] = { 121, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static int mt7623_watchdog_1_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static const struct group_desc mt7623_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINCTRL_PIN_GROUP("aud_ext_clk0", mt7623_aud_ext_clk0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) PINCTRL_PIN_GROUP("aud_ext_clk1", mt7623_aud_ext_clk1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PINCTRL_PIN_GROUP("dsi_te", mt7623_dsi_te),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PINCTRL_PIN_GROUP("disp_pwm_0", mt7623_disp_pwm_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINCTRL_PIN_GROUP("disp_pwm_1", mt7623_disp_pwm_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PINCTRL_PIN_GROUP("disp_pwm_2", mt7623_disp_pwm_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PINCTRL_PIN_GROUP("ephy", mt7623_ephy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PINCTRL_PIN_GROUP("esw_int", mt7623_esw_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PINCTRL_PIN_GROUP("esw_rst", mt7623_esw_rst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PINCTRL_PIN_GROUP("ext_sdio", mt7623_ext_sdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PINCTRL_PIN_GROUP("hdmi_cec", mt7623_hdmi_cec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PINCTRL_PIN_GROUP("hdmi_htplg", mt7623_hdmi_htplg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PINCTRL_PIN_GROUP("hdmi_i2c", mt7623_hdmi_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) PINCTRL_PIN_GROUP("hdmi_rx", mt7623_hdmi_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) PINCTRL_PIN_GROUP("hdmi_rx_i2c", mt7623_hdmi_rx_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) PINCTRL_PIN_GROUP("i2c0", mt7623_i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PINCTRL_PIN_GROUP("i2c1_0", mt7623_i2c1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PINCTRL_PIN_GROUP("i2c1_1", mt7623_i2c1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) PINCTRL_PIN_GROUP("i2c1_2", mt7623_i2c1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) PINCTRL_PIN_GROUP("i2c1_3", mt7623_i2c1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PINCTRL_PIN_GROUP("i2c1_4", mt7623_i2c1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) PINCTRL_PIN_GROUP("i2c2_0", mt7623_i2c2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PINCTRL_PIN_GROUP("i2c2_1", mt7623_i2c2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PINCTRL_PIN_GROUP("i2c2_2", mt7623_i2c2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PINCTRL_PIN_GROUP("i2c2_3", mt7623_i2c2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) PINCTRL_PIN_GROUP("i2s0", mt7623_i2s0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PINCTRL_PIN_GROUP("i2s1", mt7623_i2s1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PINCTRL_PIN_GROUP("i2s4", mt7623_i2s4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PINCTRL_PIN_GROUP("i2s5", mt7623_i2s5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PINCTRL_PIN_GROUP("i2s2_bclk_lrclk_mclk", mt7623_i2s2_bclk_lrclk_mclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PINCTRL_PIN_GROUP("i2s3_bclk_lrclk_mclk", mt7623_i2s3_bclk_lrclk_mclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PINCTRL_PIN_GROUP("i2s2_data_in", mt7623_i2s2_data_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINCTRL_PIN_GROUP("i2s3_data_in", mt7623_i2s3_data_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PINCTRL_PIN_GROUP("i2s2_data_0", mt7623_i2s2_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) PINCTRL_PIN_GROUP("i2s2_data_1", mt7623_i2s2_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PINCTRL_PIN_GROUP("i2s3_data_0", mt7623_i2s3_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PINCTRL_PIN_GROUP("i2s3_data_1", mt7623_i2s3_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PINCTRL_PIN_GROUP("ir", mt7623_ir),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PINCTRL_PIN_GROUP("lcm_rst", mt7623_lcm_rst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PINCTRL_PIN_GROUP("mdc_mdio", mt7623_mdc_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PINCTRL_PIN_GROUP("mipi_tx", mt7623_mipi_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) PINCTRL_PIN_GROUP("msdc0", mt7623_msdc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) PINCTRL_PIN_GROUP("msdc1", mt7623_msdc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) PINCTRL_PIN_GROUP("msdc1_ins", mt7623_msdc1_ins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) PINCTRL_PIN_GROUP("msdc1_wp_0", mt7623_msdc1_wp_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) PINCTRL_PIN_GROUP("msdc1_wp_1", mt7623_msdc1_wp_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PINCTRL_PIN_GROUP("msdc1_wp_2", mt7623_msdc1_wp_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PINCTRL_PIN_GROUP("msdc2", mt7623_msdc2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PINCTRL_PIN_GROUP("msdc3", mt7623_msdc3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) PINCTRL_PIN_GROUP("nandc", mt7623_nandc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PINCTRL_PIN_GROUP("nandc_ceb0", mt7623_nandc_ceb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PINCTRL_PIN_GROUP("nandc_ceb1", mt7623_nandc_ceb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PINCTRL_PIN_GROUP("otg_iddig0_0", mt7623_otg_iddig0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PINCTRL_PIN_GROUP("otg_iddig0_1", mt7623_otg_iddig0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PINCTRL_PIN_GROUP("otg_iddig0_2", mt7623_otg_iddig0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PINCTRL_PIN_GROUP("otg_iddig1_0", mt7623_otg_iddig1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) PINCTRL_PIN_GROUP("otg_iddig1_1", mt7623_otg_iddig1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) PINCTRL_PIN_GROUP("otg_iddig1_2", mt7623_otg_iddig1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINCTRL_PIN_GROUP("otg_drv_vbus0_0", mt7623_otg_drv_vbus0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PINCTRL_PIN_GROUP("otg_drv_vbus0_1", mt7623_otg_drv_vbus0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PINCTRL_PIN_GROUP("otg_drv_vbus0_2", mt7623_otg_drv_vbus0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PINCTRL_PIN_GROUP("otg_drv_vbus1_0", mt7623_otg_drv_vbus1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PINCTRL_PIN_GROUP("otg_drv_vbus1_1", mt7623_otg_drv_vbus1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINCTRL_PIN_GROUP("otg_drv_vbus1_2", mt7623_otg_drv_vbus1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PINCTRL_PIN_GROUP("pcie0_0_perst", mt7623_pcie0_0_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PINCTRL_PIN_GROUP("pcie0_1_perst", mt7623_pcie0_1_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PINCTRL_PIN_GROUP("pcie1_0_perst", mt7623_pcie1_0_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PINCTRL_PIN_GROUP("pcie1_1_perst", mt7623_pcie1_1_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PINCTRL_PIN_GROUP("pcie0_0_rev_perst", mt7623_pcie0_0_rev_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PINCTRL_PIN_GROUP("pcie0_1_rev_perst", mt7623_pcie0_1_rev_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PINCTRL_PIN_GROUP("pcie1_0_rev_perst", mt7623_pcie1_0_rev_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PINCTRL_PIN_GROUP("pcie1_1_rev_perst", mt7623_pcie1_1_rev_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PINCTRL_PIN_GROUP("pcie2_0_rev_perst", mt7623_pcie2_0_rev_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PINCTRL_PIN_GROUP("pcie2_1_rev_perst", mt7623_pcie2_1_rev_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PINCTRL_PIN_GROUP("pcie2_0_perst", mt7623_pcie2_0_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) PINCTRL_PIN_GROUP("pcie2_1_perst", mt7623_pcie2_1_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) PINCTRL_PIN_GROUP("pcie0_0_wake", mt7623_pcie0_0_wake),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PINCTRL_PIN_GROUP("pcie0_1_wake", mt7623_pcie0_1_wake),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PINCTRL_PIN_GROUP("pcie1_0_wake", mt7623_pcie1_0_wake),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PINCTRL_PIN_GROUP("pcie1_1_wake", mt7623_pcie1_1_wake),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) PINCTRL_PIN_GROUP("pcie2_0_wake", mt7623_pcie2_0_wake),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PINCTRL_PIN_GROUP("pcie2_1_wake", mt7623_pcie2_1_wake),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) PINCTRL_PIN_GROUP("pcie0_clkreq", mt7623_pcie0_clkreq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) PINCTRL_PIN_GROUP("pcie1_clkreq", mt7623_pcie1_clkreq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PINCTRL_PIN_GROUP("pcie2_clkreq", mt7623_pcie2_clkreq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PINCTRL_PIN_GROUP("pcm_clk_0", mt7623_pcm_clk_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) PINCTRL_PIN_GROUP("pcm_clk_1", mt7623_pcm_clk_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) PINCTRL_PIN_GROUP("pcm_clk_2", mt7623_pcm_clk_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PINCTRL_PIN_GROUP("pcm_clk_3", mt7623_pcm_clk_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PINCTRL_PIN_GROUP("pcm_clk_4", mt7623_pcm_clk_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PINCTRL_PIN_GROUP("pcm_clk_5", mt7623_pcm_clk_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PINCTRL_PIN_GROUP("pcm_clk_6", mt7623_pcm_clk_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PINCTRL_PIN_GROUP("pcm_sync_0", mt7623_pcm_sync_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PINCTRL_PIN_GROUP("pcm_sync_1", mt7623_pcm_sync_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PINCTRL_PIN_GROUP("pcm_sync_2", mt7623_pcm_sync_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PINCTRL_PIN_GROUP("pcm_sync_3", mt7623_pcm_sync_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PINCTRL_PIN_GROUP("pcm_sync_4", mt7623_pcm_sync_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINCTRL_PIN_GROUP("pcm_sync_5", mt7623_pcm_sync_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PINCTRL_PIN_GROUP("pcm_sync_6", mt7623_pcm_sync_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PINCTRL_PIN_GROUP("pcm_rx_0", mt7623_pcm_rx_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) PINCTRL_PIN_GROUP("pcm_rx_1", mt7623_pcm_rx_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PINCTRL_PIN_GROUP("pcm_rx_2", mt7623_pcm_rx_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PINCTRL_PIN_GROUP("pcm_rx_3", mt7623_pcm_rx_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PINCTRL_PIN_GROUP("pcm_rx_4", mt7623_pcm_rx_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PINCTRL_PIN_GROUP("pcm_rx_5", mt7623_pcm_rx_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PINCTRL_PIN_GROUP("pcm_rx_6", mt7623_pcm_rx_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PINCTRL_PIN_GROUP("pcm_tx_0", mt7623_pcm_tx_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PINCTRL_PIN_GROUP("pcm_tx_1", mt7623_pcm_tx_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PINCTRL_PIN_GROUP("pcm_tx_2", mt7623_pcm_tx_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PINCTRL_PIN_GROUP("pcm_tx_3", mt7623_pcm_tx_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PINCTRL_PIN_GROUP("pcm_tx_4", mt7623_pcm_tx_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PINCTRL_PIN_GROUP("pcm_tx_5", mt7623_pcm_tx_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PINCTRL_PIN_GROUP("pcm_tx_6", mt7623_pcm_tx_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINCTRL_PIN_GROUP("pwm_ch1_0", mt7623_pwm_ch1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PINCTRL_PIN_GROUP("pwm_ch1_1", mt7623_pwm_ch1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINCTRL_PIN_GROUP("pwm_ch1_2", mt7623_pwm_ch1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) PINCTRL_PIN_GROUP("pwm_ch1_3", mt7623_pwm_ch1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PINCTRL_PIN_GROUP("pwm_ch1_4", mt7623_pwm_ch1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PINCTRL_PIN_GROUP("pwm_ch2_0", mt7623_pwm_ch2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PINCTRL_PIN_GROUP("pwm_ch2_1", mt7623_pwm_ch2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PINCTRL_PIN_GROUP("pwm_ch2_2", mt7623_pwm_ch2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINCTRL_PIN_GROUP("pwm_ch2_3", mt7623_pwm_ch2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) PINCTRL_PIN_GROUP("pwm_ch2_4", mt7623_pwm_ch2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PINCTRL_PIN_GROUP("pwm_ch3_0", mt7623_pwm_ch3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PINCTRL_PIN_GROUP("pwm_ch3_1", mt7623_pwm_ch3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) PINCTRL_PIN_GROUP("pwm_ch3_2", mt7623_pwm_ch3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PINCTRL_PIN_GROUP("pwm_ch3_3", mt7623_pwm_ch3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PINCTRL_PIN_GROUP("pwm_ch4_0", mt7623_pwm_ch4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PINCTRL_PIN_GROUP("pwm_ch4_1", mt7623_pwm_ch4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PINCTRL_PIN_GROUP("pwm_ch4_2", mt7623_pwm_ch4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) PINCTRL_PIN_GROUP("pwm_ch4_3", mt7623_pwm_ch4_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINCTRL_PIN_GROUP("pwm_ch5_0", mt7623_pwm_ch5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PINCTRL_PIN_GROUP("pwm_ch5_1", mt7623_pwm_ch5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) PINCTRL_PIN_GROUP("pwrap", mt7623_pwrap),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PINCTRL_PIN_GROUP("rtc", mt7623_rtc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PINCTRL_PIN_GROUP("spdif_in0_0", mt7623_spdif_in0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINCTRL_PIN_GROUP("spdif_in0_1", mt7623_spdif_in0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINCTRL_PIN_GROUP("spdif_in1_0", mt7623_spdif_in1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PINCTRL_PIN_GROUP("spdif_in1_1", mt7623_spdif_in1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) PINCTRL_PIN_GROUP("spdif_out", mt7623_spdif_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PINCTRL_PIN_GROUP("spi0", mt7623_spi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PINCTRL_PIN_GROUP("spi1", mt7623_spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PINCTRL_PIN_GROUP("spi2", mt7623_spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINCTRL_PIN_GROUP("uart0_0_txd_rxd", mt7623_uart0_0_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PINCTRL_PIN_GROUP("uart0_1_txd_rxd", mt7623_uart0_1_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PINCTRL_PIN_GROUP("uart0_2_txd_rxd", mt7623_uart0_2_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PINCTRL_PIN_GROUP("uart0_3_txd_rxd", mt7623_uart0_3_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) PINCTRL_PIN_GROUP("uart1_0_txd_rxd", mt7623_uart1_0_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PINCTRL_PIN_GROUP("uart1_1_txd_rxd", mt7623_uart1_1_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PINCTRL_PIN_GROUP("uart1_2_txd_rxd", mt7623_uart1_2_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PINCTRL_PIN_GROUP("uart2_0_txd_rxd", mt7623_uart2_0_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINCTRL_PIN_GROUP("uart2_1_txd_rxd", mt7623_uart2_1_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PINCTRL_PIN_GROUP("uart3_txd_rxd", mt7623_uart3_txd_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PINCTRL_PIN_GROUP("uart0_rts_cts", mt7623_uart0_rts_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINCTRL_PIN_GROUP("uart1_rts_cts", mt7623_uart1_rts_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PINCTRL_PIN_GROUP("uart2_rts_cts", mt7623_uart2_rts_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PINCTRL_PIN_GROUP("uart3_rts_cts", mt7623_uart3_rts_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINCTRL_PIN_GROUP("watchdog_0", mt7623_watchdog_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PINCTRL_PIN_GROUP("watchdog_1", mt7623_watchdog_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* Joint those groups owning the same capability in user point of view which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * allows that people tend to use through the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static const char *mt7623_aud_clk_groups[] = { "aud_ext_clk0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) "aud_ext_clk1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static const char *mt7623_disp_pwm_groups[] = { "disp_pwm_0", "disp_pwm_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) "disp_pwm_2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static const char *mt7623_ethernet_groups[] = { "esw_int", "esw_rst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) "ephy", "mdc_mdio", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static const char *mt7623_ext_sdio_groups[] = { "ext_sdio", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static const char *mt7623_hdmi_groups[] = { "hdmi_cec", "hdmi_htplg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) "hdmi_i2c", "hdmi_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) "hdmi_rx_i2c", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static const char *mt7623_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) "i2c1_2", "i2c1_3", "i2c1_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) "i2c2_0", "i2c2_1", "i2c2_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) "i2c2_3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static const char *mt7623_i2s_groups[] = { "i2s0", "i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) "i2s2_bclk_lrclk_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) "i2s3_bclk_lrclk_mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) "i2s4", "i2s5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) "i2s2_data_in", "i2s3_data_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) "i2s2_data_0", "i2s2_data_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) "i2s3_data_0", "i2s3_data_1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static const char *mt7623_ir_groups[] = { "ir", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static const char *mt7623_lcd_groups[] = { "dsi_te", "lcm_rst", "mipi_tx", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static const char *mt7623_msdc_groups[] = { "msdc0", "msdc1", "msdc1_ins",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) "msdc1_wp_0", "msdc1_wp_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) "msdc1_wp_2", "msdc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) "msdc3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static const char *mt7623_nandc_groups[] = { "nandc", "nandc_ceb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) "nandc_ceb1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static const char *mt7623_otg_groups[] = { "otg_iddig0_0", "otg_iddig0_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) "otg_iddig0_2", "otg_iddig1_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) "otg_iddig1_1", "otg_iddig1_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) "otg_drv_vbus0_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) "otg_drv_vbus0_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) "otg_drv_vbus0_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) "otg_drv_vbus1_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) "otg_drv_vbus1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) "otg_drv_vbus1_2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static const char *mt7623_pcie_groups[] = { "pcie0_0_perst", "pcie0_1_perst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) "pcie1_0_perst", "pcie1_1_perst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) "pcie2_0_perst", "pcie2_1_perst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) "pcie0_0_rev_perst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) "pcie0_1_rev_perst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) "pcie1_0_rev_perst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) "pcie1_1_rev_perst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) "pcie2_0_rev_perst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) "pcie2_1_rev_perst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) "pcie0_0_wake", "pcie0_1_wake",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) "pcie2_0_wake", "pcie2_1_wake",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) "pcie0_clkreq", "pcie1_clkreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) "pcie2_clkreq", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static const char *mt7623_pcm_groups[] = { "pcm_clk_0", "pcm_clk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) "pcm_clk_2", "pcm_clk_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) "pcm_clk_4", "pcm_clk_5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) "pcm_clk_6", "pcm_sync_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) "pcm_sync_1", "pcm_sync_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) "pcm_sync_3", "pcm_sync_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) "pcm_sync_5", "pcm_sync_6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) "pcm_rx_0", "pcm_rx_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) "pcm_rx_2", "pcm_rx_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) "pcm_rx_4", "pcm_rx_5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) "pcm_rx_6", "pcm_tx_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) "pcm_tx_1", "pcm_tx_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) "pcm_tx_3", "pcm_tx_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) "pcm_tx_5", "pcm_tx_6", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static const char *mt7623_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) "pwm_ch1_2", "pwm_ch2_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) "pwm_ch2_1", "pwm_ch2_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) "pwm_ch3_0", "pwm_ch3_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) "pwm_ch3_2", "pwm_ch4_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) "pwm_ch4_1", "pwm_ch4_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) "pwm_ch4_3", "pwm_ch5_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) "pwm_ch5_1", "pwm_ch5_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) "pwm_ch6_0", "pwm_ch6_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) "pwm_ch6_2", "pwm_ch6_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) "pwm_ch7_0", "pwm_ch7_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) "pwm_ch7_2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static const char *mt7623_pwrap_groups[] = { "pwrap", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static const char *mt7623_rtc_groups[] = { "rtc", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static const char *mt7623_spi_groups[] = { "spi0", "spi2", "spi2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) static const char *mt7623_spdif_groups[] = { "spdif_in0_0", "spdif_in0_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) "spdif_in1_0", "spdif_in1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) "spdif_out", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static const char *mt7623_uart_groups[] = { "uart0_0_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) "uart0_1_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) "uart0_2_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) "uart0_3_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) "uart1_0_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) "uart1_1_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) "uart1_2_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) "uart2_0_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) "uart2_1_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) "uart3_txd_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) "uart0_rts_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) "uart1_rts_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) "uart2_rts_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) "uart3_rts_cts", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static const char *mt7623_wdt_groups[] = { "watchdog_0", "watchdog_1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static const struct function_desc mt7623_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) {"audck", mt7623_aud_clk_groups, ARRAY_SIZE(mt7623_aud_clk_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) {"disp", mt7623_disp_pwm_groups, ARRAY_SIZE(mt7623_disp_pwm_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) {"eth", mt7623_ethernet_groups, ARRAY_SIZE(mt7623_ethernet_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {"sdio", mt7623_ext_sdio_groups, ARRAY_SIZE(mt7623_ext_sdio_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {"hdmi", mt7623_hdmi_groups, ARRAY_SIZE(mt7623_hdmi_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {"i2c", mt7623_i2c_groups, ARRAY_SIZE(mt7623_i2c_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {"i2s", mt7623_i2s_groups, ARRAY_SIZE(mt7623_i2s_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) {"ir", mt7623_ir_groups, ARRAY_SIZE(mt7623_ir_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {"lcd", mt7623_lcd_groups, ARRAY_SIZE(mt7623_lcd_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {"msdc", mt7623_msdc_groups, ARRAY_SIZE(mt7623_msdc_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {"nand", mt7623_nandc_groups, ARRAY_SIZE(mt7623_nandc_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {"otg", mt7623_otg_groups, ARRAY_SIZE(mt7623_otg_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {"pcie", mt7623_pcie_groups, ARRAY_SIZE(mt7623_pcie_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {"pcm", mt7623_pcm_groups, ARRAY_SIZE(mt7623_pcm_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) {"pwm", mt7623_pwm_groups, ARRAY_SIZE(mt7623_pwm_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) {"pwrap", mt7623_pwrap_groups, ARRAY_SIZE(mt7623_pwrap_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {"rtc", mt7623_rtc_groups, ARRAY_SIZE(mt7623_rtc_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) {"spi", mt7623_spi_groups, ARRAY_SIZE(mt7623_spi_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) {"spdif", mt7623_spdif_groups, ARRAY_SIZE(mt7623_spdif_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) {"uart", mt7623_uart_groups, ARRAY_SIZE(mt7623_uart_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) {"watchdog", mt7623_wdt_groups, ARRAY_SIZE(mt7623_wdt_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static const struct mtk_eint_hw mt7623_eint_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .port_mask = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .ports = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .ap_num = 169,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .db_cnt = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static struct mtk_pin_soc mt7623_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .reg_cal = mt7623_reg_cals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .pins = mt7623_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .npins = ARRAY_SIZE(mt7623_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .grps = mt7623_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .ngrps = ARRAY_SIZE(mt7623_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .funcs = mt7623_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .nfuncs = ARRAY_SIZE(mt7623_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .eint_hw = &mt7623_eint_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .gpio_m = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .ies_present = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .base_names = mtk_default_register_base_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .bias_disable_set = mtk_pinconf_bias_disable_set_rev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .bias_disable_get = mtk_pinconf_bias_disable_get_rev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .bias_set = mtk_pinconf_bias_set_rev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .bias_get = mtk_pinconf_bias_get_rev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .drive_set = mtk_pinconf_drive_set_rev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .drive_get = mtk_pinconf_drive_get_rev1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .adv_pull_get = mtk_pinconf_adv_pull_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .adv_pull_set = mtk_pinconf_adv_pull_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * There are some specific pins have mux functions greater than 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * and if we want to switch thees high modes we need to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * bonding constraints firstly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static void mt7623_bonding_disable(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) mtk_rmw(hw, 0, PIN_BOND_REG0, BOND_PCIE_CLR, BOND_PCIE_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) mtk_rmw(hw, 0, PIN_BOND_REG1, BOND_I2S_CLR, BOND_I2S_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) mtk_rmw(hw, 0, PIN_BOND_REG2, BOND_MSDC0E_CLR, BOND_MSDC0E_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static const struct of_device_id mt7623_pctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) { .compatible = "mediatek,mt7623-moore-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static int mt7623_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) err = mtk_moore_pinctrl_probe(pdev, &mt7623_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) mt7623_bonding_disable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static struct platform_driver mtk_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .probe = mt7623_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .name = "mt7623-moore-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .of_match_table = mt7623_pctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static int __init mtk_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return platform_driver_register(&mtk_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) arch_initcall(mtk_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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