^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017-2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "pinctrl-moore.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MT7622_PIN(_number, _name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) MTK_PIN(_number, _name, 1, _number, DRV_GRP0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PINS_FIELD(23, 24, 0x300, 0x10, 24, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PINS_FIELD(25, 36, 0x300, 0x10, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PINS_FIELD(37, 50, 0x300, 0x10, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PIN_FIELD(51, 70, 0x330, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PINS_FIELD(71, 72, 0x300, 0x10, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PIN_FIELD(73, 76, 0x310, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PIN_FIELD(77, 77, 0x320, 0x10, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PIN_FIELD(78, 78, 0x320, 0x10, 12, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PIN_FIELD(83, 83, 0x350, 0x10, 28, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PIN_FIELD(84, 84, 0x330, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PIN_FIELD(85, 90, 0x360, 0x10, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PIN_FIELD(91, 94, 0x390, 0x10, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PIN_FIELD(95, 97, 0x380, 0x10, 20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PIN_FIELD(98, 101, 0x390, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PIN_FIELD(102, 102, 0x360, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PIN_FIELD(0, 102, 0x0, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PIN_FIELD(0, 102, 0x200, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PIN_FIELD(0, 102, 0x100, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct mtk_pin_field_calc mt7622_pin_sr_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PIN_FIELD(0, 31, 0x910, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PIN_FIELD(32, 50, 0xa10, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PIN_FIELD(51, 70, 0x810, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PIN_FIELD(71, 72, 0xb10, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PIN_FIELD(73, 86, 0xb10, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PIN_FIELD(87, 90, 0xc10, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PIN_FIELD(91, 102, 0xb10, 0x10, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PIN_FIELD(0, 31, 0x920, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PIN_FIELD(51, 70, 0x820, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PIN_FIELD(0, 31, 0x930, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PIN_FIELD(51, 70, 0x830, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PIN_FIELD(0, 31, 0x940, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PIN_FIELD(51, 70, 0x840, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PIN_FIELD(0, 31, 0x960, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PIN_FIELD(51, 70, 0x860, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PIN_FIELD(0, 31, 0x970, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PIN_FIELD(51, 70, 0x870, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct mtk_pin_field_calc mt7622_pin_tdsel_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PIN_FIELD(0, 31, 0x980, 0x4, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PIN_FIELD(32, 50, 0xa80, 0x4, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PIN_FIELD(51, 70, 0x880, 0x4, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PIN_FIELD(71, 72, 0xb80, 0x4, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PIN_FIELD(73, 86, 0xb80, 0x4, 16, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PIN_FIELD(87, 90, 0xc80, 0x4, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PIN_FIELD(91, 102, 0xb88, 0x4, 8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct mtk_pin_field_calc mt7622_pin_rdsel_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PIN_FIELD(0, 31, 0x990, 0x4, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PIN_FIELD(32, 50, 0xa90, 0x4, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PIN_FIELD(51, 58, 0x890, 0x4, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PIN_FIELD(59, 60, 0x894, 0x4, 28, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PIN_FIELD(61, 62, 0x894, 0x4, 16, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PIN_FIELD(63, 66, 0x898, 0x4, 8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PIN_FIELD(67, 68, 0x89c, 0x4, 12, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PIN_FIELD(69, 70, 0x89c, 0x4, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PIN_FIELD(71, 72, 0xb90, 0x4, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PIN_FIELD(73, 86, 0xb90, 0x4, 24, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PIN_FIELD(87, 90, 0xc90, 0x4, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PIN_FIELD(91, 102, 0xb9c, 0x4, 12, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt7622_pin_sr_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [PINCTRL_PIN_REG_TDSEL] = MTK_RANGE(mt7622_pin_tdsel_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [PINCTRL_PIN_REG_RDSEL] = MTK_RANGE(mt7622_pin_rdsel_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct mtk_pin_desc mt7622_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MT7622_PIN(0, "GPIO_A"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MT7622_PIN(1, "I2S1_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MT7622_PIN(2, "I2S1_OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MT7622_PIN(3, "I2S_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MT7622_PIN(4, "I2S_WS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MT7622_PIN(5, "I2S_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MT7622_PIN(6, "TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MT7622_PIN(7, "RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MT7622_PIN(8, "SPI_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MT7622_PIN(9, "SPI_HOLD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MT7622_PIN(10, "SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MT7622_PIN(11, "SPI_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MT7622_PIN(12, "SPI_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MT7622_PIN(13, "SPI_CS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MT7622_PIN(14, "I2C_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MT7622_PIN(15, "I2C_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MT7622_PIN(16, "I2S2_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MT7622_PIN(17, "I2S3_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MT7622_PIN(18, "I2S4_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MT7622_PIN(19, "I2S2_OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MT7622_PIN(20, "I2S3_OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MT7622_PIN(21, "I2S4_OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MT7622_PIN(22, "GPIO_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MT7622_PIN(23, "MDC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MT7622_PIN(24, "MDIO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MT7622_PIN(25, "G2_TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MT7622_PIN(26, "G2_TXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MT7622_PIN(27, "G2_TXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MT7622_PIN(28, "G2_TXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MT7622_PIN(29, "G2_TXEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MT7622_PIN(30, "G2_TXC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MT7622_PIN(31, "G2_RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MT7622_PIN(32, "G2_RXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MT7622_PIN(33, "G2_RXD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MT7622_PIN(34, "G2_RXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MT7622_PIN(35, "G2_RXDV"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MT7622_PIN(36, "G2_RXC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MT7622_PIN(37, "NCEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MT7622_PIN(38, "NWEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MT7622_PIN(39, "NREB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MT7622_PIN(40, "NDL4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MT7622_PIN(41, "NDL5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MT7622_PIN(42, "NDL6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MT7622_PIN(43, "NDL7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MT7622_PIN(44, "NRB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MT7622_PIN(45, "NCLE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MT7622_PIN(46, "NALE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MT7622_PIN(47, "NDL0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MT7622_PIN(48, "NDL1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MT7622_PIN(49, "NDL2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MT7622_PIN(50, "NDL3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MT7622_PIN(51, "MDI_TP_P0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MT7622_PIN(52, "MDI_TN_P0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MT7622_PIN(53, "MDI_RP_P0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MT7622_PIN(54, "MDI_RN_P0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MT7622_PIN(55, "MDI_TP_P1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MT7622_PIN(56, "MDI_TN_P1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MT7622_PIN(57, "MDI_RP_P1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MT7622_PIN(58, "MDI_RN_P1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MT7622_PIN(59, "MDI_RP_P2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MT7622_PIN(60, "MDI_RN_P2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MT7622_PIN(61, "MDI_TP_P2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MT7622_PIN(62, "MDI_TN_P2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MT7622_PIN(63, "MDI_TP_P3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MT7622_PIN(64, "MDI_TN_P3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MT7622_PIN(65, "MDI_RP_P3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MT7622_PIN(66, "MDI_RN_P3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MT7622_PIN(67, "MDI_RP_P4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MT7622_PIN(68, "MDI_RN_P4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MT7622_PIN(69, "MDI_TP_P4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MT7622_PIN(70, "MDI_TN_P4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MT7622_PIN(71, "PMIC_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MT7622_PIN(72, "PMIC_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MT7622_PIN(73, "SPIC1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MT7622_PIN(74, "SPIC1_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MT7622_PIN(75, "SPIC1_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MT7622_PIN(76, "SPIC1_CS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MT7622_PIN(77, "GPIO_D"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MT7622_PIN(78, "WATCHDOG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MT7622_PIN(79, "RTS3_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MT7622_PIN(80, "CTS3_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MT7622_PIN(81, "TXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MT7622_PIN(82, "RXD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MT7622_PIN(83, "PERST0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MT7622_PIN(84, "PERST1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MT7622_PIN(85, "WLED_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MT7622_PIN(86, "EPHY_LED0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MT7622_PIN(87, "AUXIN0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MT7622_PIN(88, "AUXIN1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MT7622_PIN(89, "AUXIN2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MT7622_PIN(90, "AUXIN3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MT7622_PIN(91, "TXD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MT7622_PIN(92, "RXD4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MT7622_PIN(93, "RTS4_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MT7622_PIN(94, "CTS4_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MT7622_PIN(95, "PWM1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MT7622_PIN(96, "PWM2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MT7622_PIN(97, "PWM3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MT7622_PIN(98, "PWM4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MT7622_PIN(99, "PWM5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MT7622_PIN(100, "PWM6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MT7622_PIN(101, "PWM7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MT7622_PIN(102, "GPIO_E"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* List all groups consisting of these pins dedicated to the enablement of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * certain hardware block and the corresponding mode for all of the pins. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * hardware probably has multiple combinations of these pinouts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* ANTSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int mt7622_antsel0_pins[] = { 91, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int mt7622_antsel0_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int mt7622_antsel1_pins[] = { 92, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int mt7622_antsel1_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int mt7622_antsel2_pins[] = { 93, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int mt7622_antsel2_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int mt7622_antsel3_pins[] = { 94, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int mt7622_antsel3_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int mt7622_antsel4_pins[] = { 95, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int mt7622_antsel4_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int mt7622_antsel5_pins[] = { 96, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int mt7622_antsel5_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int mt7622_antsel6_pins[] = { 97, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int mt7622_antsel6_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int mt7622_antsel7_pins[] = { 98, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int mt7622_antsel7_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int mt7622_antsel8_pins[] = { 99, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int mt7622_antsel8_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int mt7622_antsel9_pins[] = { 100, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int mt7622_antsel9_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int mt7622_antsel10_pins[] = { 101, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int mt7622_antsel10_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int mt7622_antsel11_pins[] = { 102, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int mt7622_antsel11_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int mt7622_antsel12_pins[] = { 73, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int mt7622_antsel12_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int mt7622_antsel13_pins[] = { 74, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int mt7622_antsel13_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int mt7622_antsel14_pins[] = { 75, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int mt7622_antsel14_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int mt7622_antsel15_pins[] = { 76, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int mt7622_antsel15_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int mt7622_antsel16_pins[] = { 77, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int mt7622_antsel16_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int mt7622_antsel17_pins[] = { 22, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int mt7622_antsel17_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int mt7622_antsel18_pins[] = { 79, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int mt7622_antsel18_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int mt7622_antsel19_pins[] = { 80, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int mt7622_antsel19_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int mt7622_antsel20_pins[] = { 81, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static int mt7622_antsel20_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int mt7622_antsel21_pins[] = { 82, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int mt7622_antsel21_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int mt7622_antsel22_pins[] = { 14, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int mt7622_antsel22_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int mt7622_antsel23_pins[] = { 15, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int mt7622_antsel23_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int mt7622_antsel24_pins[] = { 16, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int mt7622_antsel24_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int mt7622_antsel25_pins[] = { 17, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int mt7622_antsel25_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int mt7622_antsel26_pins[] = { 18, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int mt7622_antsel26_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int mt7622_antsel27_pins[] = { 19, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int mt7622_antsel27_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static int mt7622_antsel28_pins[] = { 20, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int mt7622_antsel28_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int mt7622_antsel29_pins[] = { 21, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int mt7622_antsel29_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* EMMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int mt7622_emmc_rst_pins[] = { 37, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int mt7622_emmc_rst_funcs[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* LED for EPHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int mt7622_ephy0_led_pins[] = { 86, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int mt7622_ephy0_led_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int mt7622_ephy1_led_pins[] = { 91, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int mt7622_ephy1_led_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int mt7622_ephy2_led_pins[] = { 92, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int mt7622_ephy2_led_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int mt7622_ephy3_led_pins[] = { 93, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static int mt7622_ephy3_led_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int mt7622_ephy4_led_pins[] = { 94, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int mt7622_ephy4_led_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Embedded Switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 62, 63, 64, 65, 66, 67, 68, 69, 70, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0, 0, 0, 0, 0, 0, 0, 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 68, 69, 70, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 0, 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* RGMII via ESW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 67, 68, 69, 70, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* RGMII via GMAC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 67, 68, 69, 70, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* RGMII via GMAC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 33, 34, 35, 36, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static int mt7622_i2c0_pins[] = { 14, 15, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int mt7622_i2c0_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int mt7622_i2c1_0_pins[] = { 55, 56, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int mt7622_i2c1_0_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int mt7622_i2c1_1_pins[] = { 73, 74, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int mt7622_i2c1_1_funcs[] = { 3, 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int mt7622_i2c1_2_pins[] = { 87, 88, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int mt7622_i2c1_2_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int mt7622_i2c2_0_pins[] = { 57, 58, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int mt7622_i2c2_0_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static int mt7622_i2c2_1_pins[] = { 75, 76, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int mt7622_i2c2_1_funcs[] = { 3, 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int mt7622_i2c2_2_pins[] = { 89, 90, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int mt7622_i2c2_2_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* I2S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static int mt7622_i2s1_in_data_pins[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int mt7622_i2s1_in_data_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int mt7622_i2s2_in_data_pins[] = { 16, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int mt7622_i2s2_in_data_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int mt7622_i2s3_in_data_pins[] = { 17, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int mt7622_i2s3_in_data_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int mt7622_i2s4_in_data_pins[] = { 18, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int mt7622_i2s4_in_data_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int mt7622_i2s1_out_data_pins[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int mt7622_i2s1_out_data_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int mt7622_i2s2_out_data_pins[] = { 19, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int mt7622_i2s2_out_data_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int mt7622_i2s3_out_data_pins[] = { 20, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int mt7622_i2s3_out_data_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int mt7622_i2s4_out_data_pins[] = { 21, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int mt7622_i2s4_out_data_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int mt7622_ir_0_tx_pins[] = { 16, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int mt7622_ir_0_tx_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int mt7622_ir_1_tx_pins[] = { 59, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int mt7622_ir_1_tx_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int mt7622_ir_2_tx_pins[] = { 99, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int mt7622_ir_2_tx_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int mt7622_ir_0_rx_pins[] = { 17, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int mt7622_ir_0_rx_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int mt7622_ir_1_rx_pins[] = { 60, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int mt7622_ir_1_rx_funcs[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int mt7622_ir_2_rx_pins[] = { 100, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int mt7622_ir_2_rx_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int mt7622_mdc_mdio_pins[] = { 23, 24, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int mt7622_pcie0_0_waken_pins[] = { 14, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int mt7622_pcie0_0_waken_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int mt7622_pcie0_1_waken_pins[] = { 79, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int mt7622_pcie0_1_waken_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int mt7622_pcie1_0_waken_pins[] = { 14, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int mt7622_pcie1_0_waken_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static int mt7622_pcie0_pad_perst_pins[] = { 83, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int mt7622_pcie1_pad_perst_pins[] = { 84, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* PMIC bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int mt7622_pmic_bus_pins[] = { 71, 72, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int mt7622_pmic_bus_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Parallel NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 48, 49, 50, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int mt7622_pwm_ch1_0_pins[] = { 51, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int mt7622_pwm_ch1_0_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int mt7622_pwm_ch1_1_pins[] = { 73, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int mt7622_pwm_ch1_1_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int mt7622_pwm_ch1_2_pins[] = { 95, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int mt7622_pwm_ch1_2_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int mt7622_pwm_ch2_0_pins[] = { 52, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static int mt7622_pwm_ch2_0_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static int mt7622_pwm_ch2_1_pins[] = { 74, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int mt7622_pwm_ch2_1_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int mt7622_pwm_ch2_2_pins[] = { 96, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int mt7622_pwm_ch2_2_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int mt7622_pwm_ch3_0_pins[] = { 53, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int mt7622_pwm_ch3_0_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int mt7622_pwm_ch3_1_pins[] = { 75, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static int mt7622_pwm_ch3_1_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static int mt7622_pwm_ch3_2_pins[] = { 97, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int mt7622_pwm_ch3_2_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int mt7622_pwm_ch4_0_pins[] = { 54, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int mt7622_pwm_ch4_0_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int mt7622_pwm_ch4_1_pins[] = { 67, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int mt7622_pwm_ch4_1_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int mt7622_pwm_ch4_2_pins[] = { 76, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int mt7622_pwm_ch4_2_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int mt7622_pwm_ch4_3_pins[] = { 98, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int mt7622_pwm_ch4_3_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static int mt7622_pwm_ch5_0_pins[] = { 68, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int mt7622_pwm_ch5_0_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int mt7622_pwm_ch5_1_pins[] = { 77, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int mt7622_pwm_ch5_1_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int mt7622_pwm_ch5_2_pins[] = { 99, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int mt7622_pwm_ch5_2_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static int mt7622_pwm_ch6_0_pins[] = { 69, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int mt7622_pwm_ch6_0_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int mt7622_pwm_ch6_1_pins[] = { 78, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int mt7622_pwm_ch6_1_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int mt7622_pwm_ch6_2_pins[] = { 81, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int mt7622_pwm_ch6_2_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int mt7622_pwm_ch6_3_pins[] = { 100, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int mt7622_pwm_ch6_3_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int mt7622_pwm_ch7_0_pins[] = { 70, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int mt7622_pwm_ch7_0_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int mt7622_pwm_ch7_1_pins[] = { 82, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int mt7622_pwm_ch7_1_funcs[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int mt7622_pwm_ch7_2_pins[] = { 101, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int mt7622_pwm_ch7_2_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* SD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Serial NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* SPI NOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* SPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* TDM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int mt7622_tdm_0_out_data_pins[] = { 20, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int mt7622_tdm_0_out_data_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int mt7622_tdm_0_in_data_pins[] = { 21, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int mt7622_tdm_0_in_data_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int mt7622_tdm_1_out_data_pins[] = { 55, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int mt7622_tdm_1_out_data_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int mt7622_tdm_1_in_data_pins[] = { 56, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int mt7622_tdm_1_in_data_funcs[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int mt7622_watchdog_pins[] = { 78, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int mt7622_watchdog_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* WLAN LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int mt7622_wled_pins[] = { 85, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int mt7622_wled_funcs[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static const struct group_desc mt7622_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINCTRL_PIN_GROUP("antsel0", mt7622_antsel0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINCTRL_PIN_GROUP("antsel1", mt7622_antsel1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINCTRL_PIN_GROUP("antsel2", mt7622_antsel2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINCTRL_PIN_GROUP("antsel3", mt7622_antsel3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINCTRL_PIN_GROUP("antsel4", mt7622_antsel4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINCTRL_PIN_GROUP("antsel5", mt7622_antsel5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINCTRL_PIN_GROUP("antsel6", mt7622_antsel6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINCTRL_PIN_GROUP("antsel7", mt7622_antsel7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PINCTRL_PIN_GROUP("antsel8", mt7622_antsel8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINCTRL_PIN_GROUP("antsel9", mt7622_antsel9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PINCTRL_PIN_GROUP("antsel10", mt7622_antsel10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINCTRL_PIN_GROUP("antsel11", mt7622_antsel11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINCTRL_PIN_GROUP("antsel12", mt7622_antsel12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINCTRL_PIN_GROUP("antsel13", mt7622_antsel13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PINCTRL_PIN_GROUP("antsel14", mt7622_antsel14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINCTRL_PIN_GROUP("antsel15", mt7622_antsel15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINCTRL_PIN_GROUP("antsel16", mt7622_antsel16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINCTRL_PIN_GROUP("antsel17", mt7622_antsel17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINCTRL_PIN_GROUP("antsel18", mt7622_antsel18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINCTRL_PIN_GROUP("antsel19", mt7622_antsel19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINCTRL_PIN_GROUP("antsel20", mt7622_antsel20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINCTRL_PIN_GROUP("antsel21", mt7622_antsel21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINCTRL_PIN_GROUP("antsel22", mt7622_antsel22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINCTRL_PIN_GROUP("antsel23", mt7622_antsel23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINCTRL_PIN_GROUP("antsel24", mt7622_antsel24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINCTRL_PIN_GROUP("antsel25", mt7622_antsel25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PINCTRL_PIN_GROUP("antsel26", mt7622_antsel26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINCTRL_PIN_GROUP("antsel27", mt7622_antsel27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINCTRL_PIN_GROUP("antsel28", mt7622_antsel28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINCTRL_PIN_GROUP("antsel29", mt7622_antsel29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PINCTRL_PIN_GROUP("esw", mt7622_esw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PINCTRL_PIN_GROUP("par_nand", mt7622_pnand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PINCTRL_PIN_GROUP("spi_nor", mt7622_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) mt7622_tdm_0_out_mclk_bclk_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) mt7622_tdm_0_in_mclk_bclk_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mt7622_tdm_1_out_mclk_bclk_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) mt7622_tdm_1_in_mclk_bclk_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PINCTRL_PIN_GROUP("wled", mt7622_wled),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Joint those groups owning the same capability in user point of view which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * allows that people tend to use through the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static const char *mt7622_antsel_groups[] = { "antsel0", "antsel1", "antsel2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "antsel3", "antsel4", "antsel5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "antsel6", "antsel7", "antsel8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "antsel9", "antsel10", "antsel11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) "antsel12", "antsel13", "antsel14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "antsel15", "antsel16", "antsel17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "antsel18", "antsel19", "antsel20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) "antsel21", "antsel22", "antsel23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "antsel24", "antsel25", "antsel26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) "antsel27", "antsel28", "antsel29",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) "esw_p2_p3_p4", "mdc_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "rgmii_via_gmac1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "rgmii_via_gmac2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) "rgmii_via_esw", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const char *mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) "i2c1_2", "i2c2_0", "i2c2_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "i2c2_2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const char *mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) "i2s_in_mclk_bclk_ws",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "i2s1_in_data", "i2s2_in_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) "i2s3_in_data", "i2s4_in_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) "i2s1_out_data", "i2s2_out_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) "i2s3_out_data", "i2s4_out_data", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static const char *mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) "ir_0_rx", "ir_1_rx", "ir_2_rx"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static const char *mt7622_led_groups[] = { "ephy_leds", "ephy0_led",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) "ephy1_led", "ephy2_led",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) "ephy3_led", "ephy4_led",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "wled", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static const char *mt7622_flash_groups[] = { "par_nand", "snfi", "spi_nor"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const char *mt7622_pcie_groups[] = { "pcie0_0_waken", "pcie0_0_clkreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "pcie0_1_waken", "pcie0_1_clkreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) "pcie1_0_waken", "pcie1_0_clkreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "pcie0_pad_perst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "pcie1_pad_perst", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static const char *mt7622_pmic_bus_groups[] = { "pmic_bus", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static const char *mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "pwm_ch1_2", "pwm_ch2_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) "pwm_ch2_1", "pwm_ch2_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) "pwm_ch3_0", "pwm_ch3_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) "pwm_ch3_2", "pwm_ch4_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "pwm_ch4_1", "pwm_ch4_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "pwm_ch4_3", "pwm_ch5_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "pwm_ch5_1", "pwm_ch5_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) "pwm_ch6_0", "pwm_ch6_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) "pwm_ch6_2", "pwm_ch6_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "pwm_ch7_0", "pwm_ch7_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) "pwm_ch7_2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static const char *mt7622_sd_groups[] = { "sd_0", "sd_1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static const char *mt7622_spic_groups[] = { "spic0_0", "spic0_1", "spic1_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) "spic1_1", "spic2_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "spic2_0_wp_hold", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const char *mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "tdm_0_in_mclk_bclk_ws",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "tdm_0_out_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "tdm_0_in_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) "tdm_1_out_mclk_bclk_ws",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) "tdm_1_in_mclk_bclk_ws",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) "tdm_1_out_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) "tdm_1_in_data", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) "uart1_0_tx_rx", "uart1_0_rts_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) "uart1_1_tx_rx", "uart1_1_rts_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) "uart2_0_tx_rx", "uart2_0_rts_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) "uart2_1_tx_rx", "uart2_1_rts_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) "uart2_2_tx_rx", "uart2_2_rts_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) "uart2_3_tx_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "uart3_0_tx_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "uart3_1_tx_rx", "uart3_1_rts_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) "uart4_0_tx_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "uart4_1_tx_rx", "uart4_1_rts_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "uart4_2_tx_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "uart4_2_rts_cts",};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const char *mt7622_wdt_groups[] = { "watchdog", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const struct function_desc mt7622_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {"antsel", mt7622_antsel_groups, ARRAY_SIZE(mt7622_antsel_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const struct mtk_eint_hw mt7622_eint_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .port_mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .ports = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .ap_num = ARRAY_SIZE(mt7622_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .db_cnt = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const struct mtk_pin_soc mt7622_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .reg_cal = mt7622_reg_cals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .pins = mt7622_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .npins = ARRAY_SIZE(mt7622_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .grps = mt7622_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .ngrps = ARRAY_SIZE(mt7622_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .funcs = mt7622_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .nfuncs = ARRAY_SIZE(mt7622_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .eint_hw = &mt7622_eint_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .gpio_m = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .ies_present = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .base_names = mtk_default_register_base_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .nbase_names = ARRAY_SIZE(mtk_default_register_base_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .bias_disable_set = mtk_pinconf_bias_disable_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .bias_disable_get = mtk_pinconf_bias_disable_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .bias_set = mtk_pinconf_bias_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .bias_get = mtk_pinconf_bias_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .drive_set = mtk_pinconf_drive_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .drive_get = mtk_pinconf_drive_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static const struct of_device_id mt7622_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) { .compatible = "mediatek,mt7622-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int mt7622_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return mtk_moore_pinctrl_probe(pdev, &mt7622_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static struct platform_driver mt7622_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .name = "mt7622-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) .of_match_table = mt7622_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .probe = mt7622_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int __init mt7622_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return platform_driver_register(&mt7622_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) arch_initcall(mt7622_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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