Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Based on pinctrl-mt6765.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Author: ZH Chen <zh.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * Copyright (C) Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pinctrl-mtk-mt6797.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pinctrl-paris.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * MT6797 have multiple bases to program pin configuration listed as the below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * iocfg[r]:0x10002800, iocfg[t]:0x10002C00.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * _i_base could be used to indicate what base the pin should be mapped into.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static const struct mtk_pin_field_calc mt6797_pin_mode_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	PIN_FIELD(0, 261, 0x300, 0x10, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const struct mtk_pin_field_calc mt6797_pin_dir_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	PIN_FIELD(0, 261, 0x0, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const struct mtk_pin_field_calc mt6797_pin_di_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	PIN_FIELD(0, 261, 0x200, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const struct mtk_pin_field_calc mt6797_pin_do_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	PIN_FIELD(0, 261, 0x100, 0x10, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static const struct mtk_pin_reg_calc mt6797_reg_cals[PINCTRL_PIN_REG_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6797_pin_mode_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6797_pin_dir_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6797_pin_di_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	[PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6797_pin_do_range),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const char * const mt6797_pinctrl_register_base_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	"gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static const struct mtk_pin_soc mt6797_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	.reg_cal = mt6797_reg_cals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	.pins = mtk_pins_mt6797,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	.npins = ARRAY_SIZE(mtk_pins_mt6797),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	.ngrps = ARRAY_SIZE(mtk_pins_mt6797),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	.gpio_m = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	.base_names = mt6797_pinctrl_register_base_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	.nbase_names = ARRAY_SIZE(mt6797_pinctrl_register_base_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const struct of_device_id mt6797_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	{ .compatible = "mediatek,mt6797-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int mt6797_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	return mtk_paris_pinctrl_probe(pdev, &mt6797_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct platform_driver mt6797_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		.name = "mt6797-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		.of_match_table = mt6797_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	.probe = mt6797_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int __init mt6797_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	return platform_driver_register(&mt6797_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) arch_initcall(mt6797_pinctrl_init);