Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2015 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/mt6397/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pinctrl-mtk-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-mtk-mt6397.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MT6397_PIN_REG_BASE  0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct mtk_pinctrl_devdata mt6397_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	.pins = mtk_pins_mt6397,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	.npins = ARRAY_SIZE(mtk_pins_mt6397),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	.dir_offset = (MT6397_PIN_REG_BASE + 0x000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	.ies_offset = MTK_PINCTRL_NOT_SUPPORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	.smt_offset = MTK_PINCTRL_NOT_SUPPORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	.pullen_offset = (MT6397_PIN_REG_BASE + 0x020),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	.pullsel_offset = (MT6397_PIN_REG_BASE + 0x040),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	.dout_offset = (MT6397_PIN_REG_BASE + 0x080),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	.din_offset = (MT6397_PIN_REG_BASE + 0x0a0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	.pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	.type1_start = 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	.type1_end = 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	.port_shf = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	.port_mask = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	.port_align = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int mt6397_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	struct mt6397_chip *mt6397;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	mt6397 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	return mtk_pctrl_init(pdev, &mt6397_pinctrl_data, mt6397->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const struct of_device_id mt6397_pctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	{ .compatible = "mediatek,mt6397-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct platform_driver mtk_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	.probe = mt6397_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		.name = "mediatek-mt6397-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		.of_match_table = mt6397_pctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) builtin_platform_driver(mtk_pinctrl_driver);