^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/pinctrl/mt65xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "pinctrl-mtk-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "pinctrl-mtk-mt2712.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static const struct mtk_pin_spec_pupd_set_samereg mt2712_spec_pupd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MTK_PIN_PUPD_SPEC_SR(34, 0xf40, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MTK_PIN_PUPD_SPEC_SR(35, 0xf40, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MTK_PIN_PUPD_SPEC_SR(36, 0xf40, 10, 9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MTK_PIN_PUPD_SPEC_SR(37, 0xc40, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MTK_PIN_PUPD_SPEC_SR(38, 0xc60, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MTK_PIN_PUPD_SPEC_SR(39, 0xc60, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MTK_PIN_PUPD_SPEC_SR(40, 0xc60, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MTK_PIN_PUPD_SPEC_SR(41, 0xc60, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MTK_PIN_PUPD_SPEC_SR(42, 0xc60, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MTK_PIN_PUPD_SPEC_SR(43, 0xc60, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MTK_PIN_PUPD_SPEC_SR(44, 0xc60, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MTK_PIN_PUPD_SPEC_SR(45, 0xc60, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MTK_PIN_PUPD_SPEC_SR(46, 0xc50, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MTK_PIN_PUPD_SPEC_SR(47, 0xda0, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MTK_PIN_PUPD_SPEC_SR(48, 0xd90, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MTK_PIN_PUPD_SPEC_SR(49, 0xdf0, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MTK_PIN_PUPD_SPEC_SR(50, 0xdf0, 10, 9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MTK_PIN_PUPD_SPEC_SR(51, 0xdf0, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MTK_PIN_PUPD_SPEC_SR(52, 0xdf0, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MTK_PIN_PUPD_SPEC_SR(53, 0xd50, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MTK_PIN_PUPD_SPEC_SR(54, 0xd80, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MTK_PIN_PUPD_SPEC_SR(55, 0xe00, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MTK_PIN_PUPD_SPEC_SR(56, 0xd40, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MTK_PIN_PUPD_SPEC_SR(63, 0xc80, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MTK_PIN_PUPD_SPEC_SR(64, 0xdb0, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MTK_PIN_PUPD_SPEC_SR(65, 0xdb0, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MTK_PIN_PUPD_SPEC_SR(66, 0xdb0, 10, 9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MTK_PIN_PUPD_SPEC_SR(67, 0xcd0, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MTK_PIN_PUPD_SPEC_SR(68, 0xdb0, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MTK_PIN_PUPD_SPEC_SR(69, 0xc90, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MTK_PIN_PUPD_SPEC_SR(70, 0xcc0, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MTK_PIN_PUPD_SPEC_SR(89, 0xce0, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MTK_PIN_PUPD_SPEC_SR(90, 0xdd0, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MTK_PIN_PUPD_SPEC_SR(91, 0xdd0, 10, 9, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MTK_PIN_PUPD_SPEC_SR(92, 0xdd0, 6, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MTK_PIN_PUPD_SPEC_SR(93, 0xdd0, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MTK_PIN_PUPD_SPEC_SR(94, 0xd20, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MTK_PIN_PUPD_SPEC_SR(95, 0xcf0, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MTK_PIN_PUPD_SPEC_SR(96, 0xd30, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MTK_PIN_PUPD_SPEC_SR(135, 0xe50, 11, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MTK_PIN_PUPD_SPEC_SR(136, 0xe50, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MTK_PIN_PUPD_SPEC_SR(137, 0xe70, 5, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MTK_PIN_PUPD_SPEC_SR(138, 0xe70, 8, 7, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MTK_PIN_PUPD_SPEC_SR(139, 0xe70, 11, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MTK_PIN_PUPD_SPEC_SR(140, 0xe70, 14, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MTK_PIN_PUPD_SPEC_SR(141, 0xe60, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MTK_PIN_PUPD_SPEC_SR(142, 0xe60, 5, 4, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int mt2712_spec_pull_set(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned char align,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bool isup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int r1r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return mtk_pctrl_spec_pull_set_samereg(regmap, mt2712_spec_pupd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ARRAY_SIZE(mt2712_spec_pupd), pin, align, isup, r1r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static const struct mtk_pin_ies_smt_set mt2712_smt_set[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MTK_PIN_IES_SMT_SPEC(0, 3, 0x900, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MTK_PIN_IES_SMT_SPEC(4, 7, 0x900, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MTK_PIN_IES_SMT_SPEC(8, 11, 0x900, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MTK_PIN_IES_SMT_SPEC(12, 12, 0x8d0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MTK_PIN_IES_SMT_SPEC(13, 13, 0x8d0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MTK_PIN_IES_SMT_SPEC(14, 14, 0x8d0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MTK_PIN_IES_SMT_SPEC(15, 15, 0x8d0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MTK_PIN_IES_SMT_SPEC(18, 23, 0x8d0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MTK_PIN_IES_SMT_SPEC(24, 25, 0x8d0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MTK_PIN_IES_SMT_SPEC(26, 26, 0x8d0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MTK_PIN_IES_SMT_SPEC(27, 27, 0x8d0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MTK_PIN_IES_SMT_SPEC(28, 29, 0x8d0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MTK_PIN_IES_SMT_SPEC(57, 62, 0x900, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MTK_PIN_IES_SMT_SPEC(67, 67, 0xc80, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MTK_PIN_IES_SMT_SPEC(68, 68, 0xca0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MTK_PIN_IES_SMT_SPEC(71, 74, 0x8d0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MTK_PIN_IES_SMT_SPEC(75, 77, 0x8d0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MTK_PIN_IES_SMT_SPEC(78, 81, 0x8d0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MTK_PIN_IES_SMT_SPEC(82, 88, 0x8d0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MTK_PIN_IES_SMT_SPEC(97, 100, 0x8d0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MTK_PIN_IES_SMT_SPEC(101, 104, 0x8d0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MTK_PIN_IES_SMT_SPEC(105, 105, 0x8d0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MTK_PIN_IES_SMT_SPEC(106, 106, 0x8d0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MTK_PIN_IES_SMT_SPEC(107, 107, 0x8d0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MTK_PIN_IES_SMT_SPEC(108, 108, 0x8e0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MTK_PIN_IES_SMT_SPEC(109, 109, 0x8e0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MTK_PIN_IES_SMT_SPEC(110, 110, 0x8e0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MTK_PIN_IES_SMT_SPEC(111, 111, 0x8d0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MTK_PIN_IES_SMT_SPEC(112, 112, 0x8d0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MTK_PIN_IES_SMT_SPEC(113, 113, 0x8d0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MTK_PIN_IES_SMT_SPEC(114, 114, 0x8e0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MTK_PIN_IES_SMT_SPEC(115, 115, 0x8e0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MTK_PIN_IES_SMT_SPEC(116, 116, 0x8e0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MTK_PIN_IES_SMT_SPEC(117, 117, 0x8e0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MTK_PIN_IES_SMT_SPEC(118, 118, 0x8e0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MTK_PIN_IES_SMT_SPEC(119, 119, 0x8e0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MTK_PIN_IES_SMT_SPEC(120, 120, 0x8e0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MTK_PIN_IES_SMT_SPEC(121, 121, 0x8e0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MTK_PIN_IES_SMT_SPEC(122, 122, 0x8e0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MTK_PIN_IES_SMT_SPEC(123, 126, 0x8e0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MTK_PIN_IES_SMT_SPEC(127, 130, 0x8e0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MTK_PIN_IES_SMT_SPEC(131, 134, 0x8e0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MTK_PIN_IES_SMT_SPEC(135, 142, 0x8d0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MTK_PIN_IES_SMT_SPEC(143, 147, 0x8e0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MTK_PIN_IES_SMT_SPEC(148, 152, 0x8e0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MTK_PIN_IES_SMT_SPEC(153, 156, 0x8e0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MTK_PIN_IES_SMT_SPEC(157, 160, 0x8e0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MTK_PIN_IES_SMT_SPEC(161, 164, 0x8e0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MTK_PIN_IES_SMT_SPEC(165, 168, 0x8e0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MTK_PIN_IES_SMT_SPEC(169, 170, 0x8e0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MTK_PIN_IES_SMT_SPEC(171, 172, 0x8f0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MTK_PIN_IES_SMT_SPEC(173, 173, 0x8f0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MTK_PIN_IES_SMT_SPEC(174, 175, 0x8f0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MTK_PIN_IES_SMT_SPEC(176, 176, 0x8f0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MTK_PIN_IES_SMT_SPEC(177, 177, 0x8f0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MTK_PIN_IES_SMT_SPEC(178, 178, 0x8f0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MTK_PIN_IES_SMT_SPEC(179, 179, 0x8f0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MTK_PIN_IES_SMT_SPEC(180, 180, 0x8f0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MTK_PIN_IES_SMT_SPEC(181, 181, 0x8f0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MTK_PIN_IES_SMT_SPEC(182, 182, 0x8f0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MTK_PIN_IES_SMT_SPEC(183, 183, 0x8f0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MTK_PIN_IES_SMT_SPEC(184, 184, 0x8f0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MTK_PIN_IES_SMT_SPEC(185, 186, 0x8f0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MTK_PIN_IES_SMT_SPEC(187, 187, 0x8f0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MTK_PIN_IES_SMT_SPEC(188, 188, 0x8f0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MTK_PIN_IES_SMT_SPEC(189, 189, 0x8f0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MTK_PIN_IES_SMT_SPEC(190, 190, 0x8f0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MTK_PIN_IES_SMT_SPEC(191, 191, 0x8f0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MTK_PIN_IES_SMT_SPEC(192, 192, 0x8f0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MTK_PIN_IES_SMT_SPEC(193, 194, 0x8f0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MTK_PIN_IES_SMT_SPEC(195, 195, 0x8f0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MTK_PIN_IES_SMT_SPEC(196, 199, 0x8f0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MTK_PIN_IES_SMT_SPEC(200, 203, 0x8f0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MTK_PIN_IES_SMT_SPEC(204, 206, 0x8f0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MTK_PIN_IES_SMT_SPEC(207, 209, 0x8f0, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct mtk_pin_ies_smt_set mt2712_ies_set[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MTK_PIN_IES_SMT_SPEC(0, 3, 0x8c0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MTK_PIN_IES_SMT_SPEC(4, 7, 0x8c0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MTK_PIN_IES_SMT_SPEC(8, 9, 0x8c0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MTK_PIN_IES_SMT_SPEC(10, 11, 0x8c0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MTK_PIN_IES_SMT_SPEC(12, 12, 0x890, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MTK_PIN_IES_SMT_SPEC(13, 13, 0x890, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MTK_PIN_IES_SMT_SPEC(14, 14, 0x890, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MTK_PIN_IES_SMT_SPEC(15, 15, 0x890, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MTK_PIN_IES_SMT_SPEC(18, 23, 0x890, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MTK_PIN_IES_SMT_SPEC(24, 25, 0x890, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MTK_PIN_IES_SMT_SPEC(26, 26, 0x890, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MTK_PIN_IES_SMT_SPEC(27, 27, 0x890, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MTK_PIN_IES_SMT_SPEC(28, 29, 0x890, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MTK_PIN_IES_SMT_SPEC(30, 36, 0xf50, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MTK_PIN_IES_SMT_SPEC(37, 37, 0xc40, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MTK_PIN_IES_SMT_SPEC(38, 45, 0xc60, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MTK_PIN_IES_SMT_SPEC(46, 46, 0xc50, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MTK_PIN_IES_SMT_SPEC(47, 47, 0xda0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MTK_PIN_IES_SMT_SPEC(48, 48, 0xd90, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MTK_PIN_IES_SMT_SPEC(49, 52, 0xd60, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MTK_PIN_IES_SMT_SPEC(53, 53, 0xd50, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MTK_PIN_IES_SMT_SPEC(54, 54, 0xd80, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MTK_PIN_IES_SMT_SPEC(55, 55, 0xe00, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MTK_PIN_IES_SMT_SPEC(56, 56, 0xd40, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MTK_PIN_IES_SMT_SPEC(57, 62, 0x8c0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MTK_PIN_IES_SMT_SPEC(63, 63, 0xc80, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MTK_PIN_IES_SMT_SPEC(64, 66, 0xca0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MTK_PIN_IES_SMT_SPEC(67, 68, 0xc80, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MTK_PIN_IES_SMT_SPEC(69, 69, 0xc90, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MTK_PIN_IES_SMT_SPEC(70, 70, 0xc80, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MTK_PIN_IES_SMT_SPEC(71, 74, 0x890, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MTK_PIN_IES_SMT_SPEC(75, 77, 0x890, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MTK_PIN_IES_SMT_SPEC(78, 81, 0x890, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MTK_PIN_IES_SMT_SPEC(82, 88, 0x890, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MTK_PIN_IES_SMT_SPEC(89, 89, 0xce0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MTK_PIN_IES_SMT_SPEC(90, 93, 0xd00, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MTK_PIN_IES_SMT_SPEC(94, 94, 0xce0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MTK_PIN_IES_SMT_SPEC(95, 96, 0xcf0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MTK_PIN_IES_SMT_SPEC(97, 100, 0x890, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MTK_PIN_IES_SMT_SPEC(101, 104, 0x890, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MTK_PIN_IES_SMT_SPEC(105, 105, 0x890, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MTK_PIN_IES_SMT_SPEC(106, 106, 0x890, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MTK_PIN_IES_SMT_SPEC(107, 107, 0x890, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MTK_PIN_IES_SMT_SPEC(108, 108, 0x8a0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MTK_PIN_IES_SMT_SPEC(109, 109, 0x8a0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MTK_PIN_IES_SMT_SPEC(110, 110, 0x8a0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MTK_PIN_IES_SMT_SPEC(111, 111, 0x890, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MTK_PIN_IES_SMT_SPEC(112, 112, 0x890, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MTK_PIN_IES_SMT_SPEC(113, 113, 0x890, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MTK_PIN_IES_SMT_SPEC(114, 114, 0x8a0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MTK_PIN_IES_SMT_SPEC(115, 115, 0x8a0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MTK_PIN_IES_SMT_SPEC(116, 116, 0x8a0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MTK_PIN_IES_SMT_SPEC(117, 117, 0x8a0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MTK_PIN_IES_SMT_SPEC(118, 118, 0x8a0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MTK_PIN_IES_SMT_SPEC(119, 119, 0x8a0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MTK_PIN_IES_SMT_SPEC(120, 120, 0x8a0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MTK_PIN_IES_SMT_SPEC(121, 121, 0x8a0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MTK_PIN_IES_SMT_SPEC(122, 122, 0x8a0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MTK_PIN_IES_SMT_SPEC(123, 126, 0x8a0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MTK_PIN_IES_SMT_SPEC(127, 130, 0x8a0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MTK_PIN_IES_SMT_SPEC(131, 135, 0x8a0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MTK_PIN_IES_SMT_SPEC(136, 142, 0x890, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MTK_PIN_IES_SMT_SPEC(143, 147, 0x8a0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MTK_PIN_IES_SMT_SPEC(148, 152, 0x8a0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MTK_PIN_IES_SMT_SPEC(153, 156, 0x8a0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MTK_PIN_IES_SMT_SPEC(157, 160, 0x8a0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MTK_PIN_IES_SMT_SPEC(161, 164, 0x8a0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MTK_PIN_IES_SMT_SPEC(165, 168, 0x8a0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MTK_PIN_IES_SMT_SPEC(169, 170, 0x8a0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MTK_PIN_IES_SMT_SPEC(171, 172, 0x8b0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MTK_PIN_IES_SMT_SPEC(173, 173, 0x8b0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MTK_PIN_IES_SMT_SPEC(174, 175, 0x8b0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MTK_PIN_IES_SMT_SPEC(176, 176, 0x8b0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MTK_PIN_IES_SMT_SPEC(177, 177, 0x8b0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MTK_PIN_IES_SMT_SPEC(178, 178, 0x8b0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MTK_PIN_IES_SMT_SPEC(179, 179, 0x8b0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MTK_PIN_IES_SMT_SPEC(180, 180, 0x8b0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MTK_PIN_IES_SMT_SPEC(181, 181, 0x8b0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MTK_PIN_IES_SMT_SPEC(182, 182, 0x8b0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MTK_PIN_IES_SMT_SPEC(183, 183, 0x8b0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MTK_PIN_IES_SMT_SPEC(184, 184, 0x8b0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MTK_PIN_IES_SMT_SPEC(185, 186, 0x8b0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MTK_PIN_IES_SMT_SPEC(187, 187, 0x8b0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MTK_PIN_IES_SMT_SPEC(188, 188, 0x8b0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MTK_PIN_IES_SMT_SPEC(189, 189, 0x8b0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MTK_PIN_IES_SMT_SPEC(190, 190, 0x8b0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MTK_PIN_IES_SMT_SPEC(191, 191, 0x8b0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MTK_PIN_IES_SMT_SPEC(192, 192, 0x8b0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MTK_PIN_IES_SMT_SPEC(193, 194, 0x8b0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MTK_PIN_IES_SMT_SPEC(195, 195, 0x8b0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MTK_PIN_IES_SMT_SPEC(196, 199, 0x8b0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MTK_PIN_IES_SMT_SPEC(200, 203, 0x8b0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MTK_PIN_IES_SMT_SPEC(204, 206, 0x8b0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MTK_PIN_IES_SMT_SPEC(207, 209, 0x8b0, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int mt2712_ies_smt_set(struct regmap *regmap, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned char align,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int value, enum pin_config_param arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (arg == PIN_CONFIG_INPUT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_ies_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) ARRAY_SIZE(mt2712_ies_set), pin, align, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return mtk_pconf_spec_set_ies_smt_range(regmap, mt2712_smt_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ARRAY_SIZE(mt2712_smt_set), pin, align, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct mtk_drv_group_desc mt2712_drv_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* 0E4E8SR 4/8/12/16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MTK_DRV_GRP(4, 16, 1, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* 0E2E4SR 2/4/6/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MTK_DRV_GRP(2, 8, 1, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* E8E4E2 2/4/6/8/10/12/14/16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MTK_DRV_GRP(2, 16, 0, 2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct mtk_pin_drv_grp mt2712_pin_drv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MTK_PIN_DRV_GRP(0, 0xc10, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MTK_PIN_DRV_GRP(1, 0xc10, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MTK_PIN_DRV_GRP(2, 0xc10, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MTK_PIN_DRV_GRP(3, 0xc10, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MTK_PIN_DRV_GRP(4, 0xc00, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MTK_PIN_DRV_GRP(5, 0xc00, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MTK_PIN_DRV_GRP(6, 0xc00, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MTK_PIN_DRV_GRP(7, 0xc00, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MTK_PIN_DRV_GRP(8, 0xc10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MTK_PIN_DRV_GRP(9, 0xc10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MTK_PIN_DRV_GRP(10, 0xc10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MTK_PIN_DRV_GRP(11, 0xc10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MTK_PIN_DRV_GRP(12, 0xb60, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MTK_PIN_DRV_GRP(13, 0xb60, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MTK_PIN_DRV_GRP(14, 0xb60, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MTK_PIN_DRV_GRP(15, 0xb60, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MTK_PIN_DRV_GRP(18, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MTK_PIN_DRV_GRP(19, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MTK_PIN_DRV_GRP(20, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MTK_PIN_DRV_GRP(21, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MTK_PIN_DRV_GRP(22, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MTK_PIN_DRV_GRP(23, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MTK_PIN_DRV_GRP(24, 0xb40, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MTK_PIN_DRV_GRP(25, 0xb40, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MTK_PIN_DRV_GRP(26, 0xb40, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MTK_PIN_DRV_GRP(27, 0xb50, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MTK_PIN_DRV_GRP(28, 0xb40, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MTK_PIN_DRV_GRP(29, 0xb40, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MTK_PIN_DRV_GRP(30, 0xf50, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MTK_PIN_DRV_GRP(31, 0xf50, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MTK_PIN_DRV_GRP(32, 0xf50, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MTK_PIN_DRV_GRP(33, 0xf50, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MTK_PIN_DRV_GRP(34, 0xf50, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MTK_PIN_DRV_GRP(35, 0xf50, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MTK_PIN_DRV_GRP(36, 0xf50, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MTK_PIN_DRV_GRP(37, 0xc40, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MTK_PIN_DRV_GRP(38, 0xc60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MTK_PIN_DRV_GRP(39, 0xc60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MTK_PIN_DRV_GRP(40, 0xc60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MTK_PIN_DRV_GRP(41, 0xc60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MTK_PIN_DRV_GRP(42, 0xc60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MTK_PIN_DRV_GRP(43, 0xc60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MTK_PIN_DRV_GRP(44, 0xc60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MTK_PIN_DRV_GRP(45, 0xc60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MTK_PIN_DRV_GRP(46, 0xc50, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MTK_PIN_DRV_GRP(47, 0xda0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MTK_PIN_DRV_GRP(48, 0xd90, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MTK_PIN_DRV_GRP(49, 0xd60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MTK_PIN_DRV_GRP(50, 0xd60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MTK_PIN_DRV_GRP(51, 0xd60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MTK_PIN_DRV_GRP(52, 0xd60, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MTK_PIN_DRV_GRP(53, 0xd50, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MTK_PIN_DRV_GRP(54, 0xd80, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MTK_PIN_DRV_GRP(55, 0xe00, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MTK_PIN_DRV_GRP(56, 0xd40, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MTK_PIN_DRV_GRP(63, 0xc80, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MTK_PIN_DRV_GRP(64, 0xca0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MTK_PIN_DRV_GRP(65, 0xca0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MTK_PIN_DRV_GRP(66, 0xca0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MTK_PIN_DRV_GRP(67, 0xcd0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MTK_PIN_DRV_GRP(68, 0xca0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MTK_PIN_DRV_GRP(69, 0xc90, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MTK_PIN_DRV_GRP(70, 0xcc0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MTK_PIN_DRV_GRP(71, 0xb60, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MTK_PIN_DRV_GRP(72, 0xb60, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MTK_PIN_DRV_GRP(73, 0xb60, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MTK_PIN_DRV_GRP(74, 0xb60, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MTK_PIN_DRV_GRP(75, 0xb60, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MTK_PIN_DRV_GRP(76, 0xb60, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MTK_PIN_DRV_GRP(77, 0xb60, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MTK_PIN_DRV_GRP(78, 0xb70, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MTK_PIN_DRV_GRP(79, 0xb70, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MTK_PIN_DRV_GRP(80, 0xb70, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MTK_PIN_DRV_GRP(81, 0xb70, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MTK_PIN_DRV_GRP(82, 0xb60, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MTK_PIN_DRV_GRP(83, 0xb60, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MTK_PIN_DRV_GRP(84, 0xb60, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MTK_PIN_DRV_GRP(85, 0xb60, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MTK_PIN_DRV_GRP(86, 0xb60, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MTK_PIN_DRV_GRP(87, 0xb60, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MTK_PIN_DRV_GRP(88, 0xb60, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MTK_PIN_DRV_GRP(89, 0xce0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MTK_PIN_DRV_GRP(90, 0xd00, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MTK_PIN_DRV_GRP(91, 0xd00, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MTK_PIN_DRV_GRP(92, 0xd00, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MTK_PIN_DRV_GRP(93, 0xd00, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MTK_PIN_DRV_GRP(94, 0xd20, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MTK_PIN_DRV_GRP(95, 0xcf0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MTK_PIN_DRV_GRP(96, 0xd30, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MTK_PIN_DRV_GRP(97, 0xb70, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MTK_PIN_DRV_GRP(98, 0xb70, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MTK_PIN_DRV_GRP(99, 0xb70, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MTK_PIN_DRV_GRP(100, 0xb70, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MTK_PIN_DRV_GRP(101, 0xb70, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MTK_PIN_DRV_GRP(102, 0xb70, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MTK_PIN_DRV_GRP(103, 0xb70, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MTK_PIN_DRV_GRP(104, 0xb70, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MTK_PIN_DRV_GRP(135, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MTK_PIN_DRV_GRP(136, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MTK_PIN_DRV_GRP(137, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MTK_PIN_DRV_GRP(138, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MTK_PIN_DRV_GRP(139, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MTK_PIN_DRV_GRP(140, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MTK_PIN_DRV_GRP(141, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MTK_PIN_DRV_GRP(142, 0xb40, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MTK_PIN_DRV_GRP(143, 0xba0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MTK_PIN_DRV_GRP(144, 0xba0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MTK_PIN_DRV_GRP(145, 0xba0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MTK_PIN_DRV_GRP(146, 0xba0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MTK_PIN_DRV_GRP(147, 0xba0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MTK_PIN_DRV_GRP(148, 0xbb0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MTK_PIN_DRV_GRP(149, 0xbb0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MTK_PIN_DRV_GRP(150, 0xbb0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MTK_PIN_DRV_GRP(151, 0xbb0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MTK_PIN_DRV_GRP(152, 0xbb0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MTK_PIN_DRV_GRP(153, 0xbb0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MTK_PIN_DRV_GRP(154, 0xbb0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MTK_PIN_DRV_GRP(155, 0xbb0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MTK_PIN_DRV_GRP(156, 0xbb0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MTK_PIN_DRV_GRP(157, 0xbb0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MTK_PIN_DRV_GRP(158, 0xbb0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MTK_PIN_DRV_GRP(159, 0xbb0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MTK_PIN_DRV_GRP(160, 0xbb0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MTK_PIN_DRV_GRP(161, 0xbb0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MTK_PIN_DRV_GRP(162, 0xbb0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MTK_PIN_DRV_GRP(163, 0xbb0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MTK_PIN_DRV_GRP(164, 0xbb0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MTK_PIN_DRV_GRP(165, 0xbc0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MTK_PIN_DRV_GRP(166, 0xbc0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MTK_PIN_DRV_GRP(167, 0xbc0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MTK_PIN_DRV_GRP(168, 0xbc0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MTK_PIN_DRV_GRP(169, 0xbc0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MTK_PIN_DRV_GRP(170, 0xbc0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MTK_PIN_DRV_GRP(171, 0xbc0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MTK_PIN_DRV_GRP(172, 0xbc0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MTK_PIN_DRV_GRP(173, 0xbc0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MTK_PIN_DRV_GRP(174, 0xbd0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MTK_PIN_DRV_GRP(175, 0xbd0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MTK_PIN_DRV_GRP(176, 0xbc0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MTK_PIN_DRV_GRP(177, 0xbd0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MTK_PIN_DRV_GRP(178, 0xbd0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MTK_PIN_DRV_GRP(179, 0xbd0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MTK_PIN_DRV_GRP(180, 0xbd0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MTK_PIN_DRV_GRP(181, 0xbd0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MTK_PIN_DRV_GRP(182, 0xbe0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MTK_PIN_DRV_GRP(183, 0xbd0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MTK_PIN_DRV_GRP(184, 0xbe0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MTK_PIN_DRV_GRP(185, 0xbe0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MTK_PIN_DRV_GRP(186, 0xbe0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MTK_PIN_DRV_GRP(187, 0xbe0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MTK_PIN_DRV_GRP(188, 0xbf0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MTK_PIN_DRV_GRP(189, 0xbe0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MTK_PIN_DRV_GRP(190, 0xbf0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MTK_PIN_DRV_GRP(191, 0xbf0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MTK_PIN_DRV_GRP(192, 0xbf0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MTK_PIN_DRV_GRP(193, 0xbf0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MTK_PIN_DRV_GRP(194, 0xbf0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MTK_PIN_DRV_GRP(195, 0xbf0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MTK_PIN_DRV_GRP(196, 0xbf0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MTK_PIN_DRV_GRP(197, 0xbf0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MTK_PIN_DRV_GRP(198, 0xbf0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) MTK_PIN_DRV_GRP(199, 0xbf0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MTK_PIN_DRV_GRP(200, 0xc00, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MTK_PIN_DRV_GRP(201, 0xc00, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MTK_PIN_DRV_GRP(202, 0xc00, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MTK_PIN_DRV_GRP(203, 0xc00, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MTK_PIN_DRV_GRP(204, 0xc00, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MTK_PIN_DRV_GRP(205, 0xc00, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MTK_PIN_DRV_GRP(206, 0xc00, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MTK_PIN_DRV_GRP(207, 0xc00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MTK_PIN_DRV_GRP(208, 0xc00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MTK_PIN_DRV_GRP(209, 0xc00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .pins = mtk_pins_mt2712,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .npins = ARRAY_SIZE(mtk_pins_mt2712),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .grp_desc = mt2712_drv_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .n_grp_cls = ARRAY_SIZE(mt2712_drv_grp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .pin_drv_grp = mt2712_pin_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .n_pin_drv_grps = ARRAY_SIZE(mt2712_pin_drv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .spec_pull_set = mt2712_spec_pull_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .spec_ies_smt_set = mt2712_ies_smt_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .dir_offset = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .pullen_offset = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .pullsel_offset = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .dout_offset = 0x0300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .din_offset = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .pinmux_offset = 0x0500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .type1_start = 210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .type1_end = 210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .port_shf = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .port_mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .port_align = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .eint_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .port_mask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .ports = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .ap_num = 229,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .db_cnt = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int mt2712_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return mtk_pctrl_init(pdev, &mt2712_pinctrl_data, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const struct of_device_id mt2712_pctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .compatible = "mediatek,mt2712-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) MODULE_DEVICE_TABLE(of, mt2712_pctrl_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct platform_driver mtk_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .probe = mt2712_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .name = "mediatek-mt2712-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .of_match_table = mt2712_pctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .pm = &mtk_eint_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static int __init mtk_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return platform_driver_register(&mtk_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) arch_initcall(mtk_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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