^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Biao Huang <biao.huang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <dt-bindings/pinctrl/mt65xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pinctrl-mtk-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-mtk-mt2701.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * struct mtk_spec_pinmux_set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * - For special pins' mode setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * @pin: The pin number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * @offset: The offset of extra setting register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @bit: The bit of extra setting register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct mtk_spec_pinmux_set {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned short pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned short offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) unsigned char bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MTK_PINMUX_SPEC(_pin, _offset, _bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .pin = _pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .offset = _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .bit = _bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct mtk_drv_group_desc mt2701_drv_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* 0E4E8SR 4/8/12/16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MTK_DRV_GRP(4, 16, 1, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* 0E2E4SR 2/4/6/8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MTK_DRV_GRP(2, 8, 1, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* E8E4E2 2/4/6/8/10/12/14/16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MTK_DRV_GRP(2, 16, 0, 2, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct mtk_pin_drv_grp mt2701_pin_drv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MTK_PIN_DRV_GRP(7, 0xf50, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MTK_PIN_DRV_GRP(8, 0xf50, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MTK_PIN_DRV_GRP(9, 0xf50, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MTK_PIN_DRV_GRP(10, 0xf50, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MTK_PIN_DRV_GRP(11, 0xf50, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MTK_PIN_DRV_GRP(12, 0xf50, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MTK_PIN_DRV_GRP(13, 0xf50, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MTK_PIN_DRV_GRP(14, 0xf50, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MTK_PIN_DRV_GRP(15, 0xf50, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MTK_PIN_DRV_GRP(16, 0xf60, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MTK_PIN_DRV_GRP(17, 0xf60, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MTK_PIN_DRV_GRP(18, 0xf60, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MTK_PIN_DRV_GRP(19, 0xf60, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MTK_PIN_DRV_GRP(20, 0xf60, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MTK_PIN_DRV_GRP(21, 0xf60, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MTK_PIN_DRV_GRP(22, 0xf60, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MTK_PIN_DRV_GRP(23, 0xf60, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MTK_PIN_DRV_GRP(24, 0xf60, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MTK_PIN_DRV_GRP(25, 0xf60, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MTK_PIN_DRV_GRP(26, 0xf60, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MTK_PIN_DRV_GRP(27, 0xf60, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MTK_PIN_DRV_GRP(28, 0xf60, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MTK_PIN_DRV_GRP(29, 0xf60, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MTK_PIN_DRV_GRP(30, 0xf60, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MTK_PIN_DRV_GRP(31, 0xf60, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MTK_PIN_DRV_GRP(32, 0xf60, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MTK_PIN_DRV_GRP(33, 0xf70, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MTK_PIN_DRV_GRP(34, 0xf70, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MTK_PIN_DRV_GRP(35, 0xf70, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MTK_PIN_DRV_GRP(36, 0xf70, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MTK_PIN_DRV_GRP(37, 0xf70, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MTK_PIN_DRV_GRP(38, 0xf70, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MTK_PIN_DRV_GRP(39, 0xf70, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MTK_PIN_DRV_GRP(40, 0xf70, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MTK_PIN_DRV_GRP(41, 0xf70, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MTK_PIN_DRV_GRP(42, 0xf70, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MTK_PIN_DRV_GRP(43, 0xf70, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MTK_PIN_DRV_GRP(44, 0xf70, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MTK_PIN_DRV_GRP(45, 0xf70, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MTK_PIN_DRV_GRP(47, 0xf80, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MTK_PIN_DRV_GRP(48, 0xf80, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MTK_PIN_DRV_GRP(49, 0xf80, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MTK_PIN_DRV_GRP(50, 0xf70, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MTK_PIN_DRV_GRP(51, 0xf70, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MTK_PIN_DRV_GRP(52, 0xf70, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MTK_PIN_DRV_GRP(53, 0xf80, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MTK_PIN_DRV_GRP(54, 0xf80, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MTK_PIN_DRV_GRP(55, 0xf80, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MTK_PIN_DRV_GRP(56, 0xf80, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MTK_PIN_DRV_GRP(60, 0xf90, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MTK_PIN_DRV_GRP(61, 0xf90, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MTK_PIN_DRV_GRP(62, 0xf90, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MTK_PIN_DRV_GRP(63, 0xf90, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MTK_PIN_DRV_GRP(64, 0xf90, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MTK_PIN_DRV_GRP(65, 0xf90, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MTK_PIN_DRV_GRP(66, 0xfa0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MTK_PIN_DRV_GRP(67, 0xfa0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MTK_PIN_DRV_GRP(68, 0xfa0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MTK_PIN_DRV_GRP(69, 0xfa0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MTK_PIN_DRV_GRP(70, 0xfa0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MTK_PIN_DRV_GRP(71, 0xfa0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MTK_PIN_DRV_GRP(72, 0xf80, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MTK_PIN_DRV_GRP(73, 0xf80, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MTK_PIN_DRV_GRP(74, 0xf80, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MTK_PIN_DRV_GRP(85, 0xda0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MTK_PIN_DRV_GRP(86, 0xd90, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MTK_PIN_DRV_GRP(87, 0xdb0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MTK_PIN_DRV_GRP(88, 0xdb0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MTK_PIN_DRV_GRP(89, 0xdb0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MTK_PIN_DRV_GRP(90, 0xdb0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MTK_PIN_DRV_GRP(105, 0xd40, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MTK_PIN_DRV_GRP(106, 0xd30, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MTK_PIN_DRV_GRP(107, 0xd50, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MTK_PIN_DRV_GRP(108, 0xd50, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MTK_PIN_DRV_GRP(109, 0xd50, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MTK_PIN_DRV_GRP(110, 0xd50, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MTK_PIN_DRV_GRP(111, 0xce0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MTK_PIN_DRV_GRP(112, 0xce0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MTK_PIN_DRV_GRP(113, 0xce0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MTK_PIN_DRV_GRP(114, 0xce0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MTK_PIN_DRV_GRP(115, 0xce0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MTK_PIN_DRV_GRP(116, 0xcd0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MTK_PIN_DRV_GRP(117, 0xcc0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MTK_PIN_DRV_GRP(118, 0xce0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MTK_PIN_DRV_GRP(119, 0xce0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MTK_PIN_DRV_GRP(120, 0xce0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MTK_PIN_DRV_GRP(121, 0xce0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MTK_PIN_DRV_GRP(126, 0xf80, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MTK_PIN_DRV_GRP(188, 0xf70, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MTK_PIN_DRV_GRP(189, 0xfe0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MTK_PIN_DRV_GRP(190, 0xfe0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MTK_PIN_DRV_GRP(191, 0xfe0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MTK_PIN_DRV_GRP(192, 0xfe0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MTK_PIN_DRV_GRP(193, 0xfe0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MTK_PIN_DRV_GRP(194, 0xfe0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MTK_PIN_DRV_GRP(195, 0xfe0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MTK_PIN_DRV_GRP(196, 0xfe0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MTK_PIN_DRV_GRP(197, 0xfe0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MTK_PIN_DRV_GRP(198, 0xfe0, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MTK_PIN_DRV_GRP(199, 0xf50, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MTK_PIN_DRV_GRP(200, 0xfd0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MTK_PIN_DRV_GRP(201, 0xfd0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MTK_PIN_DRV_GRP(202, 0xfd0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MTK_PIN_DRV_GRP(203, 0xfd0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MTK_PIN_DRV_GRP(204, 0xfd0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MTK_PIN_DRV_GRP(205, 0xfd0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MTK_PIN_DRV_GRP(206, 0xfd0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MTK_PIN_DRV_GRP(207, 0xfd0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MTK_PIN_DRV_GRP(208, 0xfd0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MTK_PIN_DRV_GRP(209, 0xfd0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MTK_PIN_DRV_GRP(210, 0xfd0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MTK_PIN_DRV_GRP(211, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MTK_PIN_DRV_GRP(212, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MTK_PIN_DRV_GRP(213, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MTK_PIN_DRV_GRP(214, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MTK_PIN_DRV_GRP(215, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MTK_PIN_DRV_GRP(216, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MTK_PIN_DRV_GRP(217, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MTK_PIN_DRV_GRP(218, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MTK_PIN_DRV_GRP(219, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MTK_PIN_DRV_GRP(220, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MTK_PIN_DRV_GRP(221, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MTK_PIN_DRV_GRP(222, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MTK_PIN_DRV_GRP(223, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MTK_PIN_DRV_GRP(224, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MTK_PIN_DRV_GRP(225, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MTK_PIN_DRV_GRP(226, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MTK_PIN_DRV_GRP(227, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MTK_PIN_DRV_GRP(228, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MTK_PIN_DRV_GRP(229, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MTK_PIN_DRV_GRP(230, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MTK_PIN_DRV_GRP(231, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MTK_PIN_DRV_GRP(232, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MTK_PIN_DRV_GRP(233, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MTK_PIN_DRV_GRP(234, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MTK_PIN_DRV_GRP(235, 0xff0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MTK_PIN_DRV_GRP(236, 0xff0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MTK_PIN_DRV_GRP(237, 0xff0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MTK_PIN_DRV_GRP(238, 0xff0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MTK_PIN_DRV_GRP(239, 0xff0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MTK_PIN_DRV_GRP(240, 0xff0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MTK_PIN_DRV_GRP(241, 0xff0, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MTK_PIN_DRV_GRP(242, 0xff0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MTK_PIN_DRV_GRP(243, 0xff0, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MTK_PIN_DRV_GRP(248, 0xf00, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MTK_PIN_DRV_GRP(249, 0xfc0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MTK_PIN_DRV_GRP(250, 0xfc0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MTK_PIN_DRV_GRP(251, 0xfc0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MTK_PIN_DRV_GRP(252, 0xfc0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MTK_PIN_DRV_GRP(253, 0xfc0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MTK_PIN_DRV_GRP(254, 0xfc0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MTK_PIN_DRV_GRP(255, 0xfc0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MTK_PIN_DRV_GRP(256, 0xfc0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MTK_PIN_DRV_GRP(257, 0xce0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MTK_PIN_DRV_GRP(258, 0xcb0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MTK_PIN_DRV_GRP(259, 0xc90, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MTK_PIN_DRV_GRP(260, 0x3a0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MTK_PIN_DRV_GRP(261, 0xd50, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MTK_PIN_DRV_GRP(262, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MTK_PIN_DRV_GRP(263, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MTK_PIN_DRV_GRP(264, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MTK_PIN_DRV_GRP(265, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MTK_PIN_DRV_GRP(266, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MTK_PIN_DRV_GRP(267, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MTK_PIN_DRV_GRP(268, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MTK_PIN_DRV_GRP(269, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MTK_PIN_DRV_GRP(270, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MTK_PIN_DRV_GRP(271, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MTK_PIN_DRV_GRP(272, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MTK_PIN_DRV_GRP(273, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MTK_PIN_DRV_GRP(274, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MTK_PIN_DRV_GRP(275, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MTK_PIN_DRV_GRP(276, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) MTK_PIN_DRV_GRP(277, 0xf00, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MTK_PIN_DRV_GRP(278, 0xf70, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct mtk_pin_spec_pupd_set_samereg mt2701_spec_pupd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MTK_PIN_PUPD_SPEC_SR(111, 0xd00, 12, 13, 14), /* ms0 data7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MTK_PIN_PUPD_SPEC_SR(112, 0xd00, 8, 9, 10), /* ms0 data6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MTK_PIN_PUPD_SPEC_SR(113, 0xd00, 4, 5, 6), /* ms0 data5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MTK_PIN_PUPD_SPEC_SR(114, 0xd00, 0, 1, 2), /* ms0 data4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MTK_PIN_PUPD_SPEC_SR(115, 0xd10, 0, 1, 2), /* ms0 rstb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MTK_PIN_PUPD_SPEC_SR(116, 0xcd0, 8, 9, 10), /* ms0 cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MTK_PIN_PUPD_SPEC_SR(117, 0xcc0, 8, 9, 10), /* ms0 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MTK_PIN_PUPD_SPEC_SR(118, 0xcf0, 12, 13, 14), /* ms0 data3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MTK_PIN_PUPD_SPEC_SR(119, 0xcf0, 8, 9, 10), /* ms0 data2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) MTK_PIN_PUPD_SPEC_SR(120, 0xcf0, 4, 5, 6), /* ms0 data1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) MTK_PIN_PUPD_SPEC_SR(121, 0xcf0, 0, 1, 2), /* ms0 data0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MTK_PIN_PUPD_SPEC_SR(105, 0xd40, 8, 9, 10), /* ms1 cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MTK_PIN_PUPD_SPEC_SR(106, 0xd30, 8, 9, 10), /* ms1 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MTK_PIN_PUPD_SPEC_SR(107, 0xd60, 0, 1, 2), /* ms1 dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MTK_PIN_PUPD_SPEC_SR(108, 0xd60, 10, 9, 8), /* ms1 dat1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MTK_PIN_PUPD_SPEC_SR(109, 0xd60, 4, 5, 6), /* ms1 dat2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MTK_PIN_PUPD_SPEC_SR(110, 0xc60, 12, 13, 14), /* ms1 dat3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MTK_PIN_PUPD_SPEC_SR(85, 0xda0, 8, 9, 10), /* ms2 cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MTK_PIN_PUPD_SPEC_SR(86, 0xd90, 8, 9, 10), /* ms2 clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MTK_PIN_PUPD_SPEC_SR(87, 0xdc0, 0, 1, 2), /* ms2 dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MTK_PIN_PUPD_SPEC_SR(88, 0xdc0, 10, 9, 8), /* ms2 dat1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MTK_PIN_PUPD_SPEC_SR(89, 0xdc0, 4, 5, 6), /* ms2 dat2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MTK_PIN_PUPD_SPEC_SR(90, 0xdc0, 12, 13, 14), /* ms2 dat3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MTK_PIN_PUPD_SPEC_SR(249, 0x140, 0, 1, 2), /* ms0e rstb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MTK_PIN_PUPD_SPEC_SR(250, 0x130, 12, 13, 14), /* ms0e dat7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MTK_PIN_PUPD_SPEC_SR(251, 0x130, 8, 9, 10), /* ms0e dat6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MTK_PIN_PUPD_SPEC_SR(252, 0x130, 4, 5, 6), /* ms0e dat5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MTK_PIN_PUPD_SPEC_SR(253, 0x130, 0, 1, 2), /* ms0e dat4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MTK_PIN_PUPD_SPEC_SR(254, 0xf40, 12, 13, 14), /* ms0e dat3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MTK_PIN_PUPD_SPEC_SR(255, 0xf40, 8, 9, 10), /* ms0e dat2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MTK_PIN_PUPD_SPEC_SR(256, 0xf40, 4, 5, 6), /* ms0e dat1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MTK_PIN_PUPD_SPEC_SR(257, 0xf40, 0, 1, 2), /* ms0e dat0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MTK_PIN_PUPD_SPEC_SR(258, 0xcb0, 8, 9, 10), /* ms0e cmd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MTK_PIN_PUPD_SPEC_SR(259, 0xc90, 8, 9, 10), /* ms0e clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MTK_PIN_PUPD_SPEC_SR(261, 0x140, 8, 9, 10), /* ms1 ins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int mt2701_spec_pull_set(struct regmap *regmap, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned char align, bool isup, unsigned int r1r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return mtk_pctrl_spec_pull_set_samereg(regmap, mt2701_spec_pupd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ARRAY_SIZE(mt2701_spec_pupd), pin, align, isup, r1r0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct mtk_pin_ies_smt_set mt2701_ies_set[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MTK_PIN_IES_SMT_SPEC(0, 6, 0xb20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MTK_PIN_IES_SMT_SPEC(7, 9, 0xb20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MTK_PIN_IES_SMT_SPEC(10, 13, 0xb30, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MTK_PIN_IES_SMT_SPEC(14, 15, 0xb30, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MTK_PIN_IES_SMT_SPEC(16, 17, 0xb40, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MTK_PIN_IES_SMT_SPEC(18, 21, 0xb40, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MTK_PIN_IES_SMT_SPEC(22, 26, 0xb40, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MTK_PIN_IES_SMT_SPEC(27, 29, 0xb40, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MTK_PIN_IES_SMT_SPEC(30, 32, 0xb40, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MTK_PIN_IES_SMT_SPEC(33, 37, 0xb40, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MTK_PIN_IES_SMT_SPEC(38, 38, 0xb20, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MTK_PIN_IES_SMT_SPEC(39, 42, 0xb40, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MTK_PIN_IES_SMT_SPEC(43, 45, 0xb20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MTK_PIN_IES_SMT_SPEC(47, 48, 0xb20, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MTK_PIN_IES_SMT_SPEC(49, 49, 0xb20, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MTK_PIN_IES_SMT_SPEC(50, 52, 0xb20, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MTK_PIN_IES_SMT_SPEC(53, 56, 0xb20, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MTK_PIN_IES_SMT_SPEC(57, 58, 0xb20, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MTK_PIN_IES_SMT_SPEC(59, 59, 0xb30, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) MTK_PIN_IES_SMT_SPEC(60, 62, 0xb30, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MTK_PIN_IES_SMT_SPEC(63, 65, 0xb30, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MTK_PIN_IES_SMT_SPEC(66, 71, 0xb30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MTK_PIN_IES_SMT_SPEC(72, 74, 0xb20, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MTK_PIN_IES_SMT_SPEC(75, 76, 0xb30, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MTK_PIN_IES_SMT_SPEC(77, 78, 0xb30, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MTK_PIN_IES_SMT_SPEC(79, 82, 0xb30, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MTK_PIN_IES_SMT_SPEC(83, 84, 0xb30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MTK_PIN_IES_SMT_SPEC(87, 90, 0xdb0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MTK_PIN_IES_SMT_SPEC(101, 104, 0xb30, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MTK_PIN_IES_SMT_SPEC(107, 110, 0xd50, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MTK_PIN_IES_SMT_SPEC(111, 115, 0xce0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MTK_PIN_IES_SMT_SPEC(118, 121, 0xce0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) MTK_PIN_IES_SMT_SPEC(122, 125, 0xb30, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MTK_PIN_IES_SMT_SPEC(126, 126, 0xb20, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) MTK_PIN_IES_SMT_SPEC(127, 142, 0xb30, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MTK_PIN_IES_SMT_SPEC(143, 160, 0xb30, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) MTK_PIN_IES_SMT_SPEC(161, 168, 0xb30, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) MTK_PIN_IES_SMT_SPEC(169, 183, 0xb30, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) MTK_PIN_IES_SMT_SPEC(184, 186, 0xb30, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MTK_PIN_IES_SMT_SPEC(187, 187, 0xb30, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) MTK_PIN_IES_SMT_SPEC(188, 188, 0xb20, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MTK_PIN_IES_SMT_SPEC(189, 193, 0xb30, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MTK_PIN_IES_SMT_SPEC(194, 198, 0xb40, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MTK_PIN_IES_SMT_SPEC(199, 199, 0xb20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MTK_PIN_IES_SMT_SPEC(200, 202, 0xb40, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MTK_PIN_IES_SMT_SPEC(203, 207, 0xb40, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MTK_PIN_IES_SMT_SPEC(208, 209, 0xb40, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MTK_PIN_IES_SMT_SPEC(210, 210, 0xb40, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MTK_PIN_IES_SMT_SPEC(211, 235, 0xb40, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MTK_PIN_IES_SMT_SPEC(236, 241, 0xb40, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MTK_PIN_IES_SMT_SPEC(242, 243, 0xb40, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MTK_PIN_IES_SMT_SPEC(244, 247, 0xb40, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MTK_PIN_IES_SMT_SPEC(248, 248, 0xb40, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MTK_PIN_IES_SMT_SPEC(249, 257, 0xfc0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MTK_PIN_IES_SMT_SPEC(261, 261, 0xd50, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MTK_PIN_IES_SMT_SPEC(262, 277, 0xb40, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MTK_PIN_IES_SMT_SPEC(278, 278, 0xb40, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct mtk_pin_ies_smt_set mt2701_smt_set[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MTK_PIN_IES_SMT_SPEC(0, 6, 0xb50, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MTK_PIN_IES_SMT_SPEC(7, 9, 0xb50, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MTK_PIN_IES_SMT_SPEC(10, 13, 0xb60, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MTK_PIN_IES_SMT_SPEC(14, 15, 0xb60, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MTK_PIN_IES_SMT_SPEC(16, 17, 0xb70, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MTK_PIN_IES_SMT_SPEC(18, 21, 0xb70, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MTK_PIN_IES_SMT_SPEC(22, 26, 0xb70, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MTK_PIN_IES_SMT_SPEC(27, 29, 0xb70, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MTK_PIN_IES_SMT_SPEC(30, 32, 0xb70, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MTK_PIN_IES_SMT_SPEC(33, 37, 0xb70, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MTK_PIN_IES_SMT_SPEC(38, 38, 0xb50, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MTK_PIN_IES_SMT_SPEC(39, 42, 0xb70, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MTK_PIN_IES_SMT_SPEC(43, 45, 0xb50, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MTK_PIN_IES_SMT_SPEC(47, 48, 0xb50, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MTK_PIN_IES_SMT_SPEC(49, 49, 0xb50, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MTK_PIN_IES_SMT_SPEC(50, 52, 0xb50, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MTK_PIN_IES_SMT_SPEC(53, 56, 0xb50, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MTK_PIN_IES_SMT_SPEC(57, 58, 0xb50, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MTK_PIN_IES_SMT_SPEC(59, 59, 0xb60, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MTK_PIN_IES_SMT_SPEC(60, 62, 0xb60, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MTK_PIN_IES_SMT_SPEC(63, 65, 0xb60, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MTK_PIN_IES_SMT_SPEC(66, 71, 0xb60, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MTK_PIN_IES_SMT_SPEC(72, 74, 0xb50, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MTK_PIN_IES_SMT_SPEC(75, 76, 0xb60, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MTK_PIN_IES_SMT_SPEC(77, 78, 0xb60, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MTK_PIN_IES_SMT_SPEC(79, 82, 0xb60, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MTK_PIN_IES_SMT_SPEC(83, 84, 0xb60, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MTK_PIN_IES_SMT_SPEC(85, 85, 0xda0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MTK_PIN_IES_SMT_SPEC(86, 86, 0xd90, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MTK_PIN_IES_SMT_SPEC(87, 87, 0xdc0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MTK_PIN_IES_SMT_SPEC(88, 88, 0xdc0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MTK_PIN_IES_SMT_SPEC(89, 89, 0xdc0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MTK_PIN_IES_SMT_SPEC(90, 90, 0xdc0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MTK_PIN_IES_SMT_SPEC(101, 104, 0xb60, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MTK_PIN_IES_SMT_SPEC(105, 105, 0xd40, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MTK_PIN_IES_SMT_SPEC(106, 106, 0xd30, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MTK_PIN_IES_SMT_SPEC(107, 107, 0xd60, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MTK_PIN_IES_SMT_SPEC(108, 108, 0xd60, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MTK_PIN_IES_SMT_SPEC(109, 109, 0xd60, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MTK_PIN_IES_SMT_SPEC(110, 110, 0xd60, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MTK_PIN_IES_SMT_SPEC(111, 111, 0xd00, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MTK_PIN_IES_SMT_SPEC(112, 112, 0xd00, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MTK_PIN_IES_SMT_SPEC(113, 113, 0xd00, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MTK_PIN_IES_SMT_SPEC(114, 114, 0xd00, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MTK_PIN_IES_SMT_SPEC(115, 115, 0xd10, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MTK_PIN_IES_SMT_SPEC(116, 116, 0xcd0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MTK_PIN_IES_SMT_SPEC(117, 117, 0xcc0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MTK_PIN_IES_SMT_SPEC(118, 118, 0xcf0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MTK_PIN_IES_SMT_SPEC(119, 119, 0xcf0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MTK_PIN_IES_SMT_SPEC(120, 120, 0xcf0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MTK_PIN_IES_SMT_SPEC(121, 121, 0xcf0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MTK_PIN_IES_SMT_SPEC(122, 125, 0xb60, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MTK_PIN_IES_SMT_SPEC(126, 126, 0xb50, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MTK_PIN_IES_SMT_SPEC(127, 142, 0xb60, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MTK_PIN_IES_SMT_SPEC(143, 160, 0xb60, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MTK_PIN_IES_SMT_SPEC(161, 168, 0xb60, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MTK_PIN_IES_SMT_SPEC(169, 183, 0xb60, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MTK_PIN_IES_SMT_SPEC(184, 186, 0xb60, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MTK_PIN_IES_SMT_SPEC(187, 187, 0xb60, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MTK_PIN_IES_SMT_SPEC(188, 188, 0xb50, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MTK_PIN_IES_SMT_SPEC(189, 193, 0xb60, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MTK_PIN_IES_SMT_SPEC(194, 198, 0xb70, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MTK_PIN_IES_SMT_SPEC(199, 199, 0xb50, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) MTK_PIN_IES_SMT_SPEC(200, 202, 0xb70, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MTK_PIN_IES_SMT_SPEC(203, 207, 0xb70, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MTK_PIN_IES_SMT_SPEC(208, 209, 0xb70, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MTK_PIN_IES_SMT_SPEC(210, 210, 0xb70, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MTK_PIN_IES_SMT_SPEC(211, 235, 0xb70, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MTK_PIN_IES_SMT_SPEC(236, 241, 0xb70, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MTK_PIN_IES_SMT_SPEC(242, 243, 0xb70, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MTK_PIN_IES_SMT_SPEC(244, 247, 0xb70, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MTK_PIN_IES_SMT_SPEC(248, 248, 0xb70, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MTK_PIN_IES_SMT_SPEC(249, 249, 0x140, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MTK_PIN_IES_SMT_SPEC(250, 250, 0x130, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MTK_PIN_IES_SMT_SPEC(251, 251, 0x130, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MTK_PIN_IES_SMT_SPEC(252, 252, 0x130, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MTK_PIN_IES_SMT_SPEC(253, 253, 0x130, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MTK_PIN_IES_SMT_SPEC(254, 254, 0xf40, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MTK_PIN_IES_SMT_SPEC(255, 255, 0xf40, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MTK_PIN_IES_SMT_SPEC(256, 256, 0xf40, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MTK_PIN_IES_SMT_SPEC(257, 257, 0xf40, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MTK_PIN_IES_SMT_SPEC(258, 258, 0xcb0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MTK_PIN_IES_SMT_SPEC(259, 259, 0xc90, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MTK_PIN_IES_SMT_SPEC(260, 260, 0x3a0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MTK_PIN_IES_SMT_SPEC(261, 261, 0x0b0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MTK_PIN_IES_SMT_SPEC(262, 277, 0xb70, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MTK_PIN_IES_SMT_SPEC(278, 278, 0xb70, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static int mt2701_ies_smt_set(struct regmap *regmap, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned char align, int value, enum pin_config_param arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (arg == PIN_CONFIG_INPUT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_ies_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ARRAY_SIZE(mt2701_ies_set), pin, align, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return mtk_pconf_spec_set_ies_smt_range(regmap, mt2701_smt_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ARRAY_SIZE(mt2701_smt_set), pin, align, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct mtk_spec_pinmux_set mt2701_spec_pinmux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MTK_PINMUX_SPEC(22, 0xb10, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MTK_PINMUX_SPEC(23, 0xb10, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MTK_PINMUX_SPEC(24, 0xb10, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MTK_PINMUX_SPEC(29, 0xb10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MTK_PINMUX_SPEC(208, 0xb10, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MTK_PINMUX_SPEC(209, 0xb10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MTK_PINMUX_SPEC(203, 0xf20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MTK_PINMUX_SPEC(204, 0xf20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MTK_PINMUX_SPEC(249, 0xef0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MTK_PINMUX_SPEC(250, 0xef0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MTK_PINMUX_SPEC(251, 0xef0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MTK_PINMUX_SPEC(252, 0xef0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MTK_PINMUX_SPEC(253, 0xef0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MTK_PINMUX_SPEC(254, 0xef0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MTK_PINMUX_SPEC(255, 0xef0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MTK_PINMUX_SPEC(256, 0xef0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MTK_PINMUX_SPEC(257, 0xef0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MTK_PINMUX_SPEC(258, 0xef0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MTK_PINMUX_SPEC(259, 0xef0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MTK_PINMUX_SPEC(260, 0xef0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void mt2701_spec_pinmux_set(struct regmap *reg, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned int i, value, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int info_num = ARRAY_SIZE(mt2701_spec_pinmux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned int spec_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) for (i = 0; i < info_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (pin == mt2701_spec_pinmux[i].pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (i == info_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) spec_flag = (mode >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) mask = BIT(mt2701_spec_pinmux[i].bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!spec_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) value = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) regmap_update_bits(reg, mt2701_spec_pinmux[i].offset, mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void mt2701_spec_dir_set(unsigned int *reg_addr, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (pin > 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) *reg_addr += 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .pins = mtk_pins_mt2701,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .npins = ARRAY_SIZE(mtk_pins_mt2701),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .grp_desc = mt2701_drv_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .n_grp_cls = ARRAY_SIZE(mt2701_drv_grp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .pin_drv_grp = mt2701_pin_drv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .n_pin_drv_grps = ARRAY_SIZE(mt2701_pin_drv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .spec_pull_set = mt2701_spec_pull_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .spec_ies_smt_set = mt2701_ies_smt_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .spec_pinmux_set = mt2701_spec_pinmux_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .spec_dir_set = mt2701_spec_dir_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .dir_offset = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .pullen_offset = 0x0150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .pullsel_offset = 0x0280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .dout_offset = 0x0500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .din_offset = 0x0630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .pinmux_offset = 0x0760,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .type1_start = 280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .type1_end = 280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .port_shf = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .port_mask = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .port_align = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .eint_hw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .port_mask = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .ports = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .ap_num = 169,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .db_cnt = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int mt2701_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return mtk_pctrl_init(pdev, &mt2701_pinctrl_data, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct of_device_id mt2701_pctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { .compatible = "mediatek,mt2701-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { .compatible = "mediatek,mt7623-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MODULE_DEVICE_TABLE(of, mt2701_pctrl_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct platform_driver mtk_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .probe = mt2701_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .name = "mediatek-mt2701-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .of_match_table = mt2701_pctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .pm = &mtk_eint_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int __init mtk_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return platform_driver_register(&mtk_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) arch_initcall(mtk_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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