^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MediaTek Pinctrl Moore Driver, which implement the generic dt-binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * pinctrl-bindings.txt for MediaTek SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2017-2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "pinctrl-moore.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Custom pinconf parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct pinconf_generic_params mtk_custom_bindings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const struct pin_config_item mtk_conf_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int selector, unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct function_desc *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct group_desc *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) func = pinmux_generic_get_function(pctldev, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (!func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) grp = pinctrl_generic_get_group(pctldev, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (!grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dev_dbg(pctldev->dev, "enable function %s group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) func->name, grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) for (i = 0; i < grp->num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int *pin_modes = grp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int pin = grp->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pin_modes[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) hw->soc->gpio_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int pin, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* hardware would take 0 as input direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int val, val2, err, reg, ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (hw->soc->bias_disable_get) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) err = hw->soc->bias_disable_get(hw, desc, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (hw->soc->bias_get) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) err = hw->soc->bias_get(hw, desc, 1, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (hw->soc->bias_get) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) err = hw->soc->bias_get(hw, desc, 0, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case PIN_CONFIG_OUTPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* HW takes input mode as zero; output mode as non-zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (val || !val2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (hw->soc->drive_get) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) err = hw->soc->drive_get(hw, desc, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case MTK_PIN_CONFIG_TDSEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case MTK_PIN_CONFIG_RDSEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) reg = (param == MTK_PIN_CONFIG_TDSEL) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) err = mtk_hw_get_value(hw, desc, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case MTK_PIN_CONFIG_PU_ADV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case MTK_PIN_CONFIG_PD_ADV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (hw->soc->adv_pull_get) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) bool pullup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) pullup = param == MTK_PIN_CONFIG_PU_ADV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *config = pinconf_to_config_packed(param, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 reg, param, arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int cfg, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) for (cfg = 0; cfg < num_configs; cfg++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) param = pinconf_to_config_param(configs[cfg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) arg = pinconf_to_config_argument(configs[cfg]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (hw->soc->bias_disable_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) err = hw->soc->bias_disable_set(hw, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (hw->soc->bias_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) err = hw->soc->bias_set(hw, desc, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (hw->soc->bias_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) err = hw->soc->bias_set(hw, desc, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) case PIN_CONFIG_OUTPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MTK_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MTK_OUTPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (hw->soc->ies_present) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MTK_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MTK_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MTK_OUTPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* arg = 1: Input mode & SMT enable ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * arg = 0: Output mode & SMT disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) arg = arg ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) arg & 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) !!(arg & 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (hw->soc->drive_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) err = hw->soc->drive_set(hw, desc, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case MTK_PIN_CONFIG_TDSEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case MTK_PIN_CONFIG_RDSEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) reg = (param == MTK_PIN_CONFIG_TDSEL) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) err = mtk_hw_set_value(hw, desc, reg, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case MTK_PIN_CONFIG_PU_ADV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case MTK_PIN_CONFIG_PD_ADV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (hw->soc->adv_pull_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bool pullup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) pullup = param == MTK_PIN_CONFIG_PU_ADV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) err = hw->soc->adv_pull_set(hw, desc, pullup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) err = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int mtk_pinconf_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) unsigned int group, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) unsigned int i, npins, old = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (mtk_pinconf_get(pctldev, pins[i], config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* configs do not match between two pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (i && old != *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) old = *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int mtk_pinconf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int group, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int i, npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = mtk_pinconf_set(pctldev, pins[i], configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct pinctrl_ops mtk_pctlops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .get_groups_count = pinctrl_generic_get_group_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .get_group_name = pinctrl_generic_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .get_group_pins = pinctrl_generic_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .dt_free_map = pinconf_generic_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct pinmux_ops mtk_pmxops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .get_functions_count = pinmux_generic_get_function_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .get_function_name = pinmux_generic_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .get_function_groups = pinmux_generic_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .set_mux = mtk_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .gpio_request_enable = mtk_pinmux_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .gpio_set_direction = mtk_pinmux_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .strict = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const struct pinconf_ops mtk_confops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .pin_config_get = mtk_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .pin_config_set = mtk_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .pin_config_group_get = mtk_pinconf_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .pin_config_group_set = mtk_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .pin_config_config_dbg_show = pinconf_generic_dump_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static struct pinctrl_desc mtk_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .name = PINCTRL_PINCTRL_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .pctlops = &mtk_pctlops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .pmxops = &mtk_pmxops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .confops = &mtk_confops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct mtk_pinctrl *hw = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int value, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return !!value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct mtk_pinctrl *hw = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return pinctrl_gpio_direction_input(chip->base + gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mtk_gpio_set(chip, gpio, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return pinctrl_gpio_direction_output(chip->base + gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct mtk_pinctrl *hw = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!hw->eint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (desc->eint.eint_n == (u16)EINT_NA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct mtk_pinctrl *hw = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) const struct mtk_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!hw->eint ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) desc->eint.eint_n == (u16)EINT_NA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct gpio_chip *chip = &hw->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) chip->label = PINCTRL_PINCTRL_DEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) chip->parent = hw->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) chip->request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) chip->free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) chip->direction_input = mtk_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) chip->direction_output = mtk_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) chip->get = mtk_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) chip->set = mtk_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) chip->to_irq = mtk_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) chip->set_config = mtk_gpio_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) chip->ngpio = hw->soc->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) chip->of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) chip->of_gpio_n_cells = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = gpiochip_add_data(chip, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Just for backward compatible for these old pinctrl nodes without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * "gpio-ranges" property. Otherwise, called directly from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * DeviceTree-supported pinctrl driver is DEPRECATED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * Please see Section 2.1 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * Documentation/devicetree/bindings/gpio/gpio.txt on how to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * bind pinctrl and gpio drivers via the "gpio-ranges" property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!of_find_property(np, "gpio-ranges", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = gpiochip_add_pin_range(chip, dev_name(hw->dev), 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) chip->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) gpiochip_remove(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static int mtk_build_groups(struct mtk_pinctrl *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) for (i = 0; i < hw->soc->ngrps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) const struct group_desc *group = hw->soc->grps + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) err = pinctrl_generic_add_group(hw->pctrl, group->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) group->pins, group->num_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) group->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) dev_err(hw->dev, "Failed to register group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) group->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int mtk_build_functions(struct mtk_pinctrl *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) for (i = 0; i < hw->soc->nfuncs ; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) const struct function_desc *func = hw->soc->funcs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) err = pinmux_generic_add_function(hw->pctrl, func->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) func->group_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) func->num_group_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) func->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_err(hw->dev, "Failed to register function %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) func->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int mtk_moore_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) const struct mtk_pin_soc *soc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct mtk_pinctrl *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) hw->soc = soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) hw->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (!hw->soc->nbase_names) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) "SoC should be assigned at least one register base\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) sizeof(*hw->base), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (!hw->base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) for (i = 0; i < hw->soc->nbase_names; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) hw->soc->base_names[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (IS_ERR(hw->base[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return PTR_ERR(hw->base[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) hw->nbase = hw->soc->nbase_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Copy from internal struct mtk_pin_desc to register to the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) for (i = 0; i < hw->soc->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pins[i].number = hw->soc->pins[i].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pins[i].name = hw->soc->pins[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Setup pins descriptions per SoC types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) mtk_desc.npins = hw->soc->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mtk_desc.custom_params = mtk_custom_bindings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) mtk_desc.custom_conf_items = mtk_conf_items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) &hw->pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Setup groups descriptions per SoC types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) err = mtk_build_groups(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_err(&pdev->dev, "Failed to build groups\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Setup functions descriptions per SoC types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) err = mtk_build_functions(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_err(&pdev->dev, "Failed to build functions\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* For able to make pinctrl_claim_hogs, we must not enable pinctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * until all groups and functions are being added one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) err = pinctrl_enable(hw->pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) err = mtk_build_eint(hw, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "Failed to add EINT, but pinctrl still can work\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Build gpiochip should be after pinctrl_enable is done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) err = mtk_build_gpiochip(hw, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dev_err(&pdev->dev, "Failed to add gpio_chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) platform_set_drvdata(pdev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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