^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Tiger Lake PCH pinctrl/GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2019 - 2020, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TGL_PAD_OWN 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TGL_LP_PADCFGLOCK 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TGL_H_PADCFGLOCK 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TGL_LP_HOSTSW_OWN 0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TGL_H_HOSTSW_OWN 0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TGL_GPI_IS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TGL_GPI_IE 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TGL_GPP(r, s, e, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .reg_num = (r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .size = ((e) - (s) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .gpio_base = (g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TGL_COMMUNITY(b, s, e, pl, ho, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .barno = (b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .padown_offset = TGL_PAD_OWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .padcfglock_offset = (pl), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .hostown_offset = (ho), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .is_offset = TGL_GPI_IS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .ie_offset = TGL_GPI_IE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .pin_base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .npins = ((e) - (s) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .gpps = (g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .ngpps = ARRAY_SIZE(g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TGL_LP_COMMUNITY(b, s, e, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) TGL_COMMUNITY(b, s, e, TGL_LP_PADCFGLOCK, TGL_LP_HOSTSW_OWN, g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TGL_H_COMMUNITY(b, s, e, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) TGL_COMMUNITY(b, s, e, TGL_H_PADCFGLOCK, TGL_H_HOSTSW_OWN, g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Tiger Lake-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct pinctrl_pin_desc tgllp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PINCTRL_PIN(0, "CORE_VID_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN(1, "CORE_VID_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN(2, "VRALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN(3, "CPU_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN(4, "CPU_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN(5, "ISH_I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN(6, "ISH_I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINCTRL_PIN(7, "ISH_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN(8, "ISH_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN(9, "I2C5_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN(10, "I2C5_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN(11, "PMCALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN(12, "SLP_S0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(13, "PLTRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINCTRL_PIN(14, "SPKR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(15, "GSPI0_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(16, "GSPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINCTRL_PIN(17, "GSPI0_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(18, "GSPI0_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINCTRL_PIN(19, "GSPI1_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(20, "GSPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PINCTRL_PIN(21, "GSPI1_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINCTRL_PIN(22, "GSPI1_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINCTRL_PIN(23, "SML1ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* GPP_T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINCTRL_PIN(26, "I2C6_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(27, "I2C6_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(28, "I2C7_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(29, "I2C7_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINCTRL_PIN(30, "UART4_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(31, "UART4_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(32, "UART4_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(33, "UART4_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(34, "UART5_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(35, "UART5_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(36, "UART5_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(37, "UART5_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(38, "UART6_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(39, "UART6_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(40, "UART6_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(41, "UART6_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(42, "ESPI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(43, "ESPI_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(44, "ESPI_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(45, "ESPI_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(46, "ESPI_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(47, "ESPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(48, "ESPI_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(49, "I2S2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(50, "I2S2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(51, "I2S2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(52, "I2S2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(53, "PMC_I2C_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(54, "SATAXPCIE_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(55, "PMC_I2C_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(56, "USB2_OCB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(57, "USB2_OCB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(58, "USB2_OCB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(59, "DDSP_HPD_C"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(60, "DDSP_HPD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(61, "DDSP_HPD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(62, "DDSP_HPD_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(63, "GPPC_A_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(64, "GPPC_A_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(65, "I2S1_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* GPP_S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(67, "SNDW0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(68, "SNDW0_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(69, "SNDW1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(70, "SNDW1_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(71, "SNDW2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(72, "SNDW2_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(73, "SNDW3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(74, "SNDW3_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(75, "GPPC_H_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(76, "GPPC_H_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(77, "GPPC_H_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(79, "I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(80, "I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(81, "I2C3_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(82, "I2C3_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(83, "I2C4_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(84, "I2C4_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(85, "SRCCLKREQB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(86, "SRCCLKREQB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(87, "M2_SKT2_CFG_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(88, "M2_SKT2_CFG_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(89, "M2_SKT2_CFG_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(90, "M2_SKT2_CFG_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(91, "DDPB_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(92, "DDPB_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(93, "CPU_C10_GATEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(94, "TIME_SYNC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(95, "IMGCLKOUT_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(96, "IMGCLKOUT_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(97, "IMGCLKOUT_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(98, "IMGCLKOUT_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(99, "ISH_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(100, "ISH_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(101, "ISH_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(102, "ISH_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(103, "IMGCLKOUT_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(104, "SRCCLKREQB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(105, "SRCCLKREQB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(106, "SRCCLKREQB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(107, "SRCCLKREQB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(108, "ISH_SPI_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(109, "ISH_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(110, "ISH_SPI_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(111, "ISH_SPI_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(112, "ISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(113, "ISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(114, "ISH_UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(115, "ISH_UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(116, "ISH_GP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(117, "ISH_GP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(118, "I2S_MCLK1_OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* GPP_U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(120, "UART3_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(121, "UART3_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(122, "UART3_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(123, "UART3_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(124, "GSPI3_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(125, "GSPI3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(126, "GSPI3_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(127, "GSPI3_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(128, "GSPI4_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(129, "GSPI4_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(130, "GSPI4_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(131, "GSPI4_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(132, "GSPI5_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(133, "GSPI5_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(134, "GSPI5_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(135, "GSPI5_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(136, "GSPI6_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(137, "GSPI6_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(138, "GSPI6_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(139, "GSPI6_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* vGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(144, "CNV_BTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(155, "vUART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(156, "vUART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(157, "vUART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(158, "vUART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(159, "vISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(160, "vISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(161, "vISH_UART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(162, "vISH_UART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(165, "vCNV_BT_I2S_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(166, "vCNV_BT_I2S_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(167, "vI2S2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(168, "vI2S2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(169, "vI2S2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(170, "vI2S2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(171, "SMBCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(172, "SMBDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(173, "SMBALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(174, "SML0CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(175, "SML0DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(176, "SML0ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(177, "SML1CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(178, "SML1DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(179, "UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(180, "UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(181, "UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(182, "UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(183, "UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(184, "UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(185, "UART1_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(186, "UART1_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(187, "I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(188, "I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(189, "I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(190, "I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(191, "UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(192, "UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(193, "UART2_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(194, "UART2_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(195, "CNV_BRI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(196, "CNV_BRI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(197, "CNV_RGI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(198, "CNV_RGI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(199, "CNV_RF_RESET_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(200, "GPPC_F_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(201, "CNV_PA_BLANKING"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(202, "GPPC_F_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(203, "I2S_MCLK2_INOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(204, "BOOTMPC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(205, "GPPC_F_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(206, "GPPC_F_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(207, "GSXDOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(208, "GSXSLOAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(209, "GSXDIN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(210, "GSXSRESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(211, "GSXCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(212, "GMII_MDC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(213, "GMII_MDIO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(214, "SRCCLKREQB_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(215, "EXT_PWR_GATEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(216, "EXT_PWR_GATE2B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(217, "VNN_CTRL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(218, "V1P05_CTRL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* HVCMOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(220, "L_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(221, "L_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(222, "L_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(223, "SYS_PWROK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(224, "SYS_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(225, "MLK_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(226, "SATAXPCIE_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(227, "SPI1_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(228, "SPI1_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(229, "CPU_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(230, "SATA_DEVSLP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(231, "SATA_DEVSLP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(232, "GPPC_E_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(233, "CPU_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(234, "SPI1_CS1B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(235, "USB2_OCB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(236, "SPI1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(237, "SPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(238, "SPI1_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(239, "SPI1_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(240, "DDSP_HPD_A"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(241, "ISH_GP_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(242, "ISH_GP_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(243, "GPPC_E_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(244, "DDP1_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(245, "DDP1_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(246, "DDP2_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(247, "DDP2_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(248, "DDPA_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(249, "DDPA_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* JTAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(251, "JTAG_TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(252, "JTAGX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(253, "PRDYB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(254, "PREQB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(255, "CPU_TRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(256, "JTAG_TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(257, "JTAG_TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(258, "JTAG_TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(259, "DBG_PMODE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* GPP_R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(260, "HDA_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(261, "HDA_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(262, "HDA_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(263, "HDA_SDI_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(264, "HDA_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(265, "HDA_SDI_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(266, "GPP_R_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(267, "GPP_R_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(268, "SPI0_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(269, "SPI0_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(270, "SPI0_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(271, "SPI0_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(272, "SPI0_TPM_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(273, "SPI0_FLASH_0_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(274, "SPI0_FLASH_1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(275, "SPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const struct intel_padgroup tgllp_community0_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) TGL_GPP(0, 0, 25, 0), /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) TGL_GPP(1, 26, 41, 32), /* GPP_T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) TGL_GPP(2, 42, 66, 64), /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const struct intel_padgroup tgllp_community1_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) TGL_GPP(0, 67, 74, 96), /* GPP_S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) TGL_GPP(1, 75, 98, 128), /* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) TGL_GPP(2, 99, 119, 160), /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) TGL_GPP(3, 120, 143, 192), /* GPP_U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) TGL_GPP(4, 144, 170, 224), /* vGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct intel_padgroup tgllp_community4_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) TGL_GPP(0, 171, 194, 256), /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) TGL_GPP(1, 195, 219, 288), /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) TGL_GPP(3, 226, 250, 320), /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct intel_padgroup tgllp_community5_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) TGL_GPP(0, 260, 267, 352), /* GPP_R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct intel_community tgllp_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) TGL_LP_COMMUNITY(0, 0, 66, tgllp_community0_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) TGL_LP_COMMUNITY(1, 67, 170, tgllp_community1_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) TGL_LP_COMMUNITY(2, 171, 259, tgllp_community4_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) TGL_LP_COMMUNITY(3, 260, 276, tgllp_community5_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const struct intel_pinctrl_soc_data tgllp_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .pins = tgllp_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .npins = ARRAY_SIZE(tgllp_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .communities = tgllp_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .ncommunities = ARRAY_SIZE(tgllp_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Tiger Lake-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct pinctrl_pin_desc tglh_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINCTRL_PIN(0, "SPI0_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINCTRL_PIN(1, "SPI0_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINCTRL_PIN(4, "SPI0_TPM_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINCTRL_PIN(7, "SPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINCTRL_PIN(8, "ESPI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINCTRL_PIN(9, "ESPI_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINCTRL_PIN(10, "ESPI_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PINCTRL_PIN(11, "ESPI_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PINCTRL_PIN(12, "ESPI_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PINCTRL_PIN(13, "ESPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PINCTRL_PIN(14, "ESPI_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINCTRL_PIN(15, "ESPI_CS1B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PINCTRL_PIN(16, "ESPI_CS2B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PINCTRL_PIN(17, "ESPI_CS3B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINCTRL_PIN(18, "ESPI_ALERT0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINCTRL_PIN(19, "ESPI_ALERT1B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PINCTRL_PIN(20, "ESPI_ALERT2B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINCTRL_PIN(21, "ESPI_ALERT3B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PINCTRL_PIN(22, "GPPC_A_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINCTRL_PIN(23, "SPI0_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* GPP_R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINCTRL_PIN(25, "HDA_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINCTRL_PIN(26, "HDA_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINCTRL_PIN(27, "HDA_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINCTRL_PIN(28, "HDA_SDI_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINCTRL_PIN(29, "HDA_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINCTRL_PIN(30, "HDA_SDI_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINCTRL_PIN(31, "GPP_R_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINCTRL_PIN(32, "GPP_R_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINCTRL_PIN(33, "GPP_R_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINCTRL_PIN(34, "PCIE_LNK_DOWN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINCTRL_PIN(35, "ISH_UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINCTRL_PIN(36, "SX_EXIT_HOLDOFFB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINCTRL_PIN(37, "CLKOUT_48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINCTRL_PIN(38, "ISH_GP_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINCTRL_PIN(39, "ISH_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINCTRL_PIN(40, "ISH_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINCTRL_PIN(41, "ISH_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PINCTRL_PIN(42, "ISH_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINCTRL_PIN(43, "ISH_GP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINCTRL_PIN(44, "ISH_GP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINCTRL_PIN(45, "GSPI0_CS1B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINCTRL_PIN(46, "GSPI1_CS1B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINCTRL_PIN(47, "VRALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINCTRL_PIN(48, "CPU_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINCTRL_PIN(49, "CPU_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINCTRL_PIN(50, "SRCCLKREQB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINCTRL_PIN(51, "SRCCLKREQB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PINCTRL_PIN(52, "SRCCLKREQB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PINCTRL_PIN(53, "SRCCLKREQB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PINCTRL_PIN(54, "SRCCLKREQB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PINCTRL_PIN(55, "SRCCLKREQB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PINCTRL_PIN(56, "I2S_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PINCTRL_PIN(57, "SLP_S0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PINCTRL_PIN(58, "PLTRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINCTRL_PIN(59, "SPKR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PINCTRL_PIN(60, "GSPI0_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINCTRL_PIN(61, "GSPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINCTRL_PIN(62, "GSPI0_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINCTRL_PIN(63, "GSPI0_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINCTRL_PIN(64, "GSPI1_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PINCTRL_PIN(65, "GSPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINCTRL_PIN(66, "GSPI1_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINCTRL_PIN(67, "GSPI1_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINCTRL_PIN(68, "SML1ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINCTRL_PIN(69, "GSPI0_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PINCTRL_PIN(70, "GSPI1_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* vGPIO_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINCTRL_PIN(71, "ESPI_USB_OCB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINCTRL_PIN(72, "ESPI_USB_OCB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINCTRL_PIN(73, "ESPI_USB_OCB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PINCTRL_PIN(74, "ESPI_USB_OCB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINCTRL_PIN(75, "USB_CPU_OCB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINCTRL_PIN(76, "USB_CPU_OCB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINCTRL_PIN(77, "USB_CPU_OCB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINCTRL_PIN(78, "USB_CPU_OCB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINCTRL_PIN(79, "SPI1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINCTRL_PIN(80, "SPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINCTRL_PIN(81, "SPI1_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINCTRL_PIN(82, "SPI1_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINCTRL_PIN(83, "SML1CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINCTRL_PIN(84, "I2S2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINCTRL_PIN(85, "I2S2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINCTRL_PIN(86, "I2S2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINCTRL_PIN(87, "I2S2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINCTRL_PIN(88, "SML0CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINCTRL_PIN(89, "SML0DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINCTRL_PIN(90, "GPP_D_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINCTRL_PIN(91, "ISH_UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PINCTRL_PIN(92, "SPI1_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PINCTRL_PIN(93, "SPI1_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINCTRL_PIN(94, "SML1DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINCTRL_PIN(95, "GSPI3_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINCTRL_PIN(96, "GSPI3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINCTRL_PIN(97, "GSPI3_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PINCTRL_PIN(98, "GSPI3_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PINCTRL_PIN(99, "UART3_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINCTRL_PIN(100, "UART3_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINCTRL_PIN(101, "UART3_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINCTRL_PIN(102, "UART3_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINCTRL_PIN(103, "SPI1_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINCTRL_PIN(104, "GSPI3_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PINCTRL_PIN(105, "SMBCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINCTRL_PIN(106, "SMBDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PINCTRL_PIN(107, "SMBALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINCTRL_PIN(108, "ISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINCTRL_PIN(109, "ISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PINCTRL_PIN(110, "SML0ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PINCTRL_PIN(111, "ISH_I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PINCTRL_PIN(112, "ISH_I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PINCTRL_PIN(113, "UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PINCTRL_PIN(114, "UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PINCTRL_PIN(115, "UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PINCTRL_PIN(116, "UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PINCTRL_PIN(117, "UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PINCTRL_PIN(118, "UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PINCTRL_PIN(119, "UART1_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) PINCTRL_PIN(120, "UART1_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PINCTRL_PIN(121, "I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PINCTRL_PIN(122, "I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PINCTRL_PIN(123, "I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) PINCTRL_PIN(124, "I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PINCTRL_PIN(125, "UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINCTRL_PIN(126, "UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PINCTRL_PIN(127, "UART2_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PINCTRL_PIN(128, "UART2_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* GPP_S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PINCTRL_PIN(129, "SNDW1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PINCTRL_PIN(130, "SNDW1_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PINCTRL_PIN(131, "SNDW2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PINCTRL_PIN(132, "SNDW2_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINCTRL_PIN(133, "SNDW3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINCTRL_PIN(134, "SNDW3_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINCTRL_PIN(135, "SNDW4_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINCTRL_PIN(136, "SNDW4_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINCTRL_PIN(137, "DDPA_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINCTRL_PIN(138, "DDPA_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINCTRL_PIN(139, "DNX_FORCE_RELOAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINCTRL_PIN(140, "GMII_MDC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINCTRL_PIN(141, "GMII_MDIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PINCTRL_PIN(142, "SLP_DRAMB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINCTRL_PIN(143, "GPPC_G_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINCTRL_PIN(144, "GPPC_G_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINCTRL_PIN(145, "ISH_SPI_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINCTRL_PIN(146, "ISH_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINCTRL_PIN(147, "ISH_SPI_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINCTRL_PIN(148, "ISH_SPI_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINCTRL_PIN(149, "DDP1_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINCTRL_PIN(150, "DDP1_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PINCTRL_PIN(151, "DDP2_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PINCTRL_PIN(152, "DDP2_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINCTRL_PIN(153, "GSPI2_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* vGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PINCTRL_PIN(154, "CNV_BTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PINCTRL_PIN(155, "CNV_BT_HOST_WAKEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINCTRL_PIN(156, "CNV_BT_IF_SELECT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINCTRL_PIN(157, "vCNV_BT_UART_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINCTRL_PIN(158, "vCNV_BT_UART_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PINCTRL_PIN(159, "vCNV_BT_UART_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PINCTRL_PIN(160, "vCNV_BT_UART_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINCTRL_PIN(161, "vCNV_MFUART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINCTRL_PIN(162, "vCNV_MFUART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PINCTRL_PIN(163, "vCNV_MFUART1_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINCTRL_PIN(164, "vCNV_MFUART1_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PINCTRL_PIN(165, "vUART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINCTRL_PIN(166, "vUART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PINCTRL_PIN(167, "vUART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINCTRL_PIN(168, "vUART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINCTRL_PIN(169, "vISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINCTRL_PIN(170, "vISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PINCTRL_PIN(171, "vISH_UART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINCTRL_PIN(172, "vISH_UART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINCTRL_PIN(173, "vCNV_BT_I2S_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINCTRL_PIN(174, "vCNV_BT_I2S_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINCTRL_PIN(175, "vCNV_BT_I2S_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINCTRL_PIN(176, "vCNV_BT_I2S_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINCTRL_PIN(177, "vI2S2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINCTRL_PIN(178, "vI2S2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINCTRL_PIN(179, "vI2S2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINCTRL_PIN(180, "vI2S2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINCTRL_PIN(181, "SATAXPCIE_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINCTRL_PIN(182, "SATAXPCIE_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINCTRL_PIN(183, "SATAXPCIE_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINCTRL_PIN(184, "CPU_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINCTRL_PIN(185, "SATA_DEVSLP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINCTRL_PIN(186, "SATA_DEVSLP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PINCTRL_PIN(187, "SATA_DEVSLP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINCTRL_PIN(188, "CPU_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINCTRL_PIN(189, "SATA_LEDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINCTRL_PIN(190, "USB2_OCB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINCTRL_PIN(191, "USB2_OCB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINCTRL_PIN(192, "USB2_OCB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINCTRL_PIN(193, "USB2_OCB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINCTRL_PIN(194, "SATAXPCIE_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINCTRL_PIN(195, "SATAXPCIE_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINCTRL_PIN(196, "SATAXPCIE_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINCTRL_PIN(197, "SATAXPCIE_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINCTRL_PIN(198, "SATAXPCIE_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINCTRL_PIN(199, "SATA_DEVSLP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PINCTRL_PIN(200, "SATA_DEVSLP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINCTRL_PIN(201, "SATA_DEVSLP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINCTRL_PIN(202, "SATA_DEVSLP_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINCTRL_PIN(203, "SATA_DEVSLP_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINCTRL_PIN(204, "SATA_SCLOCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINCTRL_PIN(205, "SATA_SLOAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINCTRL_PIN(206, "SATA_SDATAOUT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINCTRL_PIN(207, "SATA_SDATAOUT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINCTRL_PIN(208, "PS_ONB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINCTRL_PIN(209, "M2_SKT2_CFG_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINCTRL_PIN(210, "M2_SKT2_CFG_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINCTRL_PIN(211, "M2_SKT2_CFG_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PINCTRL_PIN(212, "M2_SKT2_CFG_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINCTRL_PIN(213, "L_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PINCTRL_PIN(214, "L_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINCTRL_PIN(215, "L_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINCTRL_PIN(216, "VNN_CTRL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINCTRL_PIN(217, "GPP_F_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINCTRL_PIN(218, "SRCCLKREQB_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINCTRL_PIN(219, "SRCCLKREQB_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINCTRL_PIN(220, "SRCCLKREQB_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINCTRL_PIN(221, "SRCCLKREQB_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINCTRL_PIN(222, "SRCCLKREQB_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINCTRL_PIN(223, "SRCCLKREQB_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINCTRL_PIN(224, "SRCCLKREQB_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINCTRL_PIN(225, "SRCCLKREQB_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINCTRL_PIN(226, "SRCCLKREQB_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINCTRL_PIN(227, "SRCCLKREQB_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINCTRL_PIN(228, "SML2CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PINCTRL_PIN(229, "SML2DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINCTRL_PIN(230, "SML2ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINCTRL_PIN(231, "SML3CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINCTRL_PIN(232, "SML3DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PINCTRL_PIN(233, "SML3ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINCTRL_PIN(234, "SML4CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINCTRL_PIN(235, "SML4DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINCTRL_PIN(236, "SML4ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PINCTRL_PIN(237, "ISH_I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINCTRL_PIN(238, "ISH_I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINCTRL_PIN(239, "ISH_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PINCTRL_PIN(240, "ISH_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PINCTRL_PIN(241, "TIME_SYNC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* GPP_J */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINCTRL_PIN(242, "CNV_PA_BLANKING"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINCTRL_PIN(243, "CPU_C10_GATEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PINCTRL_PIN(244, "CNV_BRI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINCTRL_PIN(245, "CNV_BRI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINCTRL_PIN(246, "CNV_RGI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINCTRL_PIN(247, "CNV_RGI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINCTRL_PIN(248, "CNV_MFUART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINCTRL_PIN(249, "CNV_MFUART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINCTRL_PIN(250, "GPP_J_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINCTRL_PIN(251, "GPP_J_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* GPP_K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINCTRL_PIN(252, "GSXDOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PINCTRL_PIN(253, "GSXSLOAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINCTRL_PIN(254, "GSXDIN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PINCTRL_PIN(255, "GSXSRESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINCTRL_PIN(256, "GSXCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINCTRL_PIN(257, "ADR_COMPLETE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PINCTRL_PIN(258, "DDSP_HPD_A"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINCTRL_PIN(259, "DDSP_HPD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PINCTRL_PIN(260, "CORE_VID_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINCTRL_PIN(261, "CORE_VID_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINCTRL_PIN(262, "DDSP_HPD_C"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINCTRL_PIN(263, "GPP_K_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PINCTRL_PIN(264, "SYS_PWROK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINCTRL_PIN(265, "SYS_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINCTRL_PIN(266, "MLK_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* GPP_I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINCTRL_PIN(267, "PMCALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINCTRL_PIN(268, "DDSP_HPD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PINCTRL_PIN(269, "DDSP_HPD_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINCTRL_PIN(270, "DDSP_HPD_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINCTRL_PIN(271, "DDSP_HPD_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINCTRL_PIN(272, "DDPB_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PINCTRL_PIN(273, "DDPB_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINCTRL_PIN(274, "DDPC_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINCTRL_PIN(275, "DDPC_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PINCTRL_PIN(276, "FUSA_DIAGTEST_EN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINCTRL_PIN(277, "FUSA_DIAGTEST_MODE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINCTRL_PIN(278, "USB2_OCB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINCTRL_PIN(279, "USB2_OCB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINCTRL_PIN(280, "USB2_OCB_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINCTRL_PIN(281, "USB2_OCB_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* JTAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PINCTRL_PIN(282, "JTAG_TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINCTRL_PIN(283, "JTAGX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINCTRL_PIN(284, "PRDYB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINCTRL_PIN(285, "PREQB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINCTRL_PIN(286, "JTAG_TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PINCTRL_PIN(287, "JTAG_TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PINCTRL_PIN(288, "JTAG_TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINCTRL_PIN(289, "DBG_PMODE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINCTRL_PIN(290, "CPU_TRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const struct intel_padgroup tglh_community0_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) TGL_GPP(0, 0, 24, 0), /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) TGL_GPP(1, 25, 44, 32), /* GPP_R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) TGL_GPP(2, 45, 70, 64), /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) TGL_GPP(3, 71, 78, 96), /* vGPIO_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const struct intel_padgroup tglh_community1_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) TGL_GPP(0, 79, 104, 128), /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) TGL_GPP(1, 105, 128, 160), /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) TGL_GPP(2, 129, 136, 192), /* GPP_S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) TGL_GPP(3, 137, 153, 224), /* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) TGL_GPP(4, 154, 180, 256), /* vGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const struct intel_padgroup tglh_community3_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) TGL_GPP(0, 181, 193, 288), /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) TGL_GPP(1, 194, 217, 320), /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const struct intel_padgroup tglh_community4_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) TGL_GPP(0, 218, 241, 352), /* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) TGL_GPP(1, 242, 251, 384), /* GPP_J */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) TGL_GPP(2, 252, 266, 416), /* GPP_K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static const struct intel_padgroup tglh_community5_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) TGL_GPP(0, 267, 281, 448), /* GPP_I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static const struct intel_community tglh_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) TGL_H_COMMUNITY(0, 0, 78, tglh_community0_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) TGL_H_COMMUNITY(1, 79, 180, tglh_community1_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) TGL_H_COMMUNITY(2, 181, 217, tglh_community3_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) TGL_H_COMMUNITY(3, 218, 266, tglh_community4_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) TGL_H_COMMUNITY(4, 267, 290, tglh_community5_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const struct intel_pinctrl_soc_data tglh_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .pins = tglh_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .npins = ARRAY_SIZE(tglh_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .communities = tglh_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .ncommunities = ARRAY_SIZE(tglh_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) { "INT34C5", (kernel_ulong_t)&tgllp_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) { "INT34C6", (kernel_ulong_t)&tglh_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static struct platform_driver tgl_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .probe = intel_pinctrl_probe_by_hid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .name = "tigerlake-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .acpi_match_table = tgl_pinctrl_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .pm = &tgl_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) module_platform_driver(tgl_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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