^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Sunrisepoint PCH pinctrl/GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPT_PAD_OWN 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPT_H_PADCFGLOCK 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPT_LP_PADCFGLOCK 0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPT_HOSTSW_OWN 0x0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPT_GPI_IS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPT_GPI_IE 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPT_COMMUNITY(b, s, e, pl, gs, gn, g, n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .barno = (b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .padown_offset = SPT_PAD_OWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .padcfglock_offset = (pl), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .hostown_offset = SPT_HOSTSW_OWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .is_offset = SPT_GPI_IS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .ie_offset = SPT_GPI_IE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .gpp_size = (gs), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .gpp_num_padown_regs = (gn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .pin_base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .npins = ((e) - (s) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .gpps = (g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .ngpps = (n), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPT_LP_COMMUNITY(b, s, e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SPT_COMMUNITY(b, s, e, SPT_LP_PADCFGLOCK, 24, 4, NULL, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPT_H_GPP(r, s, e, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .reg_num = (r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .size = ((e) - (s) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .gpio_base = (g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPT_H_COMMUNITY(b, s, e, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SPT_COMMUNITY(b, s, e, SPT_H_PADCFGLOCK, 0, 0, g, ARRAY_SIZE(g))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Sunrisepoint-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const struct pinctrl_pin_desc sptlp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN(0, "RCINB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN(1, "LAD_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN(2, "LAD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN(3, "LAD_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN(4, "LAD_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN(5, "LFRAMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINCTRL_PIN(6, "SERIQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN(7, "PIRQAB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN(8, "CLKRUNB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN(9, "CLKOUT_LPC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN(10, "CLKOUT_LPC_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN(11, "PMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(12, "BM_BUSYB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(14, "SUS_STATB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(15, "SUSACKB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINCTRL_PIN(16, "SD_1P8_SEL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(17, "SD_PWR_EN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINCTRL_PIN(18, "ISH_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(19, "ISH_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PINCTRL_PIN(20, "ISH_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINCTRL_PIN(21, "ISH_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINCTRL_PIN(22, "ISH_GP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINCTRL_PIN(23, "ISH_GP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PINCTRL_PIN(24, "CORE_VID_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINCTRL_PIN(25, "CORE_VID_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(26, "VRALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(27, "CPU_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(28, "CPU_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINCTRL_PIN(29, "SRCCLKREQB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(30, "SRCCLKREQB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(31, "SRCCLKREQB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(32, "SRCCLKREQB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(33, "SRCCLKREQB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(34, "SRCCLKREQB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(35, "EXT_PWR_GATEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(36, "SLP_S0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(37, "PLTRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(38, "SPKR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(39, "GSPI0_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(40, "GSPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(41, "GSPI0_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(42, "GSPI0_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(43, "GSPI1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(44, "GSPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(45, "GSPI1_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(46, "GSPI1_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(47, "SML1ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(48, "SMBCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(49, "SMBDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(50, "SMBALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(51, "SML0CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(52, "SML0DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(53, "SML0ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(54, "SML1CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(55, "SML1DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(56, "UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(57, "UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(58, "UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(59, "UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(60, "UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(61, "UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(62, "UART1_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(63, "UART1_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(64, "I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(65, "I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(66, "I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(67, "I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(68, "UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(69, "UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(70, "UART2_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(71, "UART2_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(72, "SPI1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(73, "SPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(76, "FLASHTRIG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(77, "ISH_I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(78, "ISH_I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(79, "ISH_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(80, "ISH_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(81, "ISH_SPI_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(82, "ISH_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(83, "ISH_SPI_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(84, "ISH_SPI_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(85, "ISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(86, "ISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(87, "ISH_UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(88, "ISH_UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(89, "DMIC_CLK_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(90, "DMIC_DATA_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(91, "DMIC_CLK_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(92, "DMIC_DATA_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(93, "SPI1_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(94, "SPI1_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(95, "SSP_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(96, "SATAXPCIE_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(97, "SATAXPCIE_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(98, "SATAXPCIE_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(99, "CPU_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(100, "SATA_DEVSLP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(101, "SATA_DEVSLP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(102, "SATA_DEVSLP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(103, "CPU_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(104, "SATA_LEDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(105, "USB2_OCB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(106, "USB2_OCB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(107, "USB2_OCB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(108, "USB2_OCB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(109, "DDSP_HPD_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(110, "DDSP_HPD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(111, "DDSP_HPD_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(112, "DDSP_HPD_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(113, "EDP_HPD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(114, "DDPB_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(115, "DDPB_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(116, "DDPC_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(117, "DDPC_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(118, "DDPD_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(119, "DDPD_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(120, "SSP2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(121, "SSP2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(122, "SSP2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(123, "SSP2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(124, "I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(125, "I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(126, "I2C3_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(127, "I2C3_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(128, "I2C4_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(129, "I2C4_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(130, "I2C5_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(131, "I2C5_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(132, "EMMC_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(133, "EMMC_DATA_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(134, "EMMC_DATA_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(135, "EMMC_DATA_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(136, "EMMC_DATA_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(137, "EMMC_DATA_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(138, "EMMC_DATA_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(139, "EMMC_DATA_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(140, "EMMC_DATA_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(141, "EMMC_RCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(142, "EMMC_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(143, "GPP_F_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(144, "SD_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(145, "SD_DATA_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(146, "SD_DATA_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(147, "SD_DATA_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(148, "SD_DATA_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(149, "SD_CDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(150, "SD_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(151, "SD_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const unsigned sptlp_i2c0_pins[] = { 64, 65 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const unsigned sptlp_i2c1_pins[] = { 66, 67 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const unsigned sptlp_i2c2_pins[] = { 124, 125 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const unsigned sptlp_i2c3_pins[] = { 126, 127 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const unsigned sptlp_i2c4_pins[] = { 128, 129 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const unsigned sptlp_i2c4b_pins[] = { 85, 86 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const unsigned sptlp_i2c5_pins[] = { 130, 131 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const unsigned sptlp_emmc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const unsigned sptlp_sd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 144, 145, 146, 147, 148, 149, 150, 151,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct intel_pingroup sptlp_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PIN_GROUP("sd_grp", sptlp_sd_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const char * const sptlp_spi0_groups[] = { "spi0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const char * const sptlp_spi1_groups[] = { "spi0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const char * const sptlp_uart0_groups[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const char * const sptlp_uart1_groups[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const char * const sptlp_uart2_groups[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const char * const sptlp_emmc_groups[] = { "emmc_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const char * const sptlp_sd_groups[] = { "sd_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const struct intel_function sptlp_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) FUNCTION("spi0", sptlp_spi0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) FUNCTION("spi1", sptlp_spi1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FUNCTION("uart0", sptlp_uart0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FUNCTION("uart1", sptlp_uart1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FUNCTION("uart2", sptlp_uart2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) FUNCTION("i2c0", sptlp_i2c0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) FUNCTION("i2c1", sptlp_i2c1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) FUNCTION("i2c2", sptlp_i2c2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) FUNCTION("i2c3", sptlp_i2c3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) FUNCTION("i2c4", sptlp_i2c4_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) FUNCTION("i2c5", sptlp_i2c5_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) FUNCTION("ssp2", sptlp_ssp2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) FUNCTION("emmc", sptlp_emmc_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) FUNCTION("sd", sptlp_sd_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct intel_community sptlp_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SPT_LP_COMMUNITY(0, 0, 47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) SPT_LP_COMMUNITY(1, 48, 119),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) SPT_LP_COMMUNITY(2, 120, 151),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const struct intel_pinctrl_soc_data sptlp_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .pins = sptlp_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .npins = ARRAY_SIZE(sptlp_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .groups = sptlp_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .ngroups = ARRAY_SIZE(sptlp_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .functions = sptlp_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .nfunctions = ARRAY_SIZE(sptlp_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .communities = sptlp_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .ncommunities = ARRAY_SIZE(sptlp_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Sunrisepoint-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct pinctrl_pin_desc spth_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(0, "RCINB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(1, "LAD_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(2, "LAD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(3, "LAD_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(4, "LAD_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(5, "LFRAMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(6, "SERIQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(7, "PIRQAB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(8, "CLKRUNB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(9, "CLKOUT_LPC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(10, "CLKOUT_LPC_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(11, "PMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(12, "BM_BUSYB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(14, "SUS_STATB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(15, "SUSACKB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(16, "CLKOUT_48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(17, "ISH_GP_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(18, "ISH_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(19, "ISH_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(20, "ISH_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(21, "ISH_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(22, "ISH_GP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(23, "ISH_GP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(24, "CORE_VID_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(25, "CORE_VID_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(26, "VRALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(27, "CPU_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(28, "CPU_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_PIN(29, "SRCCLKREQB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(30, "SRCCLKREQB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(31, "SRCCLKREQB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(32, "SRCCLKREQB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(33, "SRCCLKREQB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(34, "SRCCLKREQB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(35, "EXT_PWR_GATEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(36, "SLP_S0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(37, "PLTRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(38, "SPKR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_PIN(39, "GSPI0_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINCTRL_PIN(40, "GSPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINCTRL_PIN(41, "GSPI0_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINCTRL_PIN(42, "GSPI0_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PINCTRL_PIN(43, "GSPI1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINCTRL_PIN(44, "GSPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINCTRL_PIN(45, "GSPI1_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINCTRL_PIN(46, "GSPI1_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINCTRL_PIN(47, "SML1ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PINCTRL_PIN(48, "SMBCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PINCTRL_PIN(49, "SMBDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINCTRL_PIN(50, "SMBALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PINCTRL_PIN(51, "SML0CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PINCTRL_PIN(52, "SML0DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINCTRL_PIN(53, "SML0ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINCTRL_PIN(54, "SML1CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINCTRL_PIN(55, "SML1DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PINCTRL_PIN(56, "UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINCTRL_PIN(57, "UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINCTRL_PIN(58, "UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINCTRL_PIN(59, "UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PINCTRL_PIN(60, "UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PINCTRL_PIN(61, "UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PINCTRL_PIN(62, "UART1_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINCTRL_PIN(63, "UART1_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PINCTRL_PIN(64, "I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINCTRL_PIN(65, "I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINCTRL_PIN(66, "I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PINCTRL_PIN(67, "I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINCTRL_PIN(68, "UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINCTRL_PIN(69, "UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINCTRL_PIN(70, "UART2_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINCTRL_PIN(71, "UART2_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINCTRL_PIN(72, "SPI1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINCTRL_PIN(73, "SPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINCTRL_PIN(76, "ISH_I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINCTRL_PIN(77, "SSP0_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINCTRL_PIN(78, "SSP0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINCTRL_PIN(79, "SSP0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PINCTRL_PIN(80, "SSP0_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINCTRL_PIN(81, "ISH_SPI_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINCTRL_PIN(82, "ISH_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINCTRL_PIN(83, "ISH_SPI_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINCTRL_PIN(84, "ISH_SPI_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PINCTRL_PIN(85, "ISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINCTRL_PIN(86, "ISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINCTRL_PIN(87, "ISH_UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINCTRL_PIN(88, "ISH_UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINCTRL_PIN(89, "DMIC_CLK_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINCTRL_PIN(90, "DMIC_DATA_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINCTRL_PIN(91, "DMIC_CLK_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINCTRL_PIN(92, "DMIC_DATA_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINCTRL_PIN(93, "SPI1_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PINCTRL_PIN(94, "SPI1_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PINCTRL_PIN(95, "ISH_I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PINCTRL_PIN(96, "SATAXPCIE_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINCTRL_PIN(97, "SATAXPCIE_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PINCTRL_PIN(98, "SATAXPCIE_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PINCTRL_PIN(99, "CPU_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINCTRL_PIN(100, "SATA_DEVSLP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINCTRL_PIN(101, "SATA_DEVSLP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PINCTRL_PIN(102, "SATA_DEVSLP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINCTRL_PIN(103, "CPU_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PINCTRL_PIN(104, "SATA_LEDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINCTRL_PIN(105, "USB2_OCB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PINCTRL_PIN(106, "USB2_OCB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINCTRL_PIN(107, "USB2_OCB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINCTRL_PIN(108, "USB2_OCB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINCTRL_PIN(109, "SATAXPCIE_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINCTRL_PIN(110, "SATAXPCIE_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINCTRL_PIN(111, "SATAXPCIE_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINCTRL_PIN(112, "SATAXPCIE_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINCTRL_PIN(113, "SATAXPCIE_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINCTRL_PIN(114, "SATA_DEVSLP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINCTRL_PIN(115, "SATA_DEVSLP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINCTRL_PIN(116, "SATA_DEVSLP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINCTRL_PIN(117, "SATA_DEVSLP_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINCTRL_PIN(118, "SATA_DEVSLP_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINCTRL_PIN(119, "SATA_SCLOCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINCTRL_PIN(120, "SATA_SLOAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINCTRL_PIN(121, "SATA_SDATAOUT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINCTRL_PIN(122, "SATA_SDATAOUT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINCTRL_PIN(123, "GPP_F_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PINCTRL_PIN(124, "USB_OCB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINCTRL_PIN(125, "USB_OCB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINCTRL_PIN(126, "USB_OCB_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINCTRL_PIN(127, "USB_OCB_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINCTRL_PIN(128, "L_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINCTRL_PIN(129, "L_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINCTRL_PIN(130, "L_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINCTRL_PIN(131, "GPP_F_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINCTRL_PIN(132, "GPP_F_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINCTRL_PIN(133, "FAN_TACH_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PINCTRL_PIN(134, "FAN_TACH_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PINCTRL_PIN(135, "FAN_TACH_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PINCTRL_PIN(136, "FAN_TACH_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PINCTRL_PIN(137, "FAN_TACH_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PINCTRL_PIN(138, "FAN_TACH_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PINCTRL_PIN(139, "FAN_TACH_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PINCTRL_PIN(140, "FAN_TACH_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINCTRL_PIN(141, "FAN_PWM_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PINCTRL_PIN(142, "FAN_PWM_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINCTRL_PIN(143, "FAN_PWM_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINCTRL_PIN(144, "FAN_PWM_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINCTRL_PIN(145, "GSXDOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINCTRL_PIN(146, "GSXSLOAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PINCTRL_PIN(147, "GSXDIN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINCTRL_PIN(148, "GSXRESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINCTRL_PIN(149, "GSXCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINCTRL_PIN(150, "ADR_COMPLETE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINCTRL_PIN(151, "NMIB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PINCTRL_PIN(152, "SMIB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PINCTRL_PIN(153, "GPP_G_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINCTRL_PIN(154, "GPP_G_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINCTRL_PIN(155, "GPP_G_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINCTRL_PIN(156, "GPP_G_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINCTRL_PIN(157, "SRCCLKREQB_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINCTRL_PIN(158, "SRCCLKREQB_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINCTRL_PIN(159, "SRCCLKREQB_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINCTRL_PIN(160, "SRCCLKREQB_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINCTRL_PIN(161, "SRCCLKREQB_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINCTRL_PIN(162, "SRCCLKREQB_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINCTRL_PIN(163, "SRCCLKREQB_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINCTRL_PIN(164, "SRCCLKREQB_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINCTRL_PIN(165, "SRCCLKREQB_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINCTRL_PIN(166, "SRCCLKREQB_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINCTRL_PIN(167, "SML2CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINCTRL_PIN(168, "SML2DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINCTRL_PIN(169, "SML2ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINCTRL_PIN(170, "SML3CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINCTRL_PIN(171, "SML3DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINCTRL_PIN(172, "SML3ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINCTRL_PIN(173, "SML4CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINCTRL_PIN(174, "SML4DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PINCTRL_PIN(175, "SML4ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PINCTRL_PIN(176, "ISH_I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINCTRL_PIN(177, "ISH_I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINCTRL_PIN(178, "ISH_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINCTRL_PIN(179, "ISH_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINCTRL_PIN(180, "GPP_H_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* GPP_I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PINCTRL_PIN(181, "DDSP_HDP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINCTRL_PIN(182, "DDSP_HDP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINCTRL_PIN(183, "DDSP_HDP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINCTRL_PIN(184, "DDSP_HDP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINCTRL_PIN(185, "EDP_HPD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINCTRL_PIN(186, "DDPB_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PINCTRL_PIN(187, "DDPB_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PINCTRL_PIN(188, "DDPC_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINCTRL_PIN(189, "DDPC_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PINCTRL_PIN(190, "DDPD_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINCTRL_PIN(191, "DDPD_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static const unsigned spth_spi0_pins[] = { 39, 40, 41, 42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const unsigned spth_spi1_pins[] = { 43, 44, 45, 46 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const unsigned spth_uart0_pins[] = { 56, 57, 58, 59 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const unsigned spth_uart1_pins[] = { 60, 61, 62, 63 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const unsigned spth_uart2_pins[] = { 68, 69, 71, 71 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static const unsigned spth_i2c0_pins[] = { 64, 65 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const unsigned spth_i2c1_pins[] = { 66, 67 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const unsigned spth_i2c2_pins[] = { 76, 95 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static const struct intel_pingroup spth_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PIN_GROUP("spi0_grp", spth_spi0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PIN_GROUP("spi1_grp", spth_spi1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PIN_GROUP("uart0_grp", spth_uart0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) PIN_GROUP("uart1_grp", spth_uart1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PIN_GROUP("uart2_grp", spth_uart2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PIN_GROUP("i2c0_grp", spth_i2c0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PIN_GROUP("i2c1_grp", spth_i2c1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PIN_GROUP("i2c2_grp", spth_i2c2_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const char * const spth_spi0_groups[] = { "spi0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const char * const spth_spi1_groups[] = { "spi0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const char * const spth_uart0_groups[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const char * const spth_uart1_groups[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const char * const spth_uart2_groups[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const char * const spth_i2c0_groups[] = { "i2c0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const char * const spth_i2c1_groups[] = { "i2c1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const char * const spth_i2c2_groups[] = { "i2c2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct intel_function spth_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) FUNCTION("spi0", spth_spi0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) FUNCTION("spi1", spth_spi1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) FUNCTION("uart0", spth_uart0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) FUNCTION("uart1", spth_uart1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) FUNCTION("uart2", spth_uart2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) FUNCTION("i2c0", spth_i2c0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) FUNCTION("i2c1", spth_i2c1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) FUNCTION("i2c2", spth_i2c2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static const struct intel_padgroup spth_community0_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) SPT_H_GPP(0, 0, 23, 0), /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SPT_H_GPP(1, 24, 47, 24), /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const struct intel_padgroup spth_community1_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) SPT_H_GPP(0, 48, 71, 48), /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) SPT_H_GPP(1, 72, 95, 72), /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) SPT_H_GPP(2, 96, 108, 96), /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) SPT_H_GPP(3, 109, 132, 120), /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) SPT_H_GPP(4, 133, 156, 144), /* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) SPT_H_GPP(5, 157, 180, 168), /* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const struct intel_padgroup spth_community3_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) SPT_H_GPP(0, 181, 191, 192), /* GPP_I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const struct intel_community spth_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) SPT_H_COMMUNITY(0, 0, 47, spth_community0_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) SPT_H_COMMUNITY(1, 48, 180, spth_community1_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) SPT_H_COMMUNITY(2, 181, 191, spth_community3_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct intel_pinctrl_soc_data spth_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .pins = spth_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .npins = ARRAY_SIZE(spth_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .groups = spth_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .ngroups = ARRAY_SIZE(spth_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .functions = spth_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .nfunctions = ARRAY_SIZE(spth_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .communities = spth_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .ncommunities = ARRAY_SIZE(spth_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { "INT344B", (kernel_ulong_t)&sptlp_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { "INT3451", (kernel_ulong_t)&spth_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { "INT345D", (kernel_ulong_t)&spth_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static INTEL_PINCTRL_PM_OPS(spt_pinctrl_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static struct platform_driver spt_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .probe = intel_pinctrl_probe_by_hid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .name = "sunrisepoint-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .acpi_match_table = spt_pinctrl_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .pm = &spt_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int __init spt_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return platform_driver_register(&spt_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) subsys_initcall(spt_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static void __exit spt_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) platform_driver_unregister(&spt_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) module_exit(spt_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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