^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Merrifield SoC pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "pinctrl-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MRFLD_FAMILY_NR 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MRFLD_FAMILY_LEN 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SLEW_OFFSET 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BUFCFG_OFFSET 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MISC_OFFSET 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BUFCFG_PINMODE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BUFCFG_PINMODE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BUFCFG_PINMODE_GPIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BUFCFG_PUPD_VAL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BUFCFG_PUPD_VAL_2K 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BUFCFG_PUPD_VAL_20K 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BUFCFG_PUPD_VAL_50K 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BUFCFG_PUPD_VAL_910 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BUFCFG_PU_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BUFCFG_PD_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BUFCFG_Px_EN_MASK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BUFCFG_SLEWSEL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BUFCFG_OVINEN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BUFCFG_OVINEN_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BUFCFG_OVINEN_MASK GENMASK(13, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BUFCFG_OVOUTEN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BUFCFG_OVOUTEN_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BUFCFG_OVOUTEN_MASK GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BUFCFG_INDATAOV_VAL BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BUFCFG_INDATAOV_EN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BUFCFG_INDATAOV_MASK GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BUFCFG_OUTDATAOV_VAL BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BUFCFG_OUTDATAOV_EN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BUFCFG_OD_EN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * struct mrfld_family - Intel pin family description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @barno: MMIO BAR number where registers for this family reside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @pin_base: Starting pin of pins in this family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @npins: Number of pins in this family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @protected: True if family is protected by access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @regs: family specific common registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct mrfld_family {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int barno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) size_t npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool protected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MRFLD_FAMILY(b, s, e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .barno = (b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .pin_base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .npins = (e) - (s) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MRFLD_FAMILY_PROTECTED(b, s, e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .barno = (b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .pin_base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .npins = (e) - (s) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .protected = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const struct pinctrl_pin_desc mrfld_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Family 0: OCP2SSC (0 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Family 1: ULPI (13 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(0, "ULPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(1, "ULPI_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(2, "ULPI_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(3, "ULPI_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(4, "ULPI_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(5, "ULPI_D4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(6, "ULPI_D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(7, "ULPI_D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(8, "ULPI_D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(9, "ULPI_DIR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(10, "ULPI_NXT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(11, "ULPI_REFCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(12, "ULPI_STP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Family 2: eMMC (24 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(13, "EMMC_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(14, "EMMC_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(15, "EMMC_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(16, "EMMC_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(17, "EMMC_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(18, "EMMC_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(19, "EMMC_D4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(20, "EMMC_D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(21, "EMMC_D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(22, "EMMC_D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(23, "EMMC_RST_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(24, "GP154"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(25, "GP155"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(26, "GP156"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(27, "GP157"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(28, "GP158"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(29, "GP159"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(30, "GP160"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(31, "GP161"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(32, "GP162"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(33, "GP163"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(34, "GP97"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(35, "GP14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(36, "GP15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Family 3: SDIO (20 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(37, "GP77_SD_CD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(38, "GP78_SD_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(39, "GP79_SD_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(40, "GP80_SD_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(41, "GP81_SD_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(42, "GP82_SD_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(43, "GP83_SD_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(44, "GP84_SD_LS_CLK_FB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(45, "GP85_SD_LS_CMD_DIR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(46, "GP86_SD_LS_D_DIR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(47, "GP88_SD_LS_SEL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(48, "GP87_SD_PD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(49, "GP89_SD_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(50, "GP90_SDIO_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(51, "GP91_SDIO_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(52, "GP92_SDIO_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(53, "GP93_SDIO_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(54, "GP94_SDIO_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(55, "GP95_SDIO_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(56, "GP96_SDIO_PD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Family 4: HSI (8 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(57, "HSI_ACDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(58, "HSI_ACFLAG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(59, "HSI_ACREADY"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(60, "HSI_ACWAKE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(61, "HSI_CADATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(62, "HSI_CAFLAG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(63, "HSI_CAREADY"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(64, "HSI_CAWAKE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Family 5: SSP Audio (14 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(65, "GP70"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(66, "GP71"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(67, "GP32_I2S_0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(68, "GP33_I2S_0_FS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(69, "GP34_I2S_0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(70, "GP35_I2S_0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(71, "GP36_I2S_1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(72, "GP37_I2S_1_FS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(73, "GP38_I2S_1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(74, "GP39_I2S_1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(75, "GP40_I2S_2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(76, "GP41_I2S_2_FS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(77, "GP42_I2S_2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(78, "GP43_I2S_2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Family 6: GP SSP (22 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(79, "GP120_SPI_0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(80, "GP121_SPI_0_SS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(81, "GP122_SPI_0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(82, "GP123_SPI_0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(83, "GP102_SPI_1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(84, "GP103_SPI_1_SS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(85, "GP104_SPI_1_SS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(86, "GP105_SPI_1_SS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(87, "GP106_SPI_1_SS3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(88, "GP107_SPI_1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(89, "GP108_SPI_1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(90, "GP109_SPI_2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(91, "GP110_SPI_2_SS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(92, "GP111_SPI_2_SS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(93, "GP112_SPI_2_SS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(94, "GP113_SPI_2_SS3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(95, "GP114_SPI_2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(96, "GP115_SPI_2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(97, "GP116_SPI_3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(98, "GP117_SPI_3_SS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(99, "GP118_SPI_3_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(100, "GP119_SPI_3_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Family 7: I2C (14 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(101, "GP19_I2C_1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(102, "GP20_I2C_1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(103, "GP21_I2C_2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(104, "GP22_I2C_2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(105, "GP17_I2C_3_SCL_HDMI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(106, "GP18_I2C_3_SDA_HDMI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(107, "GP23_I2C_4_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(108, "GP24_I2C_4_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(109, "GP25_I2C_5_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(110, "GP26_I2C_5_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(111, "GP27_I2C_6_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(112, "GP28_I2C_6_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(113, "GP29_I2C_7_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(114, "GP30_I2C_7_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Family 8: UART (12 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(115, "GP124_UART_0_CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(116, "GP125_UART_0_RTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(117, "GP126_UART_0_RX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(118, "GP127_UART_0_TX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(119, "GP128_UART_1_CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(120, "GP129_UART_1_RTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(121, "GP130_UART_1_RX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(122, "GP131_UART_1_TX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(123, "GP132_UART_2_CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(124, "GP133_UART_2_RTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(125, "GP134_UART_2_RX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(126, "GP135_UART_2_TX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Family 9: GPIO South (19 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(127, "GP177"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(128, "GP178"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(129, "GP179"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(130, "GP180"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(131, "GP181"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(132, "GP182_PWM2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(133, "GP183_PWM3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(134, "GP184"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(135, "GP185"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(136, "GP186"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(137, "GP187"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(138, "GP188"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(139, "GP189"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(140, "GP64_FAST_INT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(141, "GP65_FAST_INT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(142, "GP66_FAST_INT2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(143, "GP67_FAST_INT3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(144, "GP12_PWM0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(145, "GP13_PWM1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Family 10: Camera Sideband (12 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(146, "GP0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(147, "GP1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(148, "GP2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(149, "GP3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(150, "GP4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(151, "GP5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(152, "GP6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(153, "GP7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(154, "GP8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(155, "GP9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(156, "GP10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(157, "GP11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Family 11: Clock (22 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(158, "GP137"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(159, "GP138"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(160, "GP139"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(161, "GP140"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(162, "GP141"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(163, "GP142"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(164, "GP16_HDMI_HPD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(165, "GP68_DSI_A_TE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(166, "GP69_DSI_C_TE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(167, "OSC_CLK_CTRL0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(168, "OSC_CLK_CTRL1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(169, "OSC_CLK0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(170, "OSC_CLK1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(171, "OSC_CLK2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(172, "OSC_CLK3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(173, "OSC_CLK4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(174, "RESETOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(175, "PMODE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(176, "PRDY"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(177, "PREQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(178, "GP190"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(179, "GP191"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Family 12: MSIC (15 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(180, "I2C_0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(181, "I2C_0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(182, "IERR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(183, "JTAG_TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(184, "JTAG_TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(185, "JTAG_TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(186, "JTAG_TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(187, "JTAG_TRST"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(188, "PROCHOT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(189, "RTC_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(190, "SVID_ALERT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(191, "SVID_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(192, "SVID_D"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(193, "THERMTRIP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(194, "STANDBY"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Family 13: Keyboard (20 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(195, "GP44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(196, "GP45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(197, "GP46"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(198, "GP47"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(199, "GP48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(200, "GP49"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(201, "GP50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(202, "GP51"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(203, "GP52"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(204, "GP53"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(205, "GP54"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(206, "GP55"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(207, "GP56"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(208, "GP57"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(209, "GP58"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(210, "GP59"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(211, "GP60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(212, "GP61"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(213, "GP62"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(214, "GP63"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Family 14: GPIO North (13 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(215, "GP164"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(216, "GP165"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(217, "GP166"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(218, "GP167"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(219, "GP168_MJTAG_TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(220, "GP169_MJTAG_TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(221, "GP170_MJTAG_TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(222, "GP171_MJTAG_TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(223, "GP172_MJTAG_TRST"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(224, "GP173"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(225, "GP174"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(226, "GP175"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(227, "GP176"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Family 15: PTI (5 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(228, "GP72_PTI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(229, "GP73_PTI_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(230, "GP74_PTI_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(231, "GP75_PTI_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(232, "GP76_PTI_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Family 16: USB3 (0 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Family 17: HSIC (0 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Family 18: Broadcast (0 pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const unsigned int mrfld_sdio_pins[] = { 50, 51, 52, 53, 54, 55, 56 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const unsigned int mrfld_i2s2_pins[] = { 75, 76, 77, 78 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const unsigned int mrfld_spi5_pins[] = { 90, 91, 92, 93, 94, 95, 96 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const unsigned int mrfld_uart0_pins[] = { 115, 116, 117, 118 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const unsigned int mrfld_uart1_pins[] = { 119, 120, 121, 122 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const unsigned int mrfld_uart2_pins[] = { 123, 124, 125, 126 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const unsigned int mrfld_pwm0_pins[] = { 144 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const unsigned int mrfld_pwm1_pins[] = { 145 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const unsigned int mrfld_pwm2_pins[] = { 132 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const unsigned int mrfld_pwm3_pins[] = { 133 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct intel_pingroup mrfld_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PIN_GROUP("sdio_grp", mrfld_sdio_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PIN_GROUP("i2s2_grp", mrfld_i2s2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PIN_GROUP("spi5_grp", mrfld_spi5_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PIN_GROUP("uart0_grp", mrfld_uart0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PIN_GROUP("uart1_grp", mrfld_uart1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PIN_GROUP("uart2_grp", mrfld_uart2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PIN_GROUP("pwm0_grp", mrfld_pwm0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PIN_GROUP("pwm1_grp", mrfld_pwm1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PIN_GROUP("pwm2_grp", mrfld_pwm2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PIN_GROUP("pwm3_grp", mrfld_pwm3_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const char * const mrfld_sdio_groups[] = { "sdio_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const char * const mrfld_i2s2_groups[] = { "i2s2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const char * const mrfld_spi5_groups[] = { "spi5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const char * const mrfld_uart0_groups[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const char * const mrfld_uart1_groups[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const char * const mrfld_uart2_groups[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const char * const mrfld_pwm0_groups[] = { "pwm0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const char * const mrfld_pwm1_groups[] = { "pwm1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const char * const mrfld_pwm2_groups[] = { "pwm2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const char * const mrfld_pwm3_groups[] = { "pwm3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct intel_function mrfld_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) FUNCTION("sdio", mrfld_sdio_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) FUNCTION("i2s2", mrfld_i2s2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) FUNCTION("spi5", mrfld_spi5_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) FUNCTION("uart0", mrfld_uart0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) FUNCTION("uart1", mrfld_uart1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) FUNCTION("uart2", mrfld_uart2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) FUNCTION("pwm0", mrfld_pwm0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) FUNCTION("pwm1", mrfld_pwm1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) FUNCTION("pwm2", mrfld_pwm2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) FUNCTION("pwm3", mrfld_pwm3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct mrfld_family mrfld_families[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MRFLD_FAMILY(1, 0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MRFLD_FAMILY(2, 13, 36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MRFLD_FAMILY(3, 37, 56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MRFLD_FAMILY(4, 57, 64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MRFLD_FAMILY(5, 65, 78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MRFLD_FAMILY(6, 79, 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MRFLD_FAMILY_PROTECTED(7, 101, 114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MRFLD_FAMILY(8, 115, 126),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MRFLD_FAMILY(9, 127, 145),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MRFLD_FAMILY(10, 146, 157),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MRFLD_FAMILY(11, 158, 179),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MRFLD_FAMILY_PROTECTED(12, 180, 194),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MRFLD_FAMILY(13, 195, 214),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MRFLD_FAMILY(14, 215, 227),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MRFLD_FAMILY(15, 228, 232),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * @dev: Pointer to the device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * @lock: Lock to serialize register access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * @pctldesc: Pin controller description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * @pctldev: Pointer to the pin controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * @families: Array of families this pinctrl handles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * @nfamilies: Number of families in the array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * @functions: Array of functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * @nfunctions: Number of functions in the array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * @groups: Array of pin groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * @ngroups: Number of groups in the array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * @pins: Array of pins this pinctrl controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * @npins: Number of pins in the array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct mrfld_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct pinctrl_desc pctldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct pinctrl_dev *pctldev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Pin controller configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) const struct mrfld_family *families;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) size_t nfamilies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) const struct intel_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) size_t nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) const struct intel_pingroup *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) size_t ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) size_t npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define pin_to_bufno(f, p) ((p) - (f)->pin_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) const struct mrfld_family *family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) for (i = 0; i < mp->nfamilies; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) family = &mp->families[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (pin >= family->pin_base &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pin < family->pin_base + family->npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dev_warn(mp->dev, "failed to find family for pin %u\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) const struct mrfld_family *family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) family = mrfld_get_family(mp, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!family)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return !family->protected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) const struct mrfld_family *family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) unsigned int bufno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) family = mrfld_get_family(mp, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!family)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) bufno = pin_to_bufno(family, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return family->regs + BUFCFG_OFFSET + bufno * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int mrfld_read_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) void __iomem *bufcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (!mrfld_buf_available(mp, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) bufcfg = mrfld_get_bufcfg(mp, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) *value = readl(bufcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 bits, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) void __iomem *bufcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) bufcfg = mrfld_get_bufcfg(mp, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) value = readl(bufcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) value &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) value |= bits & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) writel(value, bufcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int mrfld_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return mp->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return mp->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) const unsigned int **pins, unsigned int *npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) *pins = mp->groups[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *npins = mp->groups[group].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 value, mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ret = mrfld_read_bufcfg(mp, pin, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) seq_puts(s, "not available");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) seq_puts(s, "GPIO ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) seq_printf(s, "mode %d ", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) seq_printf(s, "0x%08x", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static const struct pinctrl_ops mrfld_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .get_groups_count = mrfld_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .get_group_name = mrfld_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .get_group_pins = mrfld_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .pin_dbg_show = mrfld_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static int mrfld_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return mp->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return mp->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned int * const ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) *groups = mp->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) *ngroups = mp->functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) const struct intel_pingroup *grp = &mp->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) u32 mask = BUFCFG_PINMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * All pins in the groups needs to be accessible and writable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * before we can enable the mux for this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) for (i = 0; i < grp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (!mrfld_buf_available(mp, grp->pins[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Now enable the mux setting for each pin in the group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) raw_spin_lock_irqsave(&mp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) for (i = 0; i < grp->npins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mrfld_update_bufcfg(mp, grp->pins[i], bits, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) raw_spin_unlock_irqrestore(&mp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 mask = BUFCFG_PINMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!mrfld_buf_available(mp, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) raw_spin_lock_irqsave(&mp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) mrfld_update_bufcfg(mp, pin, bits, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) raw_spin_unlock_irqrestore(&mp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const struct pinmux_ops mrfld_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .get_functions_count = mrfld_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .get_function_name = mrfld_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .get_function_groups = mrfld_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .set_mux = mrfld_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .gpio_request_enable = mrfld_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u32 value, term;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u16 arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ret = mrfld_read_bufcfg(mp, pin, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (value & BUFCFG_Px_EN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) switch (term) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) case BUFCFG_PUPD_VAL_910:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) arg = 910;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case BUFCFG_PUPD_VAL_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) arg = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) case BUFCFG_PUPD_VAL_20K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) arg = 20000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case BUFCFG_PUPD_VAL_50K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) arg = 50000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) switch (term) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) case BUFCFG_PUPD_VAL_910:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) arg = 910;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case BUFCFG_PUPD_VAL_2K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) arg = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case BUFCFG_PUPD_VAL_20K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) arg = 20000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case BUFCFG_PUPD_VAL_50K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) arg = 50000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!(value & BUFCFG_OD_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!(value & BUFCFG_SLEWSEL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) unsigned int param = pinconf_to_config_param(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) unsigned int arg = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u32 bits = 0, mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) bits |= BUFCFG_PU_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Set default strength value in case none is given */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (arg == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) arg = 20000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) case 50000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case 20000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) case 2000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) bits |= BUFCFG_PD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Set default strength value in case none is given */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (arg == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) arg = 20000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) case 50000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) case 20000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case 2000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mask |= BUFCFG_OD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) bits |= BUFCFG_OD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mask |= BUFCFG_SLEWSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) bits |= BUFCFG_SLEWSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) raw_spin_lock_irqsave(&mp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) mrfld_update_bufcfg(mp, pin, bits, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) raw_spin_unlock_irqrestore(&mp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) unsigned long *configs, unsigned int nconfigs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (!mrfld_buf_available(mp, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) for (i = 0; i < nconfigs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) switch (pinconf_to_config_param(configs[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ret = mrfld_config_set_pin(mp, pin, configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int mrfld_config_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) unsigned int group, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ret = mrfld_config_get(pctldev, pins[0], config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int mrfld_config_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) unsigned int group, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = mrfld_config_set(pctldev, pins[i], configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static const struct pinconf_ops mrfld_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .pin_config_get = mrfld_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .pin_config_set = mrfld_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .pin_config_group_get = mrfld_config_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .pin_config_group_set = mrfld_config_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static const struct pinctrl_desc mrfld_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .pctlops = &mrfld_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .pmxops = &mrfld_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .confops = &mrfld_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int mrfld_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct mrfld_family *families;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct mrfld_pinctrl *mp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) size_t nfamilies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) mp = devm_kzalloc(&pdev->dev, sizeof(*mp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (!mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) mp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) raw_spin_lock_init(&mp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * Make a copy of the families which we can use to hold pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * to the registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) nfamilies = ARRAY_SIZE(mrfld_families),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) families = devm_kmemdup(&pdev->dev, mrfld_families,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) sizeof(mrfld_families),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (!families)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* Splice memory resource by chunk per family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) for (i = 0; i < nfamilies; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct mrfld_family *family = &families[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) family->regs = regs + family->barno * MRFLD_FAMILY_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) mp->families = families;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) mp->nfamilies = nfamilies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) mp->functions = mrfld_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) mp->nfunctions = ARRAY_SIZE(mrfld_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) mp->groups = mrfld_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) mp->ngroups = ARRAY_SIZE(mrfld_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) mp->pctldesc = mrfld_pinctrl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) mp->pctldesc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) mp->pctldesc.pins = mrfld_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) mp->pctldev = devm_pinctrl_register(&pdev->dev, &mp->pctldesc, mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (IS_ERR(mp->pctldev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) dev_err(&pdev->dev, "failed to register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return PTR_ERR(mp->pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) platform_set_drvdata(pdev, mp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const struct acpi_device_id mrfld_acpi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) { "INTC1002" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static struct platform_driver mrfld_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .probe = mrfld_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .name = "pinctrl-merrifield",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .acpi_match_table = mrfld_acpi_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int __init mrfld_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return platform_driver_register(&mrfld_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) subsys_initcall(mrfld_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static void __exit mrfld_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) platform_driver_unregister(&mrfld_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) module_exit(mrfld_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) MODULE_ALIAS("platform:pinctrl-merrifield");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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