Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Intel Lewisburg pinctrl/GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "pinctrl-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define LBG_PAD_OWN	0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define LBG_PADCFGLOCK	0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define LBG_HOSTSW_OWN	0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LBG_GPI_IS	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define LBG_GPI_IE	0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LBG_COMMUNITY(b, s, e)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		.barno = (b),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		.padown_offset = LBG_PAD_OWN,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		.padcfglock_offset = LBG_PADCFGLOCK,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		.hostown_offset = LBG_HOSTSW_OWN,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		.is_offset = LBG_GPI_IS,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		.ie_offset = LBG_GPI_IE,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		.gpp_size = 24,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		.pin_base = (s),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		.npins = ((e) - (s) + 1),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* Lewisburg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static const struct pinctrl_pin_desc lbg_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	/* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	PINCTRL_PIN(0, "RCINB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	PINCTRL_PIN(1, "LAD_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	PINCTRL_PIN(2, "LAD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	PINCTRL_PIN(3, "LAD_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	PINCTRL_PIN(4, "LAD_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	PINCTRL_PIN(5, "LFRAMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	PINCTRL_PIN(6, "SERIRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	PINCTRL_PIN(7, "PIRQAB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	PINCTRL_PIN(8, "CLKRUNB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	PINCTRL_PIN(9, "CLKOUT_LPC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	PINCTRL_PIN(10, "CLKOUT_LPC_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	PINCTRL_PIN(11, "PMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	PINCTRL_PIN(12, "BM_BUSYB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	PINCTRL_PIN(14, "ESPI_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	PINCTRL_PIN(15, "SUSACKB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	PINCTRL_PIN(16, "CLKOUT_LPC_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	PINCTRL_PIN(17, "GPP_A_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	PINCTRL_PIN(18, "GPP_A_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	PINCTRL_PIN(19, "GPP_A_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	PINCTRL_PIN(20, "GPP_A_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	PINCTRL_PIN(21, "GPP_A_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	PINCTRL_PIN(22, "GPP_A_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	PINCTRL_PIN(23, "GPP_A_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	/* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	PINCTRL_PIN(24, "CORE_VID_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	PINCTRL_PIN(25, "CORE_VID_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	PINCTRL_PIN(26, "VRALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	PINCTRL_PIN(27, "CPU_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	PINCTRL_PIN(28, "CPU_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	PINCTRL_PIN(29, "SRCCLKREQB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	PINCTRL_PIN(30, "SRCCLKREQB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	PINCTRL_PIN(31, "SRCCLKREQB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	PINCTRL_PIN(32, "SRCCLKREQB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	PINCTRL_PIN(33, "SRCCLKREQB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	PINCTRL_PIN(34, "SRCCLKREQB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	PINCTRL_PIN(35, "GPP_B_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	PINCTRL_PIN(36, "SLP_S0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	PINCTRL_PIN(37, "PLTRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	PINCTRL_PIN(38, "SPKR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	PINCTRL_PIN(39, "GPP_B_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	PINCTRL_PIN(40, "GPP_B_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	PINCTRL_PIN(41, "GPP_B_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	PINCTRL_PIN(42, "GPP_B_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	PINCTRL_PIN(43, "GPP_B_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	PINCTRL_PIN(44, "GPP_B_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	PINCTRL_PIN(45, "GPP_B_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	PINCTRL_PIN(46, "GPP_B_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	PINCTRL_PIN(47, "SML1ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	PINCTRL_PIN(48, "SATAXPCIE_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	PINCTRL_PIN(49, "SATAXPCIE_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	PINCTRL_PIN(50, "SATAXPCIE_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	PINCTRL_PIN(51, "SATAXPCIE_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	PINCTRL_PIN(52, "SATAXPCIE_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	PINCTRL_PIN(53, "SATA_DEVSLP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	PINCTRL_PIN(54, "SATA_DEVSLP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	PINCTRL_PIN(55, "SATA_DEVSLP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	PINCTRL_PIN(56, "SATA_DEVSLP_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	PINCTRL_PIN(57, "SATA_DEVSLP_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	PINCTRL_PIN(58, "SATA_SCLOCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	PINCTRL_PIN(59, "SATA_SLOAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	PINCTRL_PIN(60, "SATA_SDATAOUT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	PINCTRL_PIN(61, "SATA_SDATAOUT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	PINCTRL_PIN(62, "SSATA_LEDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	PINCTRL_PIN(63, "USB2_OCB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	PINCTRL_PIN(64, "USB2_OCB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	PINCTRL_PIN(65, "USB2_OCB_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	PINCTRL_PIN(66, "USB2_OCB_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	PINCTRL_PIN(67, "GBE_SMBUS_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	PINCTRL_PIN(68, "GBE_SMBDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	PINCTRL_PIN(69, "GBE_SMBALRTN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	PINCTRL_PIN(70, "SSATA_SCLOCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	PINCTRL_PIN(71, "SSATA_SLOAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	PINCTRL_PIN(72, "SMBCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	PINCTRL_PIN(73, "SMBDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	PINCTRL_PIN(74, "SMBALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	PINCTRL_PIN(75, "SML0CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	PINCTRL_PIN(76, "SML0DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	PINCTRL_PIN(77, "SML0ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	PINCTRL_PIN(78, "SML1CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	PINCTRL_PIN(79, "SML1DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	PINCTRL_PIN(80, "GPP_C_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	PINCTRL_PIN(81, "GPP_C_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	PINCTRL_PIN(82, "GPP_C_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	PINCTRL_PIN(83, "GPP_C_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	PINCTRL_PIN(84, "GPP_C_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	PINCTRL_PIN(85, "GPP_C_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	PINCTRL_PIN(86, "GPP_C_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	PINCTRL_PIN(87, "GPP_C_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	PINCTRL_PIN(88, "GPP_C_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	PINCTRL_PIN(89, "GPP_C_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	PINCTRL_PIN(90, "GPP_C_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	PINCTRL_PIN(91, "GPP_C_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	PINCTRL_PIN(92, "GPP_C_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	PINCTRL_PIN(93, "GPP_C_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	PINCTRL_PIN(94, "GPP_C_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	PINCTRL_PIN(95, "GPP_C_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	PINCTRL_PIN(96, "GPP_D_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	PINCTRL_PIN(97, "GPP_D_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	PINCTRL_PIN(98, "GPP_D_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	PINCTRL_PIN(99, "GPP_D_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	PINCTRL_PIN(100, "GPP_D_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	PINCTRL_PIN(101, "SSP0_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	PINCTRL_PIN(102, "SSP0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	PINCTRL_PIN(103, "SSP0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	PINCTRL_PIN(104, "SSP0_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	PINCTRL_PIN(105, "SSATA_DEVSLP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	PINCTRL_PIN(106, "SSATA_DEVSLP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	PINCTRL_PIN(107, "SSATA_DEVSLP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	PINCTRL_PIN(108, "SSATA_SDATAOUT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	PINCTRL_PIN(109, "SML0BCLK_SML0BCLKIE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	PINCTRL_PIN(110, "SML0BDATA_SML0BDATAIE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	PINCTRL_PIN(111, "SSATA_SDATAOUT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	PINCTRL_PIN(112, "SML0BALERTB_SML0BALERTBIE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	PINCTRL_PIN(113, "DMIC_CLK_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	PINCTRL_PIN(114, "DMIC_DATA_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	PINCTRL_PIN(115, "DMIC_CLK_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	PINCTRL_PIN(116, "DMIC_DATA_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	PINCTRL_PIN(117, "IE_UART_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	PINCTRL_PIN(118, "IE_UART_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	PINCTRL_PIN(119, "GPP_D_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	PINCTRL_PIN(120, "SATAXPCIE_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	PINCTRL_PIN(121, "SATAXPCIE_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	PINCTRL_PIN(122, "SATAXPCIE_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	PINCTRL_PIN(123, "CPU_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	PINCTRL_PIN(124, "SATA_DEVSLP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	PINCTRL_PIN(125, "SATA_DEVSLP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	PINCTRL_PIN(126, "SATA_DEVSLP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	PINCTRL_PIN(127, "CPU_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	PINCTRL_PIN(128, "SATA_LEDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	PINCTRL_PIN(129, "USB2_OCB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	PINCTRL_PIN(130, "USB2_OCB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	PINCTRL_PIN(131, "USB2_OCB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	PINCTRL_PIN(132, "USB2_OCB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* GPP_I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	PINCTRL_PIN(133, "GBE_TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	PINCTRL_PIN(134, "GBE_TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	PINCTRL_PIN(135, "GBE_TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	PINCTRL_PIN(136, "GBE_TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	PINCTRL_PIN(137, "DO_RESET_INB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	PINCTRL_PIN(138, "DO_RESET_OUTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	PINCTRL_PIN(139, "RESET_DONE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	PINCTRL_PIN(140, "GBE_TRST_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	PINCTRL_PIN(141, "GBE_PCI_DIS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	PINCTRL_PIN(142, "GBE_LAN_DIS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	PINCTRL_PIN(143, "GPP_I_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* GPP_J */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	PINCTRL_PIN(144, "GBE_LED_0_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	PINCTRL_PIN(145, "GBE_LED_0_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	PINCTRL_PIN(146, "GBE_LED_1_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	PINCTRL_PIN(147, "GBE_LED_1_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	PINCTRL_PIN(148, "GBE_LED_2_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	PINCTRL_PIN(149, "GBE_LED_2_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	PINCTRL_PIN(150, "GBE_LED_3_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	PINCTRL_PIN(151, "GBE_LED_3_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	PINCTRL_PIN(152, "GBE_SCL_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	PINCTRL_PIN(153, "GBE_SDA_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	PINCTRL_PIN(154, "GBE_SCL_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	PINCTRL_PIN(155, "GBE_SDA_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	PINCTRL_PIN(156, "GBE_SCL_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	PINCTRL_PIN(157, "GBE_SDA_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	PINCTRL_PIN(158, "GBE_SCL_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	PINCTRL_PIN(159, "GBE_SDA_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	PINCTRL_PIN(160, "GBE_SDP_0_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	PINCTRL_PIN(161, "GBE_SDP_0_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	PINCTRL_PIN(162, "GBE_SDP_1_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	PINCTRL_PIN(163, "GBE_SDP_1_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	PINCTRL_PIN(164, "GBE_SDP_2_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	PINCTRL_PIN(165, "GBE_SDP_2_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	PINCTRL_PIN(166, "GBE_SDP_3_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	PINCTRL_PIN(167, "GBE_SDP_3_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	/* GPP_K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	PINCTRL_PIN(168, "GBE_RMIICLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	PINCTRL_PIN(169, "GBE_RMII_RXD_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	PINCTRL_PIN(170, "GBE_RMII_RXD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	PINCTRL_PIN(171, "GBE_RMII_CRS_DV"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	PINCTRL_PIN(172, "GBE_RMII_TX_EN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	PINCTRL_PIN(173, "GBE_RMII_TXD_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	PINCTRL_PIN(174, "GBE_RMII_TXD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	PINCTRL_PIN(175, "GBE_RMII_RX_ER"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	PINCTRL_PIN(176, "GBE_RMII_ARBIN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	PINCTRL_PIN(177, "GBE_RMII_ARB_OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	PINCTRL_PIN(178, "PE_RST_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	/* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	PINCTRL_PIN(179, "FAN_TACH_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	PINCTRL_PIN(180, "FAN_TACH_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	PINCTRL_PIN(181, "FAN_TACH_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	PINCTRL_PIN(182, "FAN_TACH_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	PINCTRL_PIN(183, "FAN_TACH_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	PINCTRL_PIN(184, "FAN_TACH_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	PINCTRL_PIN(185, "FAN_TACH_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	PINCTRL_PIN(186, "FAN_TACH_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	PINCTRL_PIN(187, "FAN_PWM_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	PINCTRL_PIN(188, "FAN_PWM_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	PINCTRL_PIN(189, "FAN_PWM_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	PINCTRL_PIN(190, "FAN_PWM_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	PINCTRL_PIN(191, "GSXDOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	PINCTRL_PIN(192, "GSXSLOAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	PINCTRL_PIN(193, "GSXDIN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	PINCTRL_PIN(194, "GSXSRESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	PINCTRL_PIN(195, "GSXCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	PINCTRL_PIN(196, "ADR_COMPLETE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	PINCTRL_PIN(197, "NMIB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	PINCTRL_PIN(198, "SMIB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	PINCTRL_PIN(199, "SSATA_DEVSLP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	PINCTRL_PIN(200, "SSATA_DEVSLP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	PINCTRL_PIN(201, "SSATA_DEVSLP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	PINCTRL_PIN(202, "SSATAXPCIE0_SSATAGP0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	PINCTRL_PIN(203, "SRCCLKREQB_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	PINCTRL_PIN(204, "SRCCLKREQB_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	PINCTRL_PIN(205, "SRCCLKREQB_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	PINCTRL_PIN(206, "SRCCLKREQB_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	PINCTRL_PIN(207, "SRCCLKREQB_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	PINCTRL_PIN(208, "SRCCLKREQB_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	PINCTRL_PIN(209, "SRCCLKREQB_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	PINCTRL_PIN(210, "SRCCLKREQB_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	PINCTRL_PIN(211, "SRCCLKREQB_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	PINCTRL_PIN(212, "SRCCLKREQB_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	PINCTRL_PIN(213, "SML2CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	PINCTRL_PIN(214, "SML2DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	PINCTRL_PIN(215, "SML2ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	PINCTRL_PIN(216, "SML3CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	PINCTRL_PIN(217, "SML3DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	PINCTRL_PIN(218, "SML3ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	PINCTRL_PIN(219, "SML4CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	PINCTRL_PIN(220, "SML4DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	PINCTRL_PIN(221, "SML4ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	PINCTRL_PIN(222, "SSATAXPCIE1_SSATAGP1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	PINCTRL_PIN(223, "SSATAXPCIE2_SSATAGP2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	PINCTRL_PIN(224, "SSATAXPCIE3_SSATAGP3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	PINCTRL_PIN(225, "SSATAXPCIE4_SSATAGP4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	PINCTRL_PIN(226, "SSATAXPCIE5_SSATAGP5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	/* GPP_L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	PINCTRL_PIN(227, "GPP_L_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	PINCTRL_PIN(228, "EC_CSME_INTR_OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	PINCTRL_PIN(229, "VISA2CH0_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	PINCTRL_PIN(230, "VISA2CH0_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	PINCTRL_PIN(231, "VISA2CH0_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	PINCTRL_PIN(232, "VISA2CH0_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	PINCTRL_PIN(233, "VISA2CH0_D4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	PINCTRL_PIN(234, "VISA2CH0_D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	PINCTRL_PIN(235, "VISA2CH0_D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	PINCTRL_PIN(236, "VISA2CH0_D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	PINCTRL_PIN(237, "VISA2CH0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	PINCTRL_PIN(238, "VISA2CH1_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	PINCTRL_PIN(239, "VISA2CH1_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	PINCTRL_PIN(240, "VISA2CH1_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	PINCTRL_PIN(241, "VISA2CH1_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	PINCTRL_PIN(242, "VISA2CH1_D4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	PINCTRL_PIN(243, "VISA2CH1_D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	PINCTRL_PIN(244, "VISA2CH1_D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	PINCTRL_PIN(245, "VISA2CH1_D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	PINCTRL_PIN(246, "VISA2CH1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct intel_community lbg_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	LBG_COMMUNITY(0, 0, 71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	LBG_COMMUNITY(1, 72, 132),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	LBG_COMMUNITY(3, 133, 143),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	LBG_COMMUNITY(4, 144, 178),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	LBG_COMMUNITY(5, 179, 246),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct intel_pinctrl_soc_data lbg_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.pins = lbg_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.npins = ARRAY_SIZE(lbg_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.communities = lbg_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.ncommunities = ARRAY_SIZE(lbg_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static INTEL_PINCTRL_PM_OPS(lbg_pinctrl_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct acpi_device_id lbg_pinctrl_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	{ "INT3536", (kernel_ulong_t)&lbg_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MODULE_DEVICE_TABLE(acpi, lbg_pinctrl_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static struct platform_driver lbg_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.probe = intel_pinctrl_probe_by_hid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		.name = "lewisburg-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		.acpi_match_table = lbg_pinctrl_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		.pm = &lbg_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) module_platform_driver(lbg_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MODULE_DESCRIPTION("Intel Lewisburg pinctrl/GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MODULE_LICENSE("GPL v2");