Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Intel Jasper Lake PCH pinctrl/GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2020, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "pinctrl-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define JSL_PAD_OWN	0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define JSL_PADCFGLOCK	0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define JSL_HOSTSW_OWN	0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define JSL_GPI_IS	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define JSL_GPI_IE	0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define JSL_GPP(r, s, e, g)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		.reg_num = (r),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		.base = (s),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		.size = ((e) - (s) + 1),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		.gpio_base = (g),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define JSL_COMMUNITY(b, s, e, g)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		.barno = (b),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		.padown_offset = JSL_PAD_OWN,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		.padcfglock_offset = JSL_PADCFGLOCK,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		.hostown_offset = JSL_HOSTSW_OWN,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.is_offset = JSL_GPI_IS,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.ie_offset = JSL_GPI_IE,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.pin_base = (s),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.npins = ((e) - (s) + 1),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.gpps = (g),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.ngpps = ARRAY_SIZE(g),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* Jasper Lake */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static const struct pinctrl_pin_desc jsl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	/* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	PINCTRL_PIN(0, "CNV_BRI_DT_UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	PINCTRL_PIN(1, "CNV_BRI_RSP_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	PINCTRL_PIN(2, "EMMC_HIP_MON"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	PINCTRL_PIN(3, "CNV_RGI_RSP_UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	PINCTRL_PIN(4, "CNV_RF_RESET_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	PINCTRL_PIN(5, "MODEM_CLKREQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	PINCTRL_PIN(6, "CNV_PA_BLANKING"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	PINCTRL_PIN(7, "EMMC_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	PINCTRL_PIN(8, "EMMC_DATA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	PINCTRL_PIN(9, "EMMC_DATA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	PINCTRL_PIN(10, "EMMC_DATA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	PINCTRL_PIN(11, "EMMC_DATA3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	PINCTRL_PIN(12, "EMMC_DATA4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	PINCTRL_PIN(13, "EMMC_DATA5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	PINCTRL_PIN(14, "EMMC_DATA6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	PINCTRL_PIN(15, "EMMC_DATA7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	PINCTRL_PIN(16, "EMMC_RCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	PINCTRL_PIN(17, "EMMC_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	PINCTRL_PIN(18, "EMMC_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	PINCTRL_PIN(19, "A4WP_PRESENT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	/* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	PINCTRL_PIN(20, "SPI0_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	PINCTRL_PIN(21, "SPI0_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	PINCTRL_PIN(22, "SPI0_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	PINCTRL_PIN(23, "SPI0_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	PINCTRL_PIN(24, "SPI0_TPM_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	PINCTRL_PIN(25, "SPI0_FLASH_0_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	PINCTRL_PIN(26, "SPI0_FLASH_1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	PINCTRL_PIN(27, "SPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	PINCTRL_PIN(28, "SPI0_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	PINCTRL_PIN(29, "CORE_VID_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	PINCTRL_PIN(30, "CORE_VID_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	PINCTRL_PIN(31, "VRALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	PINCTRL_PIN(32, "CPU_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	PINCTRL_PIN(33, "CPU_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	PINCTRL_PIN(34, "SRCCLKREQB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	PINCTRL_PIN(35, "SRCCLKREQB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	PINCTRL_PIN(36, "SRCCLKREQB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	PINCTRL_PIN(37, "SRCCLKREQB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	PINCTRL_PIN(38, "SRCCLKREQB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	PINCTRL_PIN(39, "SRCCLKREQB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	PINCTRL_PIN(40, "PMCALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	PINCTRL_PIN(41, "SLP_S0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	PINCTRL_PIN(42, "PLTRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	PINCTRL_PIN(43, "SPKR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	PINCTRL_PIN(44, "GSPI0_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	PINCTRL_PIN(45, "GSPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	PINCTRL_PIN(46, "GSPI0_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	PINCTRL_PIN(47, "GSPI0_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	PINCTRL_PIN(48, "GSPI1_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	PINCTRL_PIN(49, "GSPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	PINCTRL_PIN(50, "GSPI1_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	PINCTRL_PIN(51, "GSPI1_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	PINCTRL_PIN(52, "DDSP_HPD_A"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	PINCTRL_PIN(53, "GSPI0_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	PINCTRL_PIN(54, "GSPI1_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	/* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	PINCTRL_PIN(55, "ESPI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	PINCTRL_PIN(56, "ESPI_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	PINCTRL_PIN(57, "ESPI_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	PINCTRL_PIN(58, "ESPI_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	PINCTRL_PIN(59, "ESPI_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	PINCTRL_PIN(60, "ESPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	PINCTRL_PIN(61, "ESPI_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	PINCTRL_PIN(62, "SMBCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	PINCTRL_PIN(63, "SMBDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	PINCTRL_PIN(64, "SMBALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	PINCTRL_PIN(65, "CPU_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	PINCTRL_PIN(66, "CPU_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	PINCTRL_PIN(67, "USB2_OCB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	PINCTRL_PIN(68, "USB2_OCB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	PINCTRL_PIN(69, "USB2_OCB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	PINCTRL_PIN(70, "DDSP_HPD_A_TIME_SYNC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	PINCTRL_PIN(71, "DDSP_HPD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	PINCTRL_PIN(72, "DDSP_HPD_C"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	PINCTRL_PIN(73, "USB2_OCB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	PINCTRL_PIN(74, "PCHHOTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	PINCTRL_PIN(75, "ESPI_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/* GPP_S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	PINCTRL_PIN(76, "SNDW1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	PINCTRL_PIN(77, "SNDW1_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	PINCTRL_PIN(78, "SNDW2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	PINCTRL_PIN(79, "SNDW2_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	PINCTRL_PIN(80, "SNDW1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	PINCTRL_PIN(81, "SNDW1_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	PINCTRL_PIN(82, "SNDW4_CLK_DMIC_CLK_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	PINCTRL_PIN(83, "SNDW4_DATA_DMIC_DATA_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/* GPP_R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	PINCTRL_PIN(84, "HDA_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	PINCTRL_PIN(85, "HDA_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	PINCTRL_PIN(86, "HDA_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	PINCTRL_PIN(87, "HDA_SDI_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	PINCTRL_PIN(88, "HDA_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	PINCTRL_PIN(89, "HDA_SDI_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	PINCTRL_PIN(90, "I2S1_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	PINCTRL_PIN(91, "I2S1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	PINCTRL_PIN(92, "GPPC_H_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	PINCTRL_PIN(93, "SD_PWR_EN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	PINCTRL_PIN(94, "MODEM_CLKREQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	PINCTRL_PIN(95, "SX_EXIT_HOLDOFFB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	PINCTRL_PIN(96, "I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	PINCTRL_PIN(97, "I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	PINCTRL_PIN(98, "I2C3_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	PINCTRL_PIN(99, "I2C3_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	PINCTRL_PIN(100, "I2C4_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	PINCTRL_PIN(101, "I2C4_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	PINCTRL_PIN(102, "CPU_VCCIO_PWR_GATEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	PINCTRL_PIN(103, "I2S2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	PINCTRL_PIN(104, "I2S2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	PINCTRL_PIN(105, "I2S2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	PINCTRL_PIN(106, "I2S2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	PINCTRL_PIN(107, "I2S1_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	PINCTRL_PIN(108, "GPPC_H_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	PINCTRL_PIN(109, "GPPC_H_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	PINCTRL_PIN(110, "GPPC_H_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	PINCTRL_PIN(111, "GPPC_H_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	PINCTRL_PIN(112, "GPPC_H_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	PINCTRL_PIN(113, "GPPC_H_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	PINCTRL_PIN(114, "GPPC_H_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	PINCTRL_PIN(115, "GPPC_H_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	PINCTRL_PIN(116, "SPI1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	PINCTRL_PIN(117, "SPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	PINCTRL_PIN(118, "SPI1_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	PINCTRL_PIN(119, "SPI1_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	PINCTRL_PIN(120, "ISH_I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	PINCTRL_PIN(121, "ISH_I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	PINCTRL_PIN(122, "ISH_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	PINCTRL_PIN(123, "ISH_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	PINCTRL_PIN(124, "ISH_SPI_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	PINCTRL_PIN(125, "ISH_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	PINCTRL_PIN(126, "ISH_SPI_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	PINCTRL_PIN(127, "ISH_SPI_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	PINCTRL_PIN(128, "ISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	PINCTRL_PIN(129, "ISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	PINCTRL_PIN(130, "ISH_UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	PINCTRL_PIN(131, "ISH_UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	PINCTRL_PIN(132, "SPI1_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	PINCTRL_PIN(133, "SPI1_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	PINCTRL_PIN(134, "I2S_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	PINCTRL_PIN(135, "CNV_MFUART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	PINCTRL_PIN(136, "CNV_MFUART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	PINCTRL_PIN(137, "CNV_PA_BLANKING"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	PINCTRL_PIN(138, "I2C5_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	PINCTRL_PIN(139, "I2C5_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	PINCTRL_PIN(140, "GSPI2_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	PINCTRL_PIN(141, "SPI1_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* vGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	PINCTRL_PIN(142, "CNV_BTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	PINCTRL_PIN(143, "CNV_WCEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	PINCTRL_PIN(144, "CNV_BT_HOST_WAKEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	PINCTRL_PIN(145, "CNV_BT_IF_SELECT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	PINCTRL_PIN(146, "vCNV_BT_UART_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	PINCTRL_PIN(147, "vCNV_BT_UART_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	PINCTRL_PIN(148, "vCNV_BT_UART_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	PINCTRL_PIN(149, "vCNV_BT_UART_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	PINCTRL_PIN(150, "vCNV_MFUART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	PINCTRL_PIN(151, "vCNV_MFUART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	PINCTRL_PIN(152, "vCNV_MFUART1_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	PINCTRL_PIN(153, "vCNV_MFUART1_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	PINCTRL_PIN(154, "vUART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	PINCTRL_PIN(155, "vUART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	PINCTRL_PIN(156, "vUART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	PINCTRL_PIN(157, "vUART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	PINCTRL_PIN(158, "vISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	PINCTRL_PIN(159, "vISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	PINCTRL_PIN(160, "vISH_UART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	PINCTRL_PIN(161, "vISH_UART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	PINCTRL_PIN(162, "vCNV_BT_I2S_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	PINCTRL_PIN(163, "vCNV_BT_I2S_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	PINCTRL_PIN(164, "vCNV_BT_I2S_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	PINCTRL_PIN(165, "vCNV_BT_I2S_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	PINCTRL_PIN(166, "vI2S2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	PINCTRL_PIN(167, "vI2S2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	PINCTRL_PIN(168, "vI2S2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	PINCTRL_PIN(169, "vI2S2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	PINCTRL_PIN(170, "vSD3_CD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	/* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	PINCTRL_PIN(171, "GPPC_C_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	PINCTRL_PIN(172, "GPPC_C_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	PINCTRL_PIN(173, "GPPC_C_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	PINCTRL_PIN(174, "GPPC_C_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	PINCTRL_PIN(175, "GPPC_C_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	PINCTRL_PIN(176, "GPPC_C_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	PINCTRL_PIN(177, "SUSWARNB_SUSPWRDNACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	PINCTRL_PIN(178, "SUSACKB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	PINCTRL_PIN(179, "UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	PINCTRL_PIN(180, "UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	PINCTRL_PIN(181, "UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	PINCTRL_PIN(182, "UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	PINCTRL_PIN(183, "UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	PINCTRL_PIN(184, "UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	PINCTRL_PIN(185, "UART1_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	PINCTRL_PIN(186, "UART1_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	PINCTRL_PIN(187, "I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	PINCTRL_PIN(188, "I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	PINCTRL_PIN(189, "I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	PINCTRL_PIN(190, "I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	PINCTRL_PIN(191, "UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	PINCTRL_PIN(192, "UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	PINCTRL_PIN(193, "UART2_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	PINCTRL_PIN(194, "UART2_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* HVCMOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	PINCTRL_PIN(195, "L_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	PINCTRL_PIN(196, "L_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	PINCTRL_PIN(197, "L_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	PINCTRL_PIN(198, "SYS_PWROK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	PINCTRL_PIN(199, "SYS_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	PINCTRL_PIN(200, "MLK_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	PINCTRL_PIN(201, "ISH_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	PINCTRL_PIN(202, "ISH_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	PINCTRL_PIN(203, "IMGCLKOUT_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	PINCTRL_PIN(204, "ISH_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	PINCTRL_PIN(205, "IMGCLKOUT_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	PINCTRL_PIN(206, "SATA_LEDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	PINCTRL_PIN(207, "IMGCLKOUT_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	PINCTRL_PIN(208, "ISH_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	PINCTRL_PIN(209, "ISH_GP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	PINCTRL_PIN(210, "ISH_GP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	PINCTRL_PIN(211, "ISH_GP_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	PINCTRL_PIN(212, "ISH_GP_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	PINCTRL_PIN(213, "IMGCLKOUT_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	PINCTRL_PIN(214, "DDPA_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	PINCTRL_PIN(215, "DDPA_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	PINCTRL_PIN(216, "DDPB_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	PINCTRL_PIN(217, "DDPB_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	PINCTRL_PIN(218, "DDPC_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	PINCTRL_PIN(219, "DDPC_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	PINCTRL_PIN(220, "IMGCLKOUT_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	PINCTRL_PIN(221, "CNV_BRI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	PINCTRL_PIN(222, "CNV_BRI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	PINCTRL_PIN(223, "CNV_RGI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	PINCTRL_PIN(224, "CNV_RGI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	PINCTRL_PIN(225, "SD3_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	PINCTRL_PIN(226, "SD3_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	PINCTRL_PIN(227, "SD3_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	PINCTRL_PIN(228, "SD3_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	PINCTRL_PIN(229, "SD3_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	PINCTRL_PIN(230, "SD3_CDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	PINCTRL_PIN(231, "SD3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	PINCTRL_PIN(232, "SD3_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct intel_padgroup jsl_community0_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	JSL_GPP(0, 0, 19, 320),				/* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	JSL_GPP(1, 20, 28, INTEL_GPIO_BASE_NOMAP),	/* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	JSL_GPP(2, 29, 54, 32),				/* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	JSL_GPP(3, 55, 75, 64),				/* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	JSL_GPP(4, 76, 83, 96),				/* GPP_S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	JSL_GPP(5, 84, 91, 128),			/* GPP_R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct intel_padgroup jsl_community1_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	JSL_GPP(0, 92, 115, 160),			/* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	JSL_GPP(1, 116, 141, 192),			/* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	JSL_GPP(2, 142, 170, 224),			/* vGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	JSL_GPP(3, 171, 194, 256),			/* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct intel_padgroup jsl_community4_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	JSL_GPP(0, 195, 200, INTEL_GPIO_BASE_NOMAP),	/* HVCMOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	JSL_GPP(1, 201, 224, 288),			/* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const struct intel_padgroup jsl_community5_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	JSL_GPP(0, 225, 232, INTEL_GPIO_BASE_ZERO),	/* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct intel_community jsl_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	JSL_COMMUNITY(0, 0, 91, jsl_community0_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	JSL_COMMUNITY(1, 92, 194, jsl_community1_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	JSL_COMMUNITY(2, 195, 224, jsl_community4_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	JSL_COMMUNITY(3, 225, 232, jsl_community5_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct intel_pinctrl_soc_data jsl_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.pins = jsl_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.npins = ARRAY_SIZE(jsl_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.communities = jsl_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.ncommunities = ARRAY_SIZE(jsl_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const struct acpi_device_id jsl_pinctrl_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	{ "INT34C8", (kernel_ulong_t)&jsl_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MODULE_DEVICE_TABLE(acpi, jsl_pinctrl_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static INTEL_PINCTRL_PM_OPS(jsl_pinctrl_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct platform_driver jsl_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.probe = intel_pinctrl_probe_by_hid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.name = "jasperlake-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.acpi_match_table = jsl_pinctrl_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.pm = &jsl_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) module_platform_driver(jsl_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_DESCRIPTION("Intel Jasper Lake PCH pinctrl/GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_LICENSE("GPL v2");