^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Ice Lake PCH pinctrl/GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ICL_PAD_OWN 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ICL_PADCFGLOCK 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ICL_HOSTSW_OWN 0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ICL_GPI_IS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ICL_GPI_IE 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ICL_GPP(r, s, e, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .reg_num = (r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .size = ((e) - (s) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .gpio_base = (g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ICL_COMMUNITY(b, s, e, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .barno = (b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .padown_offset = ICL_PAD_OWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .padcfglock_offset = ICL_PADCFGLOCK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .hostown_offset = ICL_HOSTSW_OWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .is_offset = ICL_GPI_IS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .ie_offset = ICL_GPI_IE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .pin_base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .npins = ((e) - (s) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .gpps = (g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .ngpps = ARRAY_SIZE(g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Ice Lake-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct pinctrl_pin_desc icllp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PINCTRL_PIN(0, "SD3_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PINCTRL_PIN(1, "SD3_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PINCTRL_PIN(2, "SD3_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PINCTRL_PIN(3, "SD3_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PINCTRL_PIN(4, "SD3_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINCTRL_PIN(5, "SD3_CDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PINCTRL_PIN(6, "SD3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINCTRL_PIN(7, "SD3_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN(8, "CORE_VID_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN(9, "CORE_VID_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN(10, "VRALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN(11, "CPU_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN(12, "CPU_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN(13, "ISH_I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINCTRL_PIN(14, "ISH_I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN(15, "ISH_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN(16, "ISH_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN(17, "I2C5_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN(18, "I2C5_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN(19, "PMCALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(20, "SLP_S0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINCTRL_PIN(21, "PLTRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(22, "SPKR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(23, "GSPI0_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINCTRL_PIN(24, "GSPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(25, "GSPI0_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINCTRL_PIN(26, "GSPI0_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(27, "GSPI1_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PINCTRL_PIN(28, "GSPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINCTRL_PIN(29, "GSPI1_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINCTRL_PIN(30, "GSPI1_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINCTRL_PIN(31, "SML1ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(32, "GSPI0_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PINCTRL_PIN(33, "GSPI1_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(34, "ESPI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(35, "ESPI_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(36, "ESPI_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINCTRL_PIN(37, "ESPI_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(38, "ESPI_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(39, "ESPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(40, "ESPI_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(41, "I2S2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(42, "I2S2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(43, "I2S2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(44, "I2S2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(45, "SATA_DEVSLP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(46, "SATAXPCIE_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(47, "SATAXPCIE_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(48, "USB2_OCB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(49, "USB2_OCB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(50, "USB2_OCB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(51, "DDSP_HPD_C"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(52, "DDSP_HPD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(53, "DDSP_HPD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(54, "DDSP_HPD_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(55, "I2S5_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(56, "I2S5_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(57, "I2S1_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(58, "ESPI_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(59, "SD_1P8_SEL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(60, "SD_PWR_EN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(61, "GPPC_H_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(62, "SX_EXIT_HOLDOFFB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(63, "I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(64, "I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(65, "I2C3_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(66, "I2C3_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(67, "I2C4_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(68, "I2C4_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(69, "SRCCLKREQB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(70, "SRCCLKREQB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(71, "M2_SKT2_CFG_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(72, "M2_SKT2_CFG_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(73, "M2_SKT2_CFG_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(74, "M2_SKT2_CFG_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(75, "DDPB_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(76, "DDPB_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(77, "CPU_VCCIO_PWR_GATEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(78, "TIME_SYNC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(79, "IMGCLKOUT_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(80, "IMGCLKOUT_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(81, "IMGCLKOUT_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(82, "IMGCLKOUT_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(83, "ISH_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(84, "ISH_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(85, "ISH_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(86, "ISH_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(87, "IMGCLKOUT_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(88, "SRCCLKREQB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(89, "SRCCLKREQB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(90, "SRCCLKREQB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(91, "SRCCLKREQB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(92, "ISH_SPI_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(93, "ISH_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(94, "ISH_SPI_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(95, "ISH_SPI_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(96, "ISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(97, "ISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(98, "ISH_UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(99, "ISH_UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(100, "ISH_GP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(101, "ISH_GP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(102, "I2S_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(103, "GSPI2_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(104, "CNV_BRI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(105, "CNV_BRI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(106, "CNV_RGI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(107, "CNV_RGI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(108, "CNV_RF_RESET_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(109, "EMMC_HIP_MON"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(110, "CNV_PA_BLANKING"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(111, "EMMC_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(112, "EMMC_DATA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(113, "EMMC_DATA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(114, "EMMC_DATA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(115, "EMMC_DATA3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(116, "EMMC_DATA4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(117, "EMMC_DATA5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(118, "EMMC_DATA6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(119, "EMMC_DATA7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(120, "EMMC_RCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(121, "EMMC_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(122, "EMMC_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(123, "A4WP_PRESENT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* vGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(124, "CNV_BTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(125, "CNV_WCEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(126, "CNV_BT_HOST_WAKEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(127, "CNV_BT_IF_SELECT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(128, "vCNV_BT_UART_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(129, "vCNV_BT_UART_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(130, "vCNV_BT_UART_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(131, "vCNV_BT_UART_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(132, "vCNV_MFUART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(133, "vCNV_MFUART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(134, "vCNV_MFUART1_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(135, "vCNV_MFUART1_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(136, "vUART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(137, "vUART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(138, "vUART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(139, "vUART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(140, "vISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(141, "vISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(142, "vISH_UART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(143, "vISH_UART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(144, "vCNV_BT_I2S_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(145, "vCNV_BT_I2S_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(146, "vCNV_BT_I2S_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(147, "vCNV_BT_I2S_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(148, "vI2S2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(149, "vI2S2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(150, "vI2S2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(151, "vI2S2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(152, "vSD3_CD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(153, "SMBCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(154, "SMBDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(155, "SMBALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(156, "SML0CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(157, "SML0DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(158, "SML0ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(159, "SML1CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(160, "SML1DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(161, "UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(162, "UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(163, "UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(164, "UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(165, "UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(166, "UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(167, "UART1_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(168, "UART1_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(169, "I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(170, "I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(171, "I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(172, "I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(173, "UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(174, "UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(175, "UART2_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(176, "UART2_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* HVCMOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(177, "L_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(178, "L_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(179, "L_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(180, "SYS_PWROK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(181, "SYS_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(182, "MLK_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(183, "SATAXPCIE_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(184, "SPI1_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(185, "SPI1_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(186, "CPU_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(187, "SATA_DEVSLP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(188, "SATA_DEVSLP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(189, "GPPC_E_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(190, "CPU_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(191, "SATA_LEDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(192, "USB2_OCB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(193, "SPI1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(194, "SPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(195, "SPI1_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(196, "SPI1_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(197, "DDSP_HPD_A"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(198, "ISH_GP_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(199, "ISH_GP_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(200, "DISP_MISC_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(201, "DDP1_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(202, "DDP1_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(203, "DDP2_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(204, "DDP2_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(205, "DDPA_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(206, "DDPA_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* JTAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(207, "JTAG_TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(208, "JTAGX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(209, "PRDYB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(210, "PREQB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(211, "CPU_TRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(212, "JTAG_TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(213, "JTAG_TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(214, "JTAG_TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(215, "ITP_PMODE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* GPP_R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(216, "HDA_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(217, "HDA_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(218, "HDA_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(219, "HDA_SDI_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(220, "HDA_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(221, "HDA_SDI_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(222, "I2S1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(223, "I2S1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* GPP_S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(224, "SNDW1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(225, "SNDW1_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(226, "SNDW2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(227, "SNDW2_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(228, "SNDW3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(229, "SNDW3_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(230, "SNDW4_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(231, "SNDW4_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(232, "SPI0_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(233, "SPI0_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(234, "SPI0_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(235, "SPI0_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(236, "SPI0_TPM_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(237, "SPI0_FLASH_0_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(238, "SPI0_FLASH_1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(239, "SPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(240, "SPI0_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const struct intel_padgroup icllp_community0_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ICL_GPP(0, 0, 7, 0), /* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ICL_GPP(1, 8, 33, 32), /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ICL_GPP(2, 34, 58, 64), /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct intel_padgroup icllp_community1_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ICL_GPP(0, 59, 82, 96), /* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ICL_GPP(1, 83, 103, 128), /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ICL_GPP(2, 104, 123, 160), /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ICL_GPP(3, 124, 152, 192), /* vGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct intel_padgroup icllp_community4_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ICL_GPP(0, 153, 176, 224), /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ICL_GPP(2, 183, 206, 256), /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct intel_padgroup icllp_community5_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ICL_GPP(0, 216, 223, 288), /* GPP_R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ICL_GPP(1, 224, 231, 320), /* GPP_S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const struct intel_community icllp_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ICL_COMMUNITY(0, 0, 58, icllp_community0_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ICL_COMMUNITY(1, 59, 152, icllp_community1_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ICL_COMMUNITY(2, 153, 215, icllp_community4_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ICL_COMMUNITY(3, 216, 240, icllp_community5_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const unsigned int icllp_spi0_modes[] = { 3, 1, 1, 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const unsigned int icllp_spi1_pins[] = { 27, 28, 29, 30, 31 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const unsigned int icllp_spi1_modes[] = { 1, 1, 1, 1, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const unsigned int icllp_spi2_pins[] = { 92, 93, 94, 95, 98 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const unsigned int icllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const unsigned int icllp_i2c0_pins[] = { 169, 170 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const unsigned int icllp_i2c1_pins[] = { 171, 172 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const unsigned int icllp_i2c2_pins[] = { 63, 64 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const unsigned int icllp_i2c3_pins[] = { 65, 66 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const unsigned int icllp_i2c4_pins[] = { 67, 68 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const unsigned int icllp_uart0_pins[] = { 161, 162, 163, 164 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const unsigned int icllp_uart1_pins[] = { 165, 166, 167, 168 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const unsigned int icllp_uart2_pins[] = { 173, 174, 175, 176 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct intel_pingroup icllp_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PIN_GROUP("spi0_grp", icllp_spi0_pins, icllp_spi0_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PIN_GROUP("spi1_grp", icllp_spi1_pins, icllp_spi1_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PIN_GROUP("spi2_grp", icllp_spi2_pins, icllp_spi2_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PIN_GROUP("i2c0_grp", icllp_i2c0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PIN_GROUP("i2c1_grp", icllp_i2c1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PIN_GROUP("i2c2_grp", icllp_i2c2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PIN_GROUP("i2c3_grp", icllp_i2c3_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PIN_GROUP("i2c4_grp", icllp_i2c4_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PIN_GROUP("uart0_grp", icllp_uart0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PIN_GROUP("uart1_grp", icllp_uart1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PIN_GROUP("uart2_grp", icllp_uart2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const char * const icllp_spi0_groups[] = { "spi0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const char * const icllp_spi1_groups[] = { "spi1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const char * const icllp_spi2_groups[] = { "spi2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const char * const icllp_i2c0_groups[] = { "i2c0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const char * const icllp_i2c1_groups[] = { "i2c1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const char * const icllp_i2c2_groups[] = { "i2c2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const char * const icllp_i2c3_groups[] = { "i2c3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const char * const icllp_i2c4_groups[] = { "i2c4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const char * const icllp_uart0_groups[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const char * const icllp_uart1_groups[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const char * const icllp_uart2_groups[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct intel_function icllp_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) FUNCTION("spi0", icllp_spi0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) FUNCTION("spi1", icllp_spi1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) FUNCTION("spi2", icllp_spi2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) FUNCTION("i2c0", icllp_i2c0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) FUNCTION("i2c1", icllp_i2c1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) FUNCTION("i2c2", icllp_i2c2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) FUNCTION("i2c3", icllp_i2c3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) FUNCTION("i2c4", icllp_i2c4_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) FUNCTION("uart0", icllp_uart0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) FUNCTION("uart1", icllp_uart1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) FUNCTION("uart2", icllp_uart2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct intel_pinctrl_soc_data icllp_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .pins = icllp_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .npins = ARRAY_SIZE(icllp_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .groups = icllp_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .ngroups = ARRAY_SIZE(icllp_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .functions = icllp_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .nfunctions = ARRAY_SIZE(icllp_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .communities = icllp_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .ncommunities = ARRAY_SIZE(icllp_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { "INT3455", (kernel_ulong_t)&icllp_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct platform_driver icl_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .probe = intel_pinctrl_probe_by_hid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .name = "icelake-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .acpi_match_table = icl_pinctrl_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .pm = &icl_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) module_platform_driver(icl_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MODULE_DESCRIPTION("Intel Ice Lake PCH pinctrl/GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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