^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Gemini Lake SoC pinctrl/GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pinctrl-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GLK_PAD_OWN 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GLK_PADCFGLOCK 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GLK_HOSTSW_OWN 0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define GLK_GPI_IS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GLK_GPI_IE 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GLK_COMMUNITY(s, e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .padown_offset = GLK_PAD_OWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .padcfglock_offset = GLK_PADCFGLOCK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .hostown_offset = GLK_HOSTSW_OWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .is_offset = GLK_GPI_IS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .ie_offset = GLK_GPI_IE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .gpp_size = 32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .pin_base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .npins = ((e) - (s) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* GLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const struct pinctrl_pin_desc glk_northwest_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PINCTRL_PIN(0, "TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PINCTRL_PIN(1, "TRST_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PINCTRL_PIN(2, "TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PINCTRL_PIN(3, "TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PINCTRL_PIN(4, "TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PINCTRL_PIN(5, "JTAGX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PINCTRL_PIN(6, "CX_PREQ_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PINCTRL_PIN(7, "CX_PRDY_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PINCTRL_PIN(8, "GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PINCTRL_PIN(9, "GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PINCTRL_PIN(10, "GPIO_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PINCTRL_PIN(11, "GPIO_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PINCTRL_PIN(12, "GPIO_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PINCTRL_PIN(13, "GPIO_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PINCTRL_PIN(14, "GPIO_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PINCTRL_PIN(15, "GPIO_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PINCTRL_PIN(16, "GPIO_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINCTRL_PIN(17, "GPIO_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PINCTRL_PIN(18, "GPIO_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINCTRL_PIN(19, "GPIO_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PINCTRL_PIN(20, "GPIO_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN(21, "GPIO_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN(22, "GPIO_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN(23, "GPIO_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN(24, "GPIO_24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN(25, "GPIO_25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN(26, "ISH_GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINCTRL_PIN(27, "ISH_GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN(28, "ISH_GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN(29, "ISH_GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN(30, "ISH_GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN(31, "ISH_GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN(32, "ISH_GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(33, "ISH_GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINCTRL_PIN(34, "ISH_GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(35, "ISH_GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(36, "GPIO_36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINCTRL_PIN(37, "GPIO_37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(38, "GPIO_38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINCTRL_PIN(39, "GPIO_39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(40, "GPIO_40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PINCTRL_PIN(41, "GPIO_41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINCTRL_PIN(42, "GP_INTD_DSI_TE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINCTRL_PIN(43, "GP_INTD_DSI_TE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINCTRL_PIN(44, "USB_OC0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(45, "USB_OC1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PINCTRL_PIN(46, "DSI_I2C_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINCTRL_PIN(47, "DSI_I2C_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(48, "PMC_I2C_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(49, "PMC_I2C_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(50, "LPSS_I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINCTRL_PIN(51, "LPSS_I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(52, "LPSS_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(53, "LPSS_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(54, "LPSS_I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(55, "LPSS_I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(56, "LPSS_I2C3_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(57, "LPSS_I2C3_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(58, "LPSS_I2C4_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(59, "LPSS_I2C4_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(60, "LPSS_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(61, "LPSS_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(62, "LPSS_UART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(63, "LPSS_UART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(64, "LPSS_UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(65, "LPSS_UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(66, "LPSS_UART2_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(67, "LPSS_UART2_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(68, "PMC_SPI_FS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(69, "PMC_SPI_FS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(70, "PMC_SPI_FS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(71, "PMC_SPI_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(72, "PMC_SPI_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(73, "PMC_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(74, "THERMTRIP_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(75, "PROCHOT_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(76, "EMMC_RST_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(77, "GPIO_212"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(78, "GPIO_213"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(79, "GPIO_214"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const unsigned int glk_northwest_uart1_pins[] = { 26, 27, 28, 29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const unsigned int glk_northwest_pwm0_pins[] = { 42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const unsigned int glk_northwest_pwm1_pins[] = { 43 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const unsigned int glk_northwest_pwm2_pins[] = { 44 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const unsigned int glk_northwest_pwm3_pins[] = { 45 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const unsigned int glk_northwest_i2c0_pins[] = { 50, 51 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const unsigned int glk_northwest_i2c1_pins[] = { 52, 53 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const unsigned int glk_northwest_i2c2_pins[] = { 54, 55 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const unsigned int glk_northwest_i2c3_pins[] = { 56, 57 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const unsigned int glk_northwest_i2c4_pins[] = { 58, 59 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const unsigned int glk_northwest_uart0_pins[] = { 60, 61, 62, 63 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const unsigned int glk_northwest_uart2_pins[] = { 64, 65, 66, 67 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct intel_pingroup glk_northwest_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PIN_GROUP("uart1_grp", glk_northwest_uart1_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PIN_GROUP("pwm0_grp", glk_northwest_pwm0_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PIN_GROUP("pwm1_grp", glk_northwest_pwm1_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PIN_GROUP("pwm2_grp", glk_northwest_pwm2_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PIN_GROUP("pwm3_grp", glk_northwest_pwm3_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PIN_GROUP("i2c0_grp", glk_northwest_i2c0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PIN_GROUP("i2c1_grp", glk_northwest_i2c1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PIN_GROUP("i2c2_grp", glk_northwest_i2c2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PIN_GROUP("i2c3_grp", glk_northwest_i2c3_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PIN_GROUP("i2c4_grp", glk_northwest_i2c4_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PIN_GROUP("uart0_grp", glk_northwest_uart0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PIN_GROUP("uart2_grp", glk_northwest_uart2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const char * const glk_northwest_uart1_groups[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const char * const glk_northwest_pwm0_groups[] = { "pwm0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const char * const glk_northwest_pwm1_groups[] = { "pwm1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const char * const glk_northwest_pwm2_groups[] = { "pwm2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const char * const glk_northwest_pwm3_groups[] = { "pwm3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const char * const glk_northwest_i2c0_groups[] = { "i2c0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const char * const glk_northwest_i2c1_groups[] = { "i2c1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const char * const glk_northwest_i2c2_groups[] = { "i2c2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const char * const glk_northwest_i2c3_groups[] = { "i2c3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const char * const glk_northwest_i2c4_groups[] = { "i2c4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const char * const glk_northwest_uart0_groups[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const char * const glk_northwest_uart2_groups[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct intel_function glk_northwest_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) FUNCTION("uart1", glk_northwest_uart1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) FUNCTION("pmw0", glk_northwest_pwm0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) FUNCTION("pmw1", glk_northwest_pwm1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) FUNCTION("pmw2", glk_northwest_pwm2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) FUNCTION("pmw3", glk_northwest_pwm3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FUNCTION("i2c0", glk_northwest_i2c0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) FUNCTION("i2c1", glk_northwest_i2c1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) FUNCTION("i2c2", glk_northwest_i2c2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) FUNCTION("i2c3", glk_northwest_i2c3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FUNCTION("i2c4", glk_northwest_i2c4_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) FUNCTION("uart0", glk_northwest_uart0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) FUNCTION("uart2", glk_northwest_uart2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct intel_community glk_northwest_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) GLK_COMMUNITY(0, 79),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct intel_pinctrl_soc_data glk_northwest_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .uid = "1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .pins = glk_northwest_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .npins = ARRAY_SIZE(glk_northwest_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .groups = glk_northwest_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .ngroups = ARRAY_SIZE(glk_northwest_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .functions = glk_northwest_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .nfunctions = ARRAY_SIZE(glk_northwest_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .communities = glk_northwest_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .ncommunities = ARRAY_SIZE(glk_northwest_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct pinctrl_pin_desc glk_north_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(0, "SVID0_ALERT_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(1, "SVID0_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(2, "SVID0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(3, "LPSS_SPI_0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(4, "LPSS_SPI_0_FS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(5, "LPSS_SPI_0_FS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(6, "LPSS_SPI_0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(7, "LPSS_SPI_0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(8, "LPSS_SPI_2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(9, "LPSS_SPI_2_FS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(10, "LPSS_SPI_2_FS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(11, "LPSS_SPI_2_FS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(12, "LPSS_SPI_2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(13, "LPSS_SPI_2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(14, "FST_SPI_CS0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(15, "FST_SPI_CS1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(17, "FST_SPI_MISO_IO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(18, "FST_SPI_IO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(19, "FST_SPI_IO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(20, "FST_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(21, "FST_SPI_CLK_FB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(22, "PMU_PLTRST_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(23, "PMU_PWRBTN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(24, "PMU_SLP_S0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(25, "PMU_SLP_S3_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(26, "PMU_SLP_S4_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(27, "SUSPWRDNACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(28, "EMMC_DNX_PWR_EN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(29, "GPIO_105"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(30, "PMU_BATLOW_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(31, "PMU_RESETBUTTON_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(32, "PMU_SUSCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(33, "SUS_STAT_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(34, "LPSS_I2C5_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(35, "LPSS_I2C5_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(36, "LPSS_I2C6_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(37, "LPSS_I2C6_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(38, "LPSS_I2C7_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(39, "LPSS_I2C7_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(40, "PCIE_WAKE0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(41, "PCIE_WAKE1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(42, "PCIE_WAKE2_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(43, "PCIE_WAKE3_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(44, "PCIE_CLKREQ0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(45, "PCIE_CLKREQ1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(46, "PCIE_CLKREQ2_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(47, "PCIE_CLKREQ3_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(48, "HV_DDI0_DDC_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(49, "HV_DDI0_DDC_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(50, "HV_DDI1_DDC_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(51, "HV_DDI1_DDC_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(52, "PANEL0_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(53, "PANEL0_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(54, "PANEL0_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(55, "HV_DDI0_HPD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(56, "HV_DDI1_HPD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(57, "HV_EDP_HPD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(58, "GPIO_134"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(59, "GPIO_135"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(60, "GPIO_136"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(61, "GPIO_137"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(62, "GPIO_138"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(63, "GPIO_139"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(64, "GPIO_140"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(65, "GPIO_141"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(66, "GPIO_142"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(67, "GPIO_143"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(68, "GPIO_144"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(69, "GPIO_145"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(70, "GPIO_146"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(71, "LPC_ILB_SERIRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(72, "LPC_CLKOUT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(73, "LPC_CLKOUT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(74, "LPC_AD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(75, "LPC_AD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(76, "LPC_AD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(77, "LPC_AD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(78, "LPC_CLKRUNB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(79, "LPC_FRAMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const unsigned int glk_north_spi0_pins[] = { 3, 4, 5, 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const unsigned int glk_north_spi1_pins[] = { 8, 9, 10, 11, 12, 13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const unsigned int glk_north_i2c5_pins[] = { 34, 35 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const unsigned int glk_north_i2c6_pins[] = { 36, 37 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const unsigned int glk_north_i2c7_pins[] = { 38, 39 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const unsigned int glk_north_uart0_pins[] = { 62, 63, 64, 65 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const unsigned int glk_north_spi0b_pins[] = { 66, 67, 68, 69, 70 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const struct intel_pingroup glk_north_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PIN_GROUP("spi0_grp", glk_north_spi0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PIN_GROUP("spi1_grp", glk_north_spi1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PIN_GROUP("i2c5_grp", glk_north_i2c5_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PIN_GROUP("i2c6_grp", glk_north_i2c6_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PIN_GROUP("i2c7_grp", glk_north_i2c7_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PIN_GROUP("uart0_grp", glk_north_uart0_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PIN_GROUP("spi0b_grp", glk_north_spi0b_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const char * const glk_north_spi0_groups[] = { "spi0_grp", "spi0b_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const char * const glk_north_spi1_groups[] = { "spi1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const char * const glk_north_i2c5_groups[] = { "i2c5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const char * const glk_north_i2c6_groups[] = { "i2c6_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const char * const glk_north_i2c7_groups[] = { "i2c7_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const char * const glk_north_uart0_groups[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct intel_function glk_north_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) FUNCTION("spi0", glk_north_spi0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) FUNCTION("spi1", glk_north_spi1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) FUNCTION("i2c5", glk_north_i2c5_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) FUNCTION("i2c6", glk_north_i2c6_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) FUNCTION("i2c7", glk_north_i2c7_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) FUNCTION("uart0", glk_north_uart0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct intel_community glk_north_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) GLK_COMMUNITY(0, 79),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct intel_pinctrl_soc_data glk_north_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .uid = "2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .pins = glk_north_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .npins = ARRAY_SIZE(glk_north_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .groups = glk_north_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .ngroups = ARRAY_SIZE(glk_north_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .functions = glk_north_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .nfunctions = ARRAY_SIZE(glk_north_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .communities = glk_north_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .ncommunities = ARRAY_SIZE(glk_north_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct pinctrl_pin_desc glk_audio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(0, "AVS_I2S0_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(1, "AVS_I2S0_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(2, "AVS_I2S0_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(3, "AVS_I2S0_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(4, "AVS_I2S0_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(5, "AVS_I2S1_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(6, "AVS_I2S1_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(7, "AVS_I2S1_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(8, "AVS_I2S1_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(9, "AVS_I2S1_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(10, "AVS_HDA_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(11, "AVS_HDA_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(12, "AVS_HDA_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_PIN(13, "AVS_HDA_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(14, "AVS_HDA_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(15, "AVS_M_CLK_A1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(16, "AVS_M_CLK_B1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(17, "AVS_M_DATA_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(18, "AVS_M_CLK_AB2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(19, "AVS_M_DATA_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct intel_community glk_audio_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) GLK_COMMUNITY(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const struct intel_pinctrl_soc_data glk_audio_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .uid = "3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .pins = glk_audio_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .npins = ARRAY_SIZE(glk_audio_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .communities = glk_audio_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .ncommunities = ARRAY_SIZE(glk_audio_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct pinctrl_pin_desc glk_scc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINCTRL_PIN(0, "SMB_ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PINCTRL_PIN(1, "SMB_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PINCTRL_PIN(2, "SMB_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINCTRL_PIN(3, "SDCARD_LVL_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINCTRL_PIN(4, "SDCARD_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINCTRL_PIN(5, "SDCARD_CLK_FB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PINCTRL_PIN(6, "SDCARD_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINCTRL_PIN(7, "SDCARD_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINCTRL_PIN(8, "SDCARD_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINCTRL_PIN(9, "SDCARD_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PINCTRL_PIN(10, "SDCARD_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PINCTRL_PIN(11, "SDCARD_CD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PINCTRL_PIN(12, "SDCARD_PWR_DOWN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINCTRL_PIN(13, "GPIO_210"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PINCTRL_PIN(14, "OSC_CLK_OUT_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINCTRL_PIN(15, "OSC_CLK_OUT_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINCTRL_PIN(16, "CNV_BRI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PINCTRL_PIN(17, "CNV_BRI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINCTRL_PIN(18, "CNV_RGI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINCTRL_PIN(19, "CNV_RGI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINCTRL_PIN(20, "CNV_RF_RESET_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINCTRL_PIN(21, "XTAL_CLKREQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PINCTRL_PIN(22, "SDIO_CLK_FB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINCTRL_PIN(23, "EMMC0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINCTRL_PIN(24, "EMMC0_CLK_FB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINCTRL_PIN(25, "EMMC0_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINCTRL_PIN(26, "EMMC0_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINCTRL_PIN(27, "EMMC0_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINCTRL_PIN(28, "EMMC0_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINCTRL_PIN(29, "EMMC0_D4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINCTRL_PIN(30, "EMMC0_D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PINCTRL_PIN(31, "EMMC0_D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINCTRL_PIN(32, "EMMC0_D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINCTRL_PIN(33, "EMMC0_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINCTRL_PIN(34, "EMMC0_STROBE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const unsigned int glk_scc_i2c7_pins[] = { 1, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const unsigned int glk_scc_sdcard_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const unsigned int glk_scc_sdio_pins[] = { 16, 17, 18, 19, 20, 21, 22 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const unsigned int glk_scc_uart1_pins[] = { 16, 17, 18, 19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const unsigned int glk_scc_emmc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct intel_pingroup glk_scc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PIN_GROUP("i2c7_grp", glk_scc_i2c7_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PIN_GROUP("sdcard_grp", glk_scc_sdcard_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PIN_GROUP("sdio_grp", glk_scc_sdio_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PIN_GROUP("uart1_grp", glk_scc_uart1_pins, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PIN_GROUP("emmc_grp", glk_scc_emmc_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const char * const glk_scc_i2c7_groups[] = { "i2c7_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const char * const glk_scc_sdcard_groups[] = { "sdcard_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const char * const glk_scc_sdio_groups[] = { "sdio_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const char * const glk_scc_uart1_groups[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const char * const glk_scc_emmc_groups[] = { "emmc_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const struct intel_function glk_scc_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) FUNCTION("i2c7", glk_scc_i2c7_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) FUNCTION("sdcard", glk_scc_sdcard_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) FUNCTION("sdio", glk_scc_sdio_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) FUNCTION("uart1", glk_scc_uart1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) FUNCTION("emmc", glk_scc_emmc_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const struct intel_community glk_scc_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) GLK_COMMUNITY(0, 34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct intel_pinctrl_soc_data glk_scc_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .uid = "4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .pins = glk_scc_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .npins = ARRAY_SIZE(glk_scc_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .groups = glk_scc_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .ngroups = ARRAY_SIZE(glk_scc_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .functions = glk_scc_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .nfunctions = ARRAY_SIZE(glk_scc_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .communities = glk_scc_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .ncommunities = ARRAY_SIZE(glk_scc_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct intel_pinctrl_soc_data *glk_pinctrl_soc_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) &glk_northwest_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) &glk_north_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) &glk_audio_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) &glk_scc_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const struct acpi_device_id glk_pinctrl_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { "INT3453", (kernel_ulong_t)glk_pinctrl_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_DEVICE_TABLE(acpi, glk_pinctrl_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static INTEL_PINCTRL_PM_OPS(glk_pinctrl_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static struct platform_driver glk_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .probe = intel_pinctrl_probe_by_uid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .name = "geminilake-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .acpi_match_table = glk_pinctrl_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .pm = &glk_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int __init glk_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return platform_driver_register(&glk_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) subsys_initcall(glk_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static void __exit glk_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) platform_driver_unregister(&glk_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) module_exit(glk_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_DESCRIPTION("Intel Gemini Lake SoC pinctrl/GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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