Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Intel Denverton SoC pinctrl/GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "pinctrl-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DNV_PAD_OWN	0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DNV_PADCFGLOCK	0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define DNV_HOSTSW_OWN	0x0C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define DNV_GPI_IS	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DNV_GPI_IE	0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DNV_GPP(n, s, e)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		.reg_num = (n),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		.base = (s),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		.size = ((e) - (s) + 1),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DNV_COMMUNITY(b, s, e, g)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	{						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		.barno = (b),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		.padown_offset = DNV_PAD_OWN,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		.padcfglock_offset = DNV_PADCFGLOCK,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		.hostown_offset = DNV_HOSTSW_OWN,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		.is_offset = DNV_GPI_IS,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.ie_offset = DNV_GPI_IE,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		.pin_base = (s),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.npins = ((e) - (s) + 1),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.gpps = (g),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.ngpps = ARRAY_SIZE(g),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* Denverton */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static const struct pinctrl_pin_desc dnv_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* North ALL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	PINCTRL_PIN(0, "GBE0_SDP0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	PINCTRL_PIN(1, "GBE1_SDP0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	PINCTRL_PIN(2, "GBE0_SDP1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	PINCTRL_PIN(3, "GBE1_SDP1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	PINCTRL_PIN(4, "GBE0_SDP2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	PINCTRL_PIN(5, "GBE1_SDP2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	PINCTRL_PIN(6, "GBE0_SDP3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	PINCTRL_PIN(7, "GBE1_SDP3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	PINCTRL_PIN(8, "GBE2_LED0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	PINCTRL_PIN(9, "GBE2_LED1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	PINCTRL_PIN(10, "GBE0_I2C_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	PINCTRL_PIN(11, "GBE0_I2C_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	PINCTRL_PIN(12, "GBE1_I2C_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	PINCTRL_PIN(13, "GBE1_I2C_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	PINCTRL_PIN(14, "NCSI_RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	PINCTRL_PIN(15, "NCSI_CLK_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	PINCTRL_PIN(16, "NCSI_RXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	PINCTRL_PIN(17, "NCSI_CRS_DV"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	PINCTRL_PIN(18, "IDSLDO_VID_TICKLE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	PINCTRL_PIN(19, "NCSI_TX_EN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	PINCTRL_PIN(20, "NCSI_TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	PINCTRL_PIN(21, "NCSI_TXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	PINCTRL_PIN(22, "NCSI_ARB_OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	PINCTRL_PIN(23, "GBE0_LED0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	PINCTRL_PIN(24, "GBE0_LED1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	PINCTRL_PIN(25, "GBE1_LED0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	PINCTRL_PIN(26, "GBE1_LED1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	PINCTRL_PIN(27, "SPARE_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	PINCTRL_PIN(28, "PCIE_CLKREQ0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	PINCTRL_PIN(29, "PCIE_CLKREQ1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	PINCTRL_PIN(30, "PCIE_CLKREQ2_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	PINCTRL_PIN(31, "PCIE_CLKREQ3_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	PINCTRL_PIN(32, "PCIE_CLKREQ4_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	PINCTRL_PIN(33, "GBE_MDC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	PINCTRL_PIN(34, "GBE_MDIO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	PINCTRL_PIN(35, "SVID_ALERT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	PINCTRL_PIN(36, "SVID_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	PINCTRL_PIN(37, "SVID_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	PINCTRL_PIN(38, "THERMTRIP_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	PINCTRL_PIN(39, "PROCHOT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	PINCTRL_PIN(40, "MEMHOT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	/* South DFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	PINCTRL_PIN(41, "DFX_PORT_CLK0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	PINCTRL_PIN(42, "DFX_PORT_CLK1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	PINCTRL_PIN(43, "DFX_PORT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	PINCTRL_PIN(44, "DFX_PORT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	PINCTRL_PIN(45, "DFX_PORT2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	PINCTRL_PIN(46, "DFX_PORT3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	PINCTRL_PIN(47, "DFX_PORT4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	PINCTRL_PIN(48, "DFX_PORT5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	PINCTRL_PIN(49, "DFX_PORT6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	PINCTRL_PIN(50, "DFX_PORT7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	PINCTRL_PIN(51, "DFX_PORT8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	PINCTRL_PIN(52, "DFX_PORT9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	PINCTRL_PIN(53, "DFX_PORT10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	PINCTRL_PIN(54, "DFX_PORT11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	PINCTRL_PIN(55, "DFX_PORT12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	PINCTRL_PIN(56, "DFX_PORT13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	PINCTRL_PIN(57, "DFX_PORT14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	PINCTRL_PIN(58, "DFX_PORT15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* South GPP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	PINCTRL_PIN(59, "SPI_TPM_CS_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	PINCTRL_PIN(60, "UART2_CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	PINCTRL_PIN(61, "PCIE_CLKREQ5_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	PINCTRL_PIN(62, "PCIE_CLKREQ6_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	PINCTRL_PIN(63, "PCIE_CLKREQ7_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	PINCTRL_PIN(64, "UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	PINCTRL_PIN(65, "UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	PINCTRL_PIN(66, "CPU_RESET_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	PINCTRL_PIN(67, "NMI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	PINCTRL_PIN(68, "ERROR2_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	PINCTRL_PIN(69, "ERROR1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	PINCTRL_PIN(70, "ERROR0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	PINCTRL_PIN(71, "IERR_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	PINCTRL_PIN(72, "MCERR_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	PINCTRL_PIN(73, "SMB0_LEG_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	PINCTRL_PIN(74, "SMB0_LEG_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	PINCTRL_PIN(75, "SMB0_LEG_ALRT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	PINCTRL_PIN(76, "SMB1_HOST_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	PINCTRL_PIN(77, "SMB1_HOST_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	PINCTRL_PIN(78, "SMB2_PECI_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	PINCTRL_PIN(79, "SMB2_PECI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	PINCTRL_PIN(80, "SMB4_CSME0_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	PINCTRL_PIN(81, "SMB4_CSME0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	PINCTRL_PIN(82, "SMB4_CSME0_ALRT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	PINCTRL_PIN(83, "USB_OC0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	PINCTRL_PIN(84, "FLEX_CLK_SE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	PINCTRL_PIN(85, "FLEX_CLK_SE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	PINCTRL_PIN(86, "SPARE_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	PINCTRL_PIN(87, "SMB3_IE0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	PINCTRL_PIN(88, "SMB3_IE0_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	PINCTRL_PIN(89, "SMB3_IE0_ALRT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	PINCTRL_PIN(90, "SATA0_LED_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	PINCTRL_PIN(91, "SATA1_LED_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	PINCTRL_PIN(92, "SATA_PDETECT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	PINCTRL_PIN(93, "SATA_PDETECT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	PINCTRL_PIN(94, "UART1_RTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	PINCTRL_PIN(95, "UART1_CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	PINCTRL_PIN(96, "UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	PINCTRL_PIN(97, "UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	PINCTRL_PIN(98, "SPARE_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	PINCTRL_PIN(99, "SPARE_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	PINCTRL_PIN(100, "TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	PINCTRL_PIN(101, "TRST_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	PINCTRL_PIN(102, "TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	PINCTRL_PIN(103, "TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	PINCTRL_PIN(104, "TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	PINCTRL_PIN(105, "CX_PRDY_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	PINCTRL_PIN(106, "CX_PREQ_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	PINCTRL_PIN(107, "TAP1_TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	PINCTRL_PIN(108, "TAP1_TRST_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	PINCTRL_PIN(109, "TAP1_TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	PINCTRL_PIN(110, "TAP1_TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	PINCTRL_PIN(111, "TAP1_TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* South GPP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	PINCTRL_PIN(112, "SUSPWRDNACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	PINCTRL_PIN(113, "PMU_SUSCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	PINCTRL_PIN(114, "ADR_TRIGGER"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	PINCTRL_PIN(115, "PMU_SLP_S45_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	PINCTRL_PIN(116, "PMU_SLP_S3_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	PINCTRL_PIN(117, "PMU_WAKE_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	PINCTRL_PIN(118, "PMU_PWRBTN_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	PINCTRL_PIN(119, "PMU_RESETBUTTON_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	PINCTRL_PIN(120, "PMU_PLTRST_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	PINCTRL_PIN(121, "SUS_STAT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	PINCTRL_PIN(122, "SLP_S0IX_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	PINCTRL_PIN(123, "SPI_CS0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	PINCTRL_PIN(124, "SPI_CS1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	PINCTRL_PIN(125, "SPI_MOSI_IO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	PINCTRL_PIN(126, "SPI_MISO_IO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	PINCTRL_PIN(127, "SPI_IO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	PINCTRL_PIN(128, "SPI_IO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	PINCTRL_PIN(129, "SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	PINCTRL_PIN(130, "SPI_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	PINCTRL_PIN(131, "ESPI_IO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	PINCTRL_PIN(132, "ESPI_IO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	PINCTRL_PIN(133, "ESPI_IO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	PINCTRL_PIN(134, "ESPI_IO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	PINCTRL_PIN(135, "ESPI_CS0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	PINCTRL_PIN(136, "ESPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	PINCTRL_PIN(137, "ESPI_RST_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	PINCTRL_PIN(138, "ESPI_ALRT0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	PINCTRL_PIN(139, "ESPI_CS1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	PINCTRL_PIN(140, "ESPI_ALRT1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	PINCTRL_PIN(142, "EMMC_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	PINCTRL_PIN(143, "EMMC_STROBE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	PINCTRL_PIN(144, "EMMC_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	PINCTRL_PIN(145, "EMMC_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	PINCTRL_PIN(146, "EMMC_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	PINCTRL_PIN(147, "EMMC_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	PINCTRL_PIN(148, "EMMC_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	PINCTRL_PIN(149, "EMMC_D4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	PINCTRL_PIN(150, "EMMC_D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	PINCTRL_PIN(151, "EMMC_D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	PINCTRL_PIN(152, "EMMC_D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	PINCTRL_PIN(153, "SPARE_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const unsigned int dnv_uart2_modes[] = { 1, 2, 2, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const unsigned int dnv_emmc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct intel_pingroup dnv_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	PIN_GROUP("uart0_grp", dnv_uart0_pins, dnv_uart0_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	PIN_GROUP("uart1_grp", dnv_uart1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	PIN_GROUP("uart2_grp", dnv_uart2_pins, dnv_uart2_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	PIN_GROUP("emmc_grp", dnv_emmc_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const char * const dnv_uart0_groups[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const char * const dnv_uart1_groups[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const char * const dnv_uart2_groups[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const char * const dnv_emmc_groups[] = { "emmc_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const struct intel_function dnv_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	FUNCTION("uart0", dnv_uart0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	FUNCTION("uart1", dnv_uart1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	FUNCTION("uart2", dnv_uart2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	FUNCTION("emmc", dnv_emmc_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const struct intel_padgroup dnv_north_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	DNV_GPP(0, 0, 31),	/* North ALL_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	DNV_GPP(1, 32, 40),	/* North ALL_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct intel_padgroup dnv_south_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	DNV_GPP(0, 41, 58),	/* South DFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	DNV_GPP(1, 59, 90),	/* South GPP0_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	DNV_GPP(2, 91, 111),	/* South GPP0_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	DNV_GPP(3, 112, 143),	/* South GPP1_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	DNV_GPP(4, 144, 153),	/* South GPP1_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct intel_community dnv_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	DNV_COMMUNITY(0, 0, 40, dnv_north_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	DNV_COMMUNITY(1, 41, 153, dnv_south_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct intel_pinctrl_soc_data dnv_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.pins = dnv_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.npins = ARRAY_SIZE(dnv_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.groups = dnv_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.ngroups = ARRAY_SIZE(dnv_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.functions = dnv_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.nfunctions = ARRAY_SIZE(dnv_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.communities = dnv_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.ncommunities = ARRAY_SIZE(dnv_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static INTEL_PINCTRL_PM_OPS(dnv_pinctrl_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	{ "INTC3000", (kernel_ulong_t)&dnv_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static struct platform_driver dnv_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.probe = intel_pinctrl_probe_by_hid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.name = "denverton-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.acpi_match_table = dnv_pinctrl_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.pm = &dnv_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int __init dnv_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return platform_driver_register(&dnv_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) subsys_initcall(dnv_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void __exit dnv_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	platform_driver_unregister(&dnv_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) module_exit(dnv_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_LICENSE("GPL v2");