^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cherryview/Braswell pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014, 2020 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This driver is based on the original Cherryview GPIO driver by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Ning Li <ning.li@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Alan Cox <alan@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "pinctrl-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CHV_INTSTAT 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CHV_INTMASK 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FAMILY_PAD_REGS_OFF 0x4400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FAMILY_PAD_REGS_SIZE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX_FAMILY_PAD_GPIO_NO 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GPIO_REGS_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CHV_PADCTRL0 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CHV_PADCTRL0_INTSEL_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CHV_PADCTRL0_TERM_UP BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CHV_PADCTRL0_TERM_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CHV_PADCTRL0_TERM_20K 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CHV_PADCTRL0_TERM_5K 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CHV_PADCTRL0_TERM_1K 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CHV_PADCTRL0_PMODE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CHV_PADCTRL0_GPIOEN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CHV_PADCTRL0_GPIOCFG_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CHV_PADCTRL0_GPIOCFG_GPIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CHV_PADCTRL0_GPIOCFG_GPO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CHV_PADCTRL0_GPIOCFG_GPI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CHV_PADCTRL0_GPIOCFG_HIZ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CHV_PADCTRL0_GPIORXSTATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CHV_PADCTRL1 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CHV_PADCTRL1_CFGLOCK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CHV_PADCTRL1_INVRXTX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CHV_PADCTRL1_ODEN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CHV_PADCTRL1_INTWAKECFG_RISING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CHV_PADCTRL1_INTWAKECFG_BOTH 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct intel_pad_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 padctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 padctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * struct intel_community_context - community context for Cherryview
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @saved_intmask: Interrupt mask saved for system sleep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct intel_community_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int intr_lines[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 saved_intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PINMODE_INVERT_OE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CHV_GPP(start, end) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .base = (start), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .size = (end) - (start) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CHV_COMMUNITY(g, i, a) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .gpps = (g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .ngpps = ARRAY_SIZE(g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .nirqs = (i), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .acpi_space_id = (a), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct pinctrl_pin_desc southwest_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(0, "FST_SPI_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(1, "FST_SPI_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(2, "FST_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(3, "FST_SPI_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(4, "FST_SPI_CS1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(5, "FST_SPI_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(6, "FST_SPI_CS0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(7, "FST_SPI_CS2_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(15, "UART1_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(16, "UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(17, "UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(18, "UART1_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(19, "UART2_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(20, "UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(21, "UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(22, "UART2_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(30, "MF_HDA_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(31, "MF_HDA_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(32, "MF_HDA_SDIO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(33, "MF_HDA_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(35, "MF_HDA_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(36, "MF_HDA_SDI1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(45, "I2C5_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(46, "I2C4_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(47, "I2C6_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(48, "I2C5_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(49, "I2C_NFC_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(50, "I2C4_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(51, "I2C6_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(52, "I2C_NFC_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(60, "I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(61, "I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(62, "I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(63, "I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(64, "I2C3_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(65, "I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(66, "I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(67, "I2C3_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(75, "SATA_GP0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(76, "SATA_GP1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(77, "SATA_LEDN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(78, "SATA_GP2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(79, "MF_SMB_ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(80, "SATA_GP3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(81, "MF_SMB_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(82, "MF_SMB_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(92, "GP_SSP_2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(94, "GP_SSP_2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(96, "GP_SSP_2_FS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(97, "GP_SSP_2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const unsigned southwest_uart0_pins[] = { 16, 20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const unsigned southwest_i2c0_pins[] = { 61, 65 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const unsigned southwest_lpe_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const unsigned southwest_i2c1_pins[] = { 60, 63 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const unsigned southwest_i2c2_pins[] = { 62, 66 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const unsigned southwest_i2c3_pins[] = { 64, 67 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const unsigned southwest_i2c4_pins[] = { 46, 50 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const unsigned southwest_i2c5_pins[] = { 45, 48 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const unsigned southwest_i2c6_pins[] = { 47, 51 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Some of LPE I2S TXD pins need to have OE inversion set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const unsigned int southwest_lpe_altfuncs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Two spi3 chipselects are available in different mode than the main spi3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * functionality, which is using mode 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const unsigned int southwest_spi3_altfuncs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINMODE(2, 0), /* 82 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct intel_pingroup southwest_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const char * const southwest_uart0_groups[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const char * const southwest_uart1_groups[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const char * const southwest_uart2_groups[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const char * const southwest_hda_groups[] = { "hda_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const char * const southwest_lpe_groups[] = { "lpe_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const char * const southwest_spi3_groups[] = { "spi3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * enabled only as GPIOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct intel_function southwest_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) FUNCTION("uart0", southwest_uart0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) FUNCTION("uart1", southwest_uart1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) FUNCTION("uart2", southwest_uart2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) FUNCTION("hda", southwest_hda_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) FUNCTION("lpe", southwest_lpe_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) FUNCTION("i2c0", southwest_i2c0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) FUNCTION("i2c1", southwest_i2c1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) FUNCTION("i2c2", southwest_i2c2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) FUNCTION("i2c3", southwest_i2c3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) FUNCTION("i2c4", southwest_i2c4_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) FUNCTION("i2c5", southwest_i2c5_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) FUNCTION("i2c6", southwest_i2c6_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) FUNCTION("spi3", southwest_spi3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct intel_padgroup southwest_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) CHV_GPP(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CHV_GPP(15, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) CHV_GPP(30, 37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) CHV_GPP(45, 52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) CHV_GPP(60, 67),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) CHV_GPP(75, 82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) CHV_GPP(90, 97),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * Southwest community can generate GPIO interrupts only for the first 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * interrupts. The upper half (8-15) can only be used to trigger GPEs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct intel_community southwest_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) CHV_COMMUNITY(southwest_gpps, 8, 0x91),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const struct intel_pinctrl_soc_data southwest_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .uid = "1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .pins = southwest_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .npins = ARRAY_SIZE(southwest_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .groups = southwest_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .ngroups = ARRAY_SIZE(southwest_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .functions = southwest_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .nfunctions = ARRAY_SIZE(southwest_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .communities = southwest_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .ncommunities = ARRAY_SIZE(southwest_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct pinctrl_pin_desc north_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(0, "GPIO_DFX_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(1, "GPIO_DFX_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(2, "GPIO_DFX_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(3, "GPIO_DFX_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(4, "GPIO_DFX_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(5, "GPIO_DFX_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(6, "GPIO_DFX_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(7, "GPIO_DFX_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(8, "GPIO_DFX_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(15, "GPIO_SUS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(17, "GPIO_SUS3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(18, "GPIO_SUS7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(19, "GPIO_SUS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(20, "GPIO_SUS5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(22, "GPIO_SUS4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(24, "GPIO_SUS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(25, "GPIO_SUS6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(26, "CX_PREQ_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(30, "TRST_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(31, "TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(32, "PROCHOT_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(33, "SVIDO_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(34, "TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(35, "CX_PRDY_B_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(36, "TDO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(37, "CX_PRDY_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(38, "SVIDO_ALERT_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(39, "TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(40, "SVIDO_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(41, "TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(45, "GP_CAMERASB_05"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(46, "GP_CAMERASB_02"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(47, "GP_CAMERASB_08"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(48, "GP_CAMERASB_00"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(49, "GP_CAMERASB_06"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(50, "GP_CAMERASB_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(51, "GP_CAMERASB_03"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(52, "GP_CAMERASB_09"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(53, "GP_CAMERASB_01"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(54, "GP_CAMERASB_07"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(55, "GP_CAMERASB_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(56, "GP_CAMERASB_04"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(60, "PANEL0_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(61, "HV_DDI0_HPD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(64, "HV_DDI1_HPD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(68, "HV_DDI2_HPD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(69, "PANEL1_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(70, "PANEL1_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_PIN(72, "PANEL0_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const struct intel_padgroup north_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) CHV_GPP(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) CHV_GPP(15, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) CHV_GPP(30, 41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) CHV_GPP(45, 56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) CHV_GPP(60, 72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * North community can generate GPIO interrupts only for the first 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * interrupts. The upper half (8-15) can only be used to trigger GPEs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct intel_community north_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) CHV_COMMUNITY(north_gpps, 8, 0x92),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct intel_pinctrl_soc_data north_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .uid = "2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .pins = north_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .npins = ARRAY_SIZE(north_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .communities = north_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .ncommunities = ARRAY_SIZE(north_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct pinctrl_pin_desc east_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINCTRL_PIN(0, "PMU_SLP_S3_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PINCTRL_PIN(1, "PMU_BATLOW_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINCTRL_PIN(2, "SUS_STAT_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINCTRL_PIN(4, "PMU_AC_PRESENT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINCTRL_PIN(5, "PMU_PLTRST_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PINCTRL_PIN(6, "PMU_SUSCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINCTRL_PIN(8, "PMU_PWRBTN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINCTRL_PIN(9, "PMU_SLP_S4_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINCTRL_PIN(10, "PMU_WAKE_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct intel_padgroup east_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) CHV_GPP(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) CHV_GPP(15, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct intel_community east_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) CHV_COMMUNITY(east_gpps, 16, 0x93),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct intel_pinctrl_soc_data east_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .uid = "3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .pins = east_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .npins = ARRAY_SIZE(east_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .communities = east_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .ncommunities = ARRAY_SIZE(east_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct pinctrl_pin_desc southeast_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINCTRL_PIN(0, "MF_PLT_CLK0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINCTRL_PIN(1, "PWM1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINCTRL_PIN(2, "MF_PLT_CLK1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINCTRL_PIN(3, "MF_PLT_CLK4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINCTRL_PIN(4, "MF_PLT_CLK3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINCTRL_PIN(5, "PWM0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINCTRL_PIN(6, "MF_PLT_CLK5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINCTRL_PIN(7, "MF_PLT_CLK2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINCTRL_PIN(16, "SDMMC1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINCTRL_PIN(17, "SDMMC1_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINCTRL_PIN(18, "SDMMC2_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINCTRL_PIN(19, "SDMMC2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINCTRL_PIN(20, "SDMMC1_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINCTRL_PIN(21, "SDMMC2_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PINCTRL_PIN(22, "SDMMC2_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINCTRL_PIN(23, "SDMMC1_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINCTRL_PIN(24, "SDMMC1_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINCTRL_PIN(25, "SDMMC2_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINCTRL_PIN(30, "SDMMC3_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINCTRL_PIN(31, "SDMMC3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINCTRL_PIN(32, "SDMMC3_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINCTRL_PIN(33, "SDMMC3_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINCTRL_PIN(34, "SDMMC3_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PINCTRL_PIN(35, "SDMMC3_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PINCTRL_PIN(45, "MF_LPC_AD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PINCTRL_PIN(46, "LPC_CLKRUNB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PINCTRL_PIN(47, "MF_LPC_AD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PINCTRL_PIN(48, "LPC_FRAMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINCTRL_PIN(50, "MF_LPC_AD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINCTRL_PIN(52, "MF_LPC_AD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINCTRL_PIN(60, "SPI1_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINCTRL_PIN(61, "SPI1_CSO_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PINCTRL_PIN(62, "SPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINCTRL_PIN(63, "MMC1_D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINCTRL_PIN(64, "SPI1_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINCTRL_PIN(65, "MMC1_D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINCTRL_PIN(66, "SPI1_CS1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PINCTRL_PIN(68, "MMC1_D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINCTRL_PIN(69, "MMC1_RCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINCTRL_PIN(75, "USB_OC1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINCTRL_PIN(77, "GPIO_ALERT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINCTRL_PIN(79, "ILB_SERIRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINCTRL_PIN(80, "USB_OC0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINCTRL_PIN(81, "SDMMC3_CD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINCTRL_PIN(82, "SPKR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINCTRL_PIN(83, "SUSPWRDNACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINCTRL_PIN(84, "SPARE_PIN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const unsigned southeast_pwm0_pins[] = { 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const unsigned southeast_pwm1_pins[] = { 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const unsigned southeast_sdmmc1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const unsigned southeast_sdmmc3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 30, 31, 32, 33, 34, 35, 78, 81, 85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct intel_pingroup southeast_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static const char * const southeast_spi1_groups[] = { "spi1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const char * const southeast_spi2_groups[] = { "spi2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const struct intel_function southeast_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) FUNCTION("pwm0", southeast_pwm0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) FUNCTION("pwm1", southeast_pwm1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) FUNCTION("sdmmc1", southeast_sdmmc1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) FUNCTION("sdmmc2", southeast_sdmmc2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) FUNCTION("sdmmc3", southeast_sdmmc3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) FUNCTION("spi1", southeast_spi1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) FUNCTION("spi2", southeast_spi2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const struct intel_padgroup southeast_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) CHV_GPP(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) CHV_GPP(15, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) CHV_GPP(30, 35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) CHV_GPP(45, 52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) CHV_GPP(60, 69),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) CHV_GPP(75, 85),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const struct intel_community southeast_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) CHV_COMMUNITY(southeast_gpps, 16, 0x94),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const struct intel_pinctrl_soc_data southeast_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .uid = "4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .pins = southeast_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .npins = ARRAY_SIZE(southeast_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .groups = southeast_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .ngroups = ARRAY_SIZE(southeast_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .functions = southeast_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .nfunctions = ARRAY_SIZE(southeast_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .communities = southeast_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .ncommunities = ARRAY_SIZE(southeast_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const struct intel_pinctrl_soc_data *chv_soc_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) &southwest_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) &north_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) &east_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) &southeast_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * Lock to serialize register accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * Due to a silicon issue, a shared lock must be used to prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * concurrent accesses across the 4 GPIO controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * errata #CHT34, for further information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static DEFINE_RAW_SPINLOCK(chv_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) const struct intel_community *community = &pctrl->communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return readl(community->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) const struct intel_community *community = &pctrl->communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) void __iomem *reg = community->regs + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Write and simple read back to confirm the bus transferring done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) writel(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) const struct intel_community *community = &pctrl->communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return community->pad_regs + offset + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return readl(chv_padreg(pctrl, pin, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) void __iomem *reg = chv_padreg(pctrl, pin, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Write and simple read back to confirm the bus transferring done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) writel(value, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static int chv_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return pctrl->soc->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return pctrl->soc->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) const unsigned int **pins, unsigned int *npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) *pins = pctrl->soc->groups[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) *npins = pctrl->soc->groups[group].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u32 ctrl0, ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) bool locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) locked = chv_pad_locked(pctrl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) seq_puts(s, "GPIO ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) mode >>= CHV_PADCTRL0_PMODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) seq_printf(s, "mode %d ", mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (locked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) seq_puts(s, " [LOCKED]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const struct pinctrl_ops chv_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .get_groups_count = chv_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .get_group_name = chv_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .get_group_pins = chv_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .pin_dbg_show = chv_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static int chv_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return pctrl->soc->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) unsigned int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return pctrl->soc->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static int chv_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned int * const ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) *groups = pctrl->soc->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) *ngroups = pctrl->soc->functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) unsigned int function, unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) const struct intel_pingroup *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) grp = &pctrl->soc->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Check first that the pad is not locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) for (i = 0; i < grp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (chv_pad_locked(pctrl, grp->pins[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) grp->pins[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) for (i = 0; i < grp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) int pin = grp->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) bool invert_oe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* Check if there is pin-specific config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (grp->modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mode = grp->modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mode = grp->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* Extract OE inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) invert_oe = mode & PINMODE_INVERT_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) mode &= ~PINMODE_INVERT_OE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) value = chv_readl(pctrl, pin, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Disable GPIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) value &= ~CHV_PADCTRL0_GPIOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Set to desired mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) value &= ~CHV_PADCTRL0_PMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) value |= mode << CHV_PADCTRL0_PMODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) chv_writel(pctrl, pin, CHV_PADCTRL0, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Update for invert_oe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (invert_oe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) chv_writel(pctrl, pin, CHV_PADCTRL1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) pin, mode, invert_oe ? "" : "not ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * One some devices the GPIO should output the inverted value from what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * device-drivers / ACPI code expects (inverted external buffer?). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * preserve this flag if the pin is already setup as GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) value = chv_readl(pctrl, offset, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (value & CHV_PADCTRL0_GPIOEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) value = chv_readl(pctrl, offset, CHV_PADCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) value &= ~invrxtx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) chv_writel(pctrl, offset, CHV_PADCTRL1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (chv_pad_locked(pctrl, offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) value = chv_readl(pctrl, offset, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (!(value & CHV_PADCTRL0_GPIOEN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Locked so cannot enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct intel_community_context *cctx = &pctrl->context.communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* Reset the interrupt mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (cctx->intr_lines[i] == offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) cctx->intr_lines[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* Disable interrupt generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) chv_gpio_clear_triggering(pctrl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) value = chv_readl(pctrl, offset, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) * If the pin is in HiZ mode (both TX and RX buffers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * disabled) we turn it to be input now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Switch to a GPIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) value |= CHV_PADCTRL0_GPIOEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) chv_writel(pctrl, offset, CHV_PADCTRL0, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (!chv_pad_locked(pctrl, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) chv_gpio_clear_triggering(pctrl, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) unsigned int offset, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u32 ctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static const struct pinmux_ops chv_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .get_functions_count = chv_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .get_function_name = chv_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .get_function_groups = chv_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .set_mux = chv_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .gpio_request_enable = chv_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .gpio_disable_free = chv_gpio_disable_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .gpio_set_direction = chv_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) u32 ctrl0, ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u16 arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u32 term;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (term)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) switch (term) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) case CHV_PADCTRL0_TERM_20K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) arg = 20000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) case CHV_PADCTRL0_TERM_5K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) arg = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) case CHV_PADCTRL0_TERM_1K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) arg = 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) switch (term) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) case CHV_PADCTRL0_TERM_20K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) arg = 20000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) case CHV_PADCTRL0_TERM_5K:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) arg = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (!(ctrl1 & CHV_PADCTRL1_ODEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) enum pin_config_param param, u32 arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) u32 ctrl0, pull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) case 1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* For 1k there is only pull up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) case 5000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) case 20000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) case 5000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) case 20000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ctrl0 |= pull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) u32 ctrl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ctrl1 |= CHV_PADCTRL1_ODEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ctrl1 &= ~CHV_PADCTRL1_ODEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) unsigned long *configs, unsigned int nconfigs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (chv_pad_locked(pctrl, pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) for (i = 0; i < nconfigs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ret = chv_config_set_pull(pctrl, pin, param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ret = chv_config_set_oden(pctrl, pin, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ret = chv_config_set_oden(pctrl, pin, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static int chv_config_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ret = chv_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ret = chv_config_get(pctldev, pins[0], config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static int chv_config_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) unsigned int group, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret = chv_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ret = chv_config_set(pctldev, pins[i], configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static const struct pinconf_ops chv_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .pin_config_set = chv_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .pin_config_get = chv_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .pin_config_group_get = chv_config_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .pin_config_group_set = chv_config_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static struct pinctrl_desc chv_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .pctlops = &chv_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .pmxops = &chv_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .confops = &chv_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) u32 ctrl0, cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) u32 ctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) u32 ctrl0, direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (direction == CHV_PADCTRL0_GPIOCFG_GPO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return pinctrl_gpio_direction_input(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) chv_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return pinctrl_gpio_direction_output(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static const struct gpio_chip chv_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .get_direction = chv_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .direction_input = chv_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .direction_output = chv_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .get = chv_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .set = chv_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static void chv_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) int pin = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) u32 intr_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) raw_spin_lock(&chv_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) intr_line &= CHV_PADCTRL0_INTSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) raw_spin_unlock(&chv_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) int pin = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) u32 value, intr_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) intr_line = chv_readl(pctrl, pin, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) intr_line &= CHV_PADCTRL0_INTSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) value = chv_pctrl_readl(pctrl, CHV_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) value &= ~BIT(intr_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) value |= BIT(intr_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) chv_pctrl_writel(pctrl, CHV_INTMASK, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static void chv_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) chv_gpio_irq_mask_unmask(d, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static void chv_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) chv_gpio_irq_mask_unmask(d, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static unsigned chv_gpio_irq_startup(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * Check if the interrupt has been requested with 0 as triggering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * type. In that case it is assumed that the current values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * programmed to the hardware are used (e.g BIOS configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * defaults).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * In that case ->irq_set_type() will never be called so we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * read back the values from hardware now, set correct flow handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * and update mappings before the interrupt is being used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct intel_community_context *cctx = &pctrl->context.communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) unsigned int pin = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) irq_flow_handler_t handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) u32 intsel, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) intsel = chv_readl(pctrl, pin, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) intsel &= CHV_PADCTRL0_INTSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) value = chv_readl(pctrl, pin, CHV_PADCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (!cctx->intr_lines[intsel]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) irq_set_handler_locked(d, handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) cctx->intr_lines[intsel] = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) chv_gpio_irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct intel_community_context *cctx = &pctrl->context.communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) unsigned int pin = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * Pins which can be used as shared interrupt are configured in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * BIOS. Driver trusts BIOS configurations and assigns different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * handler according to the irq type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) * Driver needs to save the mapping between each pin and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * its interrupt line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) * 1. If the pin cfg is locked in BIOS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) * Trust BIOS has programmed IntWakeCfg bits correctly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * driver just needs to save the mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * 2. If the pin cfg is not locked in BIOS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * Driver programs the IntWakeCfg bits and save the mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (!chv_pad_locked(pctrl, pin)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) value = chv_readl(pctrl, pin, CHV_PADCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) value &= ~CHV_PADCTRL1_INVRXTX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (type & IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) else if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) value |= CHV_PADCTRL1_INTWAKECFG_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) else if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) } else if (type & IRQ_TYPE_LEVEL_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (type & IRQ_TYPE_LEVEL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) value |= CHV_PADCTRL1_INVRXTX_RXDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) chv_writel(pctrl, pin, CHV_PADCTRL1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) value = chv_readl(pctrl, pin, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) value &= CHV_PADCTRL0_INTSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) value >>= CHV_PADCTRL0_INTSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) cctx->intr_lines[value] = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) else if (type & IRQ_TYPE_LEVEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static void chv_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) const struct intel_community *community = &pctrl->communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct intel_community_context *cctx = &pctrl->context.communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) u32 intr_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) pending = chv_pctrl_readl(pctrl, CHV_INTSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) for_each_set_bit(intr_line, &pending, community->nirqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) unsigned int irq, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) offset = cctx->intr_lines[intr_line];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) irq = irq_find_mapping(gc->irq.domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * tables. Since we leave GPIOs that are not capable of generating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) * interrupts out of the irqdomain the numbering will be different and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) * cause devices using the hardcoded IRQ numbers fail. In order not to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) * break such machines we will only mask pins from irqdomain if the machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) * is not listed below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static const struct dmi_system_id chv_no_valid_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .ident = "Intel_Strago based Chromebooks (All models)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .ident = "HP Chromebook 11 G5 (Setzer)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) DMI_MATCH(DMI_SYS_VENDOR, "HP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .ident = "Acer Chromebook R11 (Cyan)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .ident = "Samsung Chromebook 3 (Celes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) DMI_MATCH(DMI_PRODUCT_NAME, "Celes"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static void chv_init_irq_valid_mask(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) unsigned long *valid_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) unsigned int ngpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) const struct intel_community *community = &pctrl->communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) for (i = 0; i < pctrl->soc->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) const struct pinctrl_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) u32 intsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) desc = &pctrl->soc->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) intsel &= CHV_PADCTRL0_INTSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (intsel >= community->nirqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) clear_bit(desc->number, valid_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static int chv_gpio_irq_init_hw(struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) const struct intel_community *community = &pctrl->communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) * The same set of machines in chv_no_valid_mask[] have incorrectly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) * configured GPIOs that generate spurious interrupts so we use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * this same list to apply another quirk for them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (!pctrl->chip.irq.init_valid_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) * Mask all interrupts the community is able to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) * but leave the ones that can only generate GPEs unmasked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /* Clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static int chv_gpio_add_pin_ranges(struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) const struct intel_community *community = &pctrl->communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) const struct intel_padgroup *gpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) for (i = 0; i < community->ngpps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) gpp = &community->gpps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) gpp->base, gpp->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) gpp->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) dev_err(pctrl->dev, "failed to add GPIO pin range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) const struct intel_community *community = &pctrl->communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) const struct intel_padgroup *gpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) struct gpio_chip *chip = &pctrl->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) int ret, i, irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) *chip = chv_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) chip->label = dev_name(pctrl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) chip->add_pin_ranges = chv_gpio_add_pin_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) chip->parent = pctrl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) pctrl->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) pctrl->irqchip.name = "chv-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) pctrl->irqchip.irq_startup = chv_gpio_irq_startup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) pctrl->irqchip.irq_ack = chv_gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) pctrl->irqchip.irq_mask = chv_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) pctrl->irqchip.irq_unmask = chv_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) pctrl->irqchip.irq_set_type = chv_gpio_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) pctrl->irqchip.flags = IRQCHIP_SKIP_SET_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) chip->irq.chip = &pctrl->irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) chip->irq.init_hw = chv_gpio_irq_init_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) chip->irq.parent_handler = chv_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) chip->irq.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) chip->irq.parents = &pctrl->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) chip->irq.default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) chip->irq.handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (need_valid_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) chip->irq.init_valid_mask = chv_init_irq_valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) pctrl->soc->npins, NUMA_NO_NODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (irq_base < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) return irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) dev_err(pctrl->dev, "Failed to register gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (!need_valid_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) for (i = 0; i < community->ngpps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) gpp = &community->gpps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) irq_domain_associate_many(chip->irq.domain, irq_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) gpp->base, gpp->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) irq_base += gpp->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static acpi_status chv_pinctrl_mmio_access_handler(u32 function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) acpi_physical_address address, u32 bits, u64 *value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) void *handler_context, void *region_context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) struct intel_pinctrl *pctrl = region_context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) acpi_status ret = AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (function == ACPI_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) chv_pctrl_writel(pctrl, address, *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) else if (function == ACPI_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) *value = chv_pctrl_readl(pctrl, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) ret = AE_BAD_PARAMETER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static int chv_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) const struct intel_pinctrl_soc_data *soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct intel_community *community;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) struct acpi_device *adev = ACPI_COMPANION(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct intel_pinctrl *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) soc_data = intel_pinctrl_get_soc_data(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (IS_ERR(soc_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return PTR_ERR(soc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) if (!pctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) pctrl->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) pctrl->soc = soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) pctrl->ncommunities = pctrl->soc->ncommunities;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) pctrl->communities = devm_kmemdup(dev, pctrl->soc->communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) pctrl->ncommunities * sizeof(*pctrl->communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (!pctrl->communities)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) community = &pctrl->communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) community->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (IS_ERR(community->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) return PTR_ERR(community->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) sizeof(*pctrl->context.pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (!pctrl->context.pads)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) sizeof(*pctrl->context.communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (!pctrl->context.communities)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) pctrl->pctldesc = chv_pinctrl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) pctrl->pctldesc.name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) pctrl->pctldesc.pins = pctrl->soc->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) pctrl->pctldesc.npins = pctrl->soc->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) if (IS_ERR(pctrl->pctldev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) dev_err(dev, "failed to register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) return PTR_ERR(pctrl->pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ret = chv_gpio_probe(pctrl, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) status = acpi_install_address_space_handler(adev->handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) community->acpi_space_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) chv_pinctrl_mmio_access_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) NULL, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) if (ACPI_FAILURE(status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) dev_err(dev, "failed to install ACPI addr space handler\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) platform_set_drvdata(pdev, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static int chv_pinctrl_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) const struct intel_community *community = &pctrl->communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) community->acpi_space_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) chv_pinctrl_mmio_access_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static int chv_pinctrl_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) struct intel_community_context *cctx = &pctrl->context.communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) for (i = 0; i < pctrl->soc->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) const struct pinctrl_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) struct intel_pad_context *ctx = &pctrl->context.pads[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) desc = &pctrl->soc->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (chv_pad_locked(pctrl, desc->number))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) static int chv_pinctrl_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) struct intel_community_context *cctx = &pctrl->context.communities[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) raw_spin_lock_irqsave(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) * Mask all interrupts before restoring per-pin configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) * registers because we don't know in which state BIOS left them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) * upon exiting suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) for (i = 0; i < pctrl->soc->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) const struct pinctrl_pin_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) struct intel_pad_context *ctx = &pctrl->context.pads[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) desc = &pctrl->soc->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (chv_pad_locked(pctrl, desc->number))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /* Only restore if our saved state differs from the current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) val = chv_readl(pctrl, desc->number, CHV_PADCTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) val &= ~CHV_PADCTRL0_GPIORXSTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) if (ctx->padctrl0 != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) val = chv_readl(pctrl, desc->number, CHV_PADCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) if (ctx->padctrl1 != val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) desc->number, chv_readl(pctrl, desc->number, CHV_PADCTRL1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * Now that all pins are restored to known state, we can restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) * the interrupt mask register as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) raw_spin_unlock_irqrestore(&chv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static const struct dev_pm_ops chv_pinctrl_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) chv_pinctrl_resume_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) { "INT33FF", (kernel_ulong_t)chv_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static struct platform_driver chv_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .probe = chv_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .remove = chv_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .name = "cherryview-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .pm = &chv_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .acpi_match_table = chv_pinctrl_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) static int __init chv_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return platform_driver_register(&chv_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) subsys_initcall(chv_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) static void __exit chv_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) platform_driver_unregister(&chv_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) module_exit(chv_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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