^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Cedar Fork PCH pinctrl/GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pinctrl-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CDF_PAD_OWN 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CDF_PADCFGLOCK 0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CDF_HOSTSW_OWN 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CDF_GPI_IS 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CDF_GPI_IE 0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CDF_GPP(r, s, e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .reg_num = (r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .size = ((e) - (s) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CDF_COMMUNITY(b, s, e, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .barno = (b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .padown_offset = CDF_PAD_OWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .padcfglock_offset = CDF_PADCFGLOCK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .hostown_offset = CDF_HOSTSW_OWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .is_offset = CDF_GPI_IS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .ie_offset = CDF_GPI_IE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .pin_base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .npins = ((e) - (s) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .gpps = (g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .ngpps = ARRAY_SIZE(g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Cedar Fork PCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct pinctrl_pin_desc cdf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* WEST2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PINCTRL_PIN(0, "GBE_SDP_TIMESYNC0_S2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PINCTRL_PIN(1, "GBE_SDP_TIMESYNC1_S2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PINCTRL_PIN(2, "GBE_SDP_TIMESYNC2_S2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PINCTRL_PIN(3, "GBE_SDP_TIMESYNC3_S2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PINCTRL_PIN(4, "GBE0_I2C_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PINCTRL_PIN(5, "GBE0_I2C_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PINCTRL_PIN(6, "GBE1_I2C_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINCTRL_PIN(7, "GBE1_I2C_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PINCTRL_PIN(8, "GBE2_I2C_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINCTRL_PIN(9, "GBE2_I2C_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PINCTRL_PIN(10, "GBE3_I2C_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN(11, "GBE3_I2C_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN(12, "GBE0_LED0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN(13, "GBE0_LED1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN(14, "GBE0_LED2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN(15, "GBE1_LED0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN(16, "GBE1_LED1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINCTRL_PIN(17, "GBE1_LED2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN(18, "GBE2_LED0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN(19, "GBE2_LED1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN(20, "GBE2_LED2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN(21, "GBE3_LED0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN(22, "GBE3_LED1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(23, "GBE3_LED2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* WEST3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(24, "NCSI_RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(25, "NCSI_CLK_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINCTRL_PIN(26, "NCSI_RXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(27, "NCSI_CRS_DV"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINCTRL_PIN(28, "NCSI_ARB_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(29, "NCSI_TX_EN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PINCTRL_PIN(30, "NCSI_TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINCTRL_PIN(31, "NCSI_TXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINCTRL_PIN(32, "NCSI_ARB_OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINCTRL_PIN(33, "GBE_SMB_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(34, "GBE_SMB_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PINCTRL_PIN(35, "GBE_SMB_ALRT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINCTRL_PIN(36, "THERMTRIP_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(37, "PCHHOT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(38, "ERROR0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(39, "ERROR1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINCTRL_PIN(40, "ERROR2_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(41, "MSMI_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(42, "CATERR_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(43, "MEMTRIP_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(44, "UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(45, "UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(46, "GBE_UART_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(47, "GBE_UART_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* WEST01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(48, "GBE_GPIO13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(49, "AUX_PWR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(50, "UART0_RTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(51, "UART0_CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(52, "FAN_PWM_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(53, "FAN_PWM_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(54, "FAN_PWM_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(55, "FAN_PWM_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(56, "FAN_TACH_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(57, "FAN_TACH_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(58, "FAN_TACH_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(59, "FAN_TACH_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(60, "ME_SMB0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(61, "ME_SMB0_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(62, "ME_SMB0_ALRT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(63, "ME_SMB1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(64, "ME_SMB1_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(65, "ME_SMB1_ALRT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(66, "ME_SMB2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(67, "ME_SMB2_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(68, "ME_SMB2_ALRT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(69, "GBE_MNG_I2C_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(70, "GBE_MNG_I2C_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* WEST5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(71, "IE_UART_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(72, "IE_UART_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(73, "VPP_SMB_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(74, "VPP_SMB_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(75, "VPP_SMB_ALRT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(76, "PCIE_CLKREQ0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(77, "PCIE_CLKREQ1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(78, "PCIE_CLKREQ2_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(79, "PCIE_CLKREQ3_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(80, "PCIE_CLKREQ4_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(81, "PCIE_CLKREQ5_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(82, "PCIE_CLKREQ6_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(83, "PCIE_CLKREQ7_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(84, "PCIE_CLKREQ8_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(85, "PCIE_CLKREQ9_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(86, "FLEX_CLK_SE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(87, "FLEX_CLK_SE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(88, "FLEX_CLK1_50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(89, "FLEX_CLK2_50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(90, "FLEX_CLK_125"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* WESTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(91, "TCK_PCH"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(92, "JTAGX_PCH"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(93, "TRST_N_PCH"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(94, "TMS_PCH"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(95, "TDI_PCH"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(96, "TDO_PCH"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* WESTC_DFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(97, "CX_PRDY_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(98, "CX_PREQ_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(99, "CPU_FBREAK_OUT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(100, "TRIGGER0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(101, "TRIGGER1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* WESTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(102, "DBG_PTI_CLK0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(103, "DBG_PTI_CLK3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(104, "DBG_PTI_DATA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(105, "DBG_PTI_DATA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(106, "DBG_PTI_DATA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(107, "DBG_PTI_DATA3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(108, "DBG_PTI_DATA4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(109, "DBG_PTI_DATA5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(110, "DBG_PTI_DATA6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(111, "DBG_PTI_DATA7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* WESTB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(112, "DBG_PTI_DATA8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(113, "DBG_PTI_DATA9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(114, "DBG_PTI_DATA10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(115, "DBG_PTI_DATA11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(116, "DBG_PTI_DATA12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(117, "DBG_PTI_DATA13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(118, "DBG_PTI_DATA14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(119, "DBG_PTI_DATA15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(120, "DBG_SPARE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(121, "DBG_SPARE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(122, "DBG_SPARE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(123, "DBG_SPARE3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* WESTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(124, "CPU_PWR_GOOD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(125, "PLTRST_CPU_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(126, "NAC_RESET_NAC_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(127, "PCH_SBLINK_RX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(128, "PCH_SBLINK_TX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(129, "PMSYNC_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(130, "CPU_ERR0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(131, "CPU_ERR1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(132, "CPU_ERR2_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(133, "CPU_THERMTRIP_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(134, "CPU_MSMI_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(135, "CPU_CATERR_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(136, "CPU_MEMTRIP_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(137, "NAC_GR_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(138, "NAC_XTAL_VALID"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(139, "NAC_WAKE_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(140, "NAC_SBLINK_CLK_S2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(141, "NAC_SBLINK_N2S"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(142, "NAC_SBLINK_S2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(143, "NAC_SBLINK_CLK_N2S"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* WESTD_PECI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(144, "ME_PECI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* WESTF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(145, "NAC_RMII_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(146, "NAC_RGMII_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(147, "NAC_GBE_SMB_CLK_TX_N2S"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(148, "NAC_GBE_SMB_DATA_TX_N2S"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(149, "NAC_SPARE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(150, "NAC_INIT_SX_WAKE_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(151, "NAC_GBE_GPIO0_S2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(152, "NAC_GBE_GPIO1_S2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(153, "NAC_GBE_GPIO2_S2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(154, "NAC_GBE_GPIO3_S2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(155, "NAC_NCSI_RXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(156, "NAC_NCSI_CLK_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(157, "NAC_NCSI_RXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(158, "NAC_NCSI_CRS_DV"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(159, "NAC_NCSI_ARB_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(160, "NAC_NCSI_TX_EN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(161, "NAC_NCSI_TXD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(162, "NAC_NCSI_TXD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(163, "NAC_NCSI_ARB_OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(164, "NAC_NCSI_OE_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(165, "NAC_GBE_SMB_CLK_RX_S2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(166, "NAC_GBE_SMB_DATA_RX_S2N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(167, "NAC_GBE_SMB_ALRT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* EAST2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(168, "USB_OC0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(169, "GBE_GPIO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(170, "GBE_GPIO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(171, "GBE_GPIO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(172, "GBE_GPIO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(173, "GBE_GPIO4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(174, "GBE_GPIO5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(175, "GBE_GPIO6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(176, "GBE_GPIO7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(177, "SPI_TPM_CS_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(178, "GBE_GPIO9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(179, "GBE_GPIO10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(180, "GBE_GPIO11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(181, "GBE_GPIO12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(182, "PECI_SMB_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(183, "SATA0_LED_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(184, "SATA1_LED_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(185, "SATA_PDETECT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(186, "SATA_PDETECT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(187, "SATA0_SDOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(188, "SATA1_SDOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(189, "SATA2_LED_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(190, "SATA_PDETECT2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(191, "SATA2_SDOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* EAST3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(192, "ESPI_IO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(193, "ESPI_IO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(194, "ESPI_IO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(195, "ESPI_IO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(196, "ESPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(197, "ESPI_RST_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(198, "ESPI_CS0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(199, "ESPI_ALRT0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(200, "ESPI_CS1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(201, "ESPI_ALRT1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(202, "ESPI_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* EAST0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(203, "SPI_CS0_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(204, "SPI_CS1_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(205, "SPI_MOSI_IO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(206, "SPI_MISO_IO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(207, "SPI_IO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(208, "SPI_IO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(209, "SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(210, "SPI_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(211, "SUSPWRDNACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(212, "PMU_SUSCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(213, "ADR_COMPLETE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(214, "ADR_TRIGGER_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(215, "PMU_SLP_S45_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(216, "PMU_SLP_S3_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(217, "PMU_WAKE_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(218, "PMU_PWRBTN_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(219, "PMU_RESETBUTTON_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(220, "PMU_PLTRST_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(221, "SUS_STAT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(222, "PMU_I2C_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(223, "PMU_I2C_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(224, "PECI_SMB_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(225, "PECI_SMB_ALRT_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* EMMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(226, "EMMC_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(227, "EMMC_STROBE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(228, "EMMC_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(229, "EMMC_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(230, "EMMC_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(231, "EMMC_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(232, "EMMC_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(233, "EMMC_D4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(234, "EMMC_D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(235, "EMMC_D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(236, "EMMC_D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct intel_padgroup cdf_community0_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) CDF_GPP(0, 0, 23), /* WEST2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CDF_GPP(1, 24, 47), /* WEST3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) CDF_GPP(2, 48, 70), /* WEST01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) CDF_GPP(3, 71, 90), /* WEST5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) CDF_GPP(4, 91, 96), /* WESTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) CDF_GPP(5, 97, 101), /* WESTC_DFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CDF_GPP(6, 102, 111), /* WESTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) CDF_GPP(7, 112, 123), /* WESTB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) CDF_GPP(8, 124, 143), /* WESTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) CDF_GPP(9, 144, 144), /* WESTD_PECI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) CDF_GPP(10, 145, 167), /* WESTF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct intel_padgroup cdf_community1_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) CDF_GPP(0, 168, 191), /* EAST2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) CDF_GPP(1, 192, 202), /* EAST3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) CDF_GPP(2, 203, 225), /* EAST0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) CDF_GPP(3, 226, 236), /* EMMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct intel_community cdf_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) CDF_COMMUNITY(0, 0, 167, cdf_community0_gpps), /* West */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) CDF_COMMUNITY(1, 168, 236, cdf_community1_gpps), /* East */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct intel_pinctrl_soc_data cdf_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .pins = cdf_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .npins = ARRAY_SIZE(cdf_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .communities = cdf_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .ncommunities = ARRAY_SIZE(cdf_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static INTEL_PINCTRL_PM_OPS(cdf_pinctrl_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct acpi_device_id cdf_pinctrl_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { "INTC3001", (kernel_ulong_t)&cdf_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MODULE_DEVICE_TABLE(acpi, cdf_pinctrl_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct platform_driver cdf_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .probe = intel_pinctrl_probe_by_hid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .name = "cedarfork-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .acpi_match_table = cdf_pinctrl_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .pm = &cdf_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int __init cdf_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return platform_driver_register(&cdf_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) subsys_initcall(cdf_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void __exit cdf_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) platform_driver_unregister(&cdf_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) module_exit(cdf_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_DESCRIPTION("Intel Cedar Fork PCH pinctrl/GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags