^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Cannon Lake PCH pinctrl/GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017, Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CNL_PAD_OWN 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CNL_PADCFGLOCK 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CNL_LP_HOSTSW_OWN 0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CNL_H_HOSTSW_OWN 0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CNL_GPI_IS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CNL_GPI_IE 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CNL_GPP(r, s, e, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .reg_num = (r), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .size = ((e) - (s) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .gpio_base = (g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CNL_COMMUNITY(b, s, e, ho, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .barno = (b), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .padown_offset = CNL_PAD_OWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .padcfglock_offset = CNL_PADCFGLOCK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .hostown_offset = (ho), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .is_offset = CNL_GPI_IS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .ie_offset = CNL_GPI_IE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .pin_base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .npins = ((e) - (s) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .gpps = (g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .ngpps = ARRAY_SIZE(g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CNL_LP_COMMUNITY(b, s, e, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CNL_H_COMMUNITY(b, s, e, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Cannon Lake-H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static const struct pinctrl_pin_desc cnlh_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINCTRL_PIN(0, "RCINB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PINCTRL_PIN(1, "LAD_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN(2, "LAD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN(3, "LAD_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN(4, "LAD_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN(5, "LFRAMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN(6, "SERIRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN(7, "PIRQAB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINCTRL_PIN(8, "CLKRUNB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN(9, "CLKOUT_LPC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN(10, "CLKOUT_LPC_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN(11, "PMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN(12, "BM_BUSYB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(14, "SUS_STATB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINCTRL_PIN(15, "SUSACKB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(16, "CLKOUT_48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINCTRL_PIN(18, "ISH_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(19, "ISH_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINCTRL_PIN(20, "ISH_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(21, "ISH_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PINCTRL_PIN(22, "ISH_GP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINCTRL_PIN(23, "ISH_GP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(25, "GSPI0_CS1B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PINCTRL_PIN(26, "GSPI1_CS1B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINCTRL_PIN(27, "VRALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(28, "CPU_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(29, "CPU_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(30, "SRCCLKREQB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINCTRL_PIN(31, "SRCCLKREQB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(32, "SRCCLKREQB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(33, "SRCCLKREQB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(34, "SRCCLKREQB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(35, "SRCCLKREQB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(36, "SSP_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(37, "SLP_S0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(38, "PLTRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(39, "SPKR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(40, "GSPI0_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(41, "GSPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(42, "GSPI0_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(43, "GSPI0_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(44, "GSPI1_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(45, "GSPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(46, "GSPI1_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(47, "GSPI1_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(48, "SML1ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(51, "SMBCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(52, "SMBDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(53, "SMBALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(54, "SML0CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(55, "SML0DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(56, "SML0ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(57, "SML1CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(58, "SML1DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(59, "UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(60, "UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(61, "UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(62, "UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(63, "UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(64, "UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(65, "UART1_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(66, "UART1_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(67, "I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(68, "I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(69, "I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(70, "I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(71, "UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(72, "UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(73, "UART2_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(74, "UART2_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(75, "SPI1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(76, "SPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(77, "SPI1_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(78, "SPI1_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(79, "ISH_I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(80, "SSP2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(81, "SSP2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(82, "SSP2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(83, "SSP2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(84, "ISH_SPI_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(85, "ISH_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(86, "ISH_SPI_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(87, "ISH_SPI_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(88, "ISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(89, "ISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(90, "ISH_UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(91, "ISH_UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(92, "DMIC_CLK_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(93, "DMIC_DATA_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(94, "DMIC_CLK_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(95, "DMIC_DATA_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(96, "SPI1_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(97, "SPI1_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(98, "ISH_I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(99, "SD3_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(100, "SD3_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(101, "SD3_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(102, "SD3_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(103, "SD3_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(104, "SD3_CDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(105, "SD3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(106, "SD3_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* AZA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(107, "HDA_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(108, "HDA_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(109, "HDA_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(110, "HDA_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(111, "HDA_SDI_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(112, "HDA_SDI_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(113, "SSP1_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(114, "SSP1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* vGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(115, "CNV_BTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(116, "CNV_GNEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(117, "CNV_WFEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(118, "CNV_WCEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(119, "CNV_BT_HOST_WAKEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(120, "vCNV_GNSS_HOST_WAKEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(121, "vSD3_CD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(122, "CNV_BT_IF_SELECT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(123, "vCNV_BT_UART_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(124, "vCNV_BT_UART_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(125, "vCNV_BT_UART_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(126, "vCNV_BT_UART_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(127, "vCNV_MFUART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(128, "vCNV_MFUART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(129, "vCNV_MFUART1_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(130, "vCNV_MFUART1_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(131, "vCNV_GNSS_UART_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(132, "vCNV_GNSS_UART_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(133, "vCNV_GNSS_UART_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(134, "vCNV_GNSS_UART_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(135, "vUART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(136, "vUART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(137, "vUART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(138, "vUART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(139, "vISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(140, "vISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(141, "vISH_UART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(142, "vISH_UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(143, "vISH_UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(144, "vISH_UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(145, "vISH_UART1_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(146, "vISH_UART1_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(147, "vCNV_BT_I2S_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(148, "vCNV_BT_I2S_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(149, "vCNV_BT_I2S_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(150, "vCNV_BT_I2S_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(151, "vSSP2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(152, "vSSP2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(153, "vSSP2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(154, "vSSP2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* GPP_K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(155, "FAN_TACH_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(156, "FAN_TACH_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(157, "FAN_TACH_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(158, "FAN_TACH_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(159, "FAN_TACH_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(160, "FAN_TACH_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(161, "FAN_TACH_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(162, "FAN_TACH_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(163, "FAN_PWM_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(164, "FAN_PWM_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(165, "FAN_PWM_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(166, "FAN_PWM_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(167, "GSXDOUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(168, "GSXSLOAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(169, "GSXDIN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(170, "GSXSRESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(171, "GSXCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(172, "ADR_COMPLETE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(173, "NMIB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(174, "SMIB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(175, "CORE_VID_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(176, "CORE_VID_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(177, "IMGCLKOUT_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(178, "IMGCLKOUT_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(179, "SRCCLKREQB_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(180, "SRCCLKREQB_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(181, "SRCCLKREQB_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(182, "SRCCLKREQB_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(183, "SRCCLKREQB_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(184, "SRCCLKREQB_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(185, "SRCCLKREQB_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(186, "SRCCLKREQB_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(187, "SRCCLKREQB_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(188, "SRCCLKREQB_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(189, "SML2CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(190, "SML2DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(191, "SML2ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(192, "SML3CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(193, "SML3DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(194, "SML3ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(195, "SML4CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(196, "SML4DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(197, "SML4ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(198, "ISH_I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(199, "ISH_I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(200, "ISH_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(201, "ISH_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(202, "TIME_SYNC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(203, "SATAXPCIE_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(204, "SATAXPCIE_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(205, "SATAXPCIE_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(206, "CPU_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(207, "SATA_DEVSLP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(208, "SATA_DEVSLP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(209, "SATA_DEVSLP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(210, "CPU_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(211, "SATA_LEDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(212, "USB2_OCB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(213, "USB2_OCB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(214, "USB2_OCB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(215, "USB2_OCB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(216, "SATAXPCIE_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(217, "SATAXPCIE_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(218, "SATAXPCIE_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(219, "SATAXPCIE_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(220, "SATAXPCIE_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(221, "SATA_DEVSLP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(222, "SATA_DEVSLP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(223, "SATA_DEVSLP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(224, "SATA_DEVSLP_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(225, "SATA_DEVSLP_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(226, "SATA_SCLOCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(227, "SATA_SLOAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(228, "SATA_SDATAOUT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(229, "SATA_SDATAOUT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(230, "EXT_PWR_GATEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(231, "USB2_OCB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(232, "USB2_OCB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(233, "USB2_OCB_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(234, "USB2_OCB_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(235, "L_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(236, "L_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(237, "L_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(238, "DDPF_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(239, "DDPF_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(240, "SPI0_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(241, "SPI0_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(242, "SPI0_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(243, "SPI0_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(244, "SPI0_TPM_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(245, "SPI0_FLASH_0_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(246, "SPI0_FLASH_1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(247, "SPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(248, "SPI0_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(249, "HDACPU_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(250, "HDACPU_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(251, "HDACPU_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(252, "PM_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(253, "PECI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(254, "CPUPWRGD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(255, "THRMTRIPB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(256, "PLTRST_CPUB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(257, "PM_DOWN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(258, "TRIGGER_IN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(259, "TRIGGER_OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* JTAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(260, "JTAG_TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(261, "JTAGX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(262, "PRDYB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(263, "PREQB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(264, "CPU_TRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(265, "JTAG_TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(266, "JTAG_TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(267, "JTAG_TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(268, "ITP_PMODE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* GPP_I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(269, "DDSP_HPD_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(270, "DDSP_HPD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(271, "DDSP_HPD_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(272, "DDSP_HPD_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(273, "EDP_HPD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(274, "DDPB_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(275, "DDPB_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(276, "DDPC_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(277, "DDPC_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_PIN(278, "DDPD_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINCTRL_PIN(279, "DDPD_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINCTRL_PIN(280, "M2_SKT2_CFG_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINCTRL_PIN(281, "M2_SKT2_CFG_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PINCTRL_PIN(282, "M2_SKT2_CFG_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINCTRL_PIN(283, "M2_SKT2_CFG_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINCTRL_PIN(284, "SYS_PWROK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINCTRL_PIN(285, "SYS_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINCTRL_PIN(286, "MLK_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* GPP_J */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PINCTRL_PIN(287, "CNV_PA_BLANKING"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PINCTRL_PIN(288, "CNV_GNSS_FTA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINCTRL_PIN(289, "CNV_GNSS_SYSCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PINCTRL_PIN(290, "CNV_RF_RESET_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PINCTRL_PIN(291, "CNV_BRI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINCTRL_PIN(292, "CNV_BRI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINCTRL_PIN(293, "CNV_RGI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINCTRL_PIN(294, "CNV_RGI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PINCTRL_PIN(295, "CNV_MFUART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINCTRL_PIN(296, "CNV_MFUART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINCTRL_PIN(297, "CNV_MODEM_CLKREQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINCTRL_PIN(298, "A4WP_PRESENT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const struct intel_padgroup cnlh_community0_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) CNL_GPP(0, 0, 24, 0), /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) CNL_GPP(1, 25, 50, 32), /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct intel_padgroup cnlh_community1_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) CNL_GPP(0, 51, 74, 64), /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) CNL_GPP(1, 75, 98, 96), /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) CNL_GPP(2, 99, 106, 128), /* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct intel_padgroup cnlh_community3_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) CNL_GPP(0, 155, 178, 192), /* GPP_K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) CNL_GPP(1, 179, 202, 224), /* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) CNL_GPP(2, 203, 215, 256), /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) CNL_GPP(3, 216, 239, 288), /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const struct intel_padgroup cnlh_community4_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) CNL_GPP(2, 269, 286, 320), /* GPP_I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) CNL_GPP(3, 287, 298, 352), /* GPP_J */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const unsigned int cnlh_spi1_pins[] = { 44, 45, 46, 47 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const unsigned int cnlh_spi2_pins[] = { 84, 85, 86, 87 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const unsigned int cnlh_uart0_pins[] = { 59, 60, 61, 62 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const unsigned int cnlh_uart1_pins[] = { 63, 64, 65, 66 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const unsigned int cnlh_uart2_pins[] = { 71, 72, 73, 74 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const unsigned int cnlh_i2c0_pins[] = { 67, 68 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const unsigned int cnlh_i2c1_pins[] = { 69, 70 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const unsigned int cnlh_i2c2_pins[] = { 88, 89 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const unsigned int cnlh_i2c3_pins[] = { 79, 98 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const struct intel_pingroup cnlh_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PIN_GROUP("spi0_grp", cnlh_spi0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PIN_GROUP("spi1_grp", cnlh_spi1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PIN_GROUP("spi2_grp", cnlh_spi2_pins, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PIN_GROUP("uart0_grp", cnlh_uart0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PIN_GROUP("uart1_grp", cnlh_uart1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PIN_GROUP("uart2_grp", cnlh_uart2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PIN_GROUP("i2c0_grp", cnlh_i2c0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PIN_GROUP("i2c1_grp", cnlh_i2c1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PIN_GROUP("i2c2_grp", cnlh_i2c2_pins, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PIN_GROUP("i2c3_grp", cnlh_i2c3_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const char * const cnlh_spi0_groups[] = { "spi0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const char * const cnlh_spi1_groups[] = { "spi1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const char * const cnlh_spi2_groups[] = { "spi2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const char * const cnlh_uart0_groups[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const char * const cnlh_uart1_groups[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const char * const cnlh_uart2_groups[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const char * const cnlh_i2c0_groups[] = { "i2c0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const char * const cnlh_i2c1_groups[] = { "i2c1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const char * const cnlh_i2c2_groups[] = { "i2c2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static const char * const cnlh_i2c3_groups[] = { "i2c3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct intel_function cnlh_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) FUNCTION("spi0", cnlh_spi0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) FUNCTION("spi1", cnlh_spi1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) FUNCTION("spi2", cnlh_spi2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) FUNCTION("uart0", cnlh_uart0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) FUNCTION("uart1", cnlh_uart1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) FUNCTION("uart2", cnlh_uart2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) FUNCTION("i2c0", cnlh_i2c0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) FUNCTION("i2c1", cnlh_i2c1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) FUNCTION("i2c2", cnlh_i2c2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) FUNCTION("i2c3", cnlh_i2c3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct intel_community cnlh_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) CNL_H_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) CNL_H_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) CNL_H_COMMUNITY(2, 155, 248, cnlh_community3_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) CNL_H_COMMUNITY(3, 249, 298, cnlh_community4_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct intel_pinctrl_soc_data cnlh_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .pins = cnlh_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .npins = ARRAY_SIZE(cnlh_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .groups = cnlh_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .ngroups = ARRAY_SIZE(cnlh_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .functions = cnlh_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .nfunctions = ARRAY_SIZE(cnlh_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .communities = cnlh_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .ncommunities = ARRAY_SIZE(cnlh_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* Cannon Lake-LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const struct pinctrl_pin_desc cnllp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINCTRL_PIN(0, "RCINB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINCTRL_PIN(1, "LAD_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINCTRL_PIN(2, "LAD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINCTRL_PIN(3, "LAD_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINCTRL_PIN(4, "LAD_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINCTRL_PIN(5, "LFRAMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINCTRL_PIN(6, "SERIRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINCTRL_PIN(7, "PIRQAB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINCTRL_PIN(8, "CLKRUNB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINCTRL_PIN(9, "CLKOUT_LPC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINCTRL_PIN(10, "CLKOUT_LPC_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINCTRL_PIN(11, "PMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINCTRL_PIN(12, "BM_BUSYB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINCTRL_PIN(14, "SUS_STATB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINCTRL_PIN(15, "SUSACKB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINCTRL_PIN(16, "SD_1P8_SEL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINCTRL_PIN(17, "SD_PWR_EN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PINCTRL_PIN(18, "ISH_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PINCTRL_PIN(19, "ISH_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINCTRL_PIN(20, "ISH_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINCTRL_PIN(21, "ISH_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINCTRL_PIN(22, "ISH_GP_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINCTRL_PIN(23, "ISH_GP_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINCTRL_PIN(25, "CORE_VID_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINCTRL_PIN(26, "CORE_VID_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINCTRL_PIN(27, "VRALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINCTRL_PIN(28, "CPU_GP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINCTRL_PIN(29, "CPU_GP_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PINCTRL_PIN(30, "SRCCLKREQB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PINCTRL_PIN(31, "SRCCLKREQB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINCTRL_PIN(32, "SRCCLKREQB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PINCTRL_PIN(33, "SRCCLKREQB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINCTRL_PIN(34, "SRCCLKREQB_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINCTRL_PIN(35, "SRCCLKREQB_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PINCTRL_PIN(36, "EXT_PWR_GATEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PINCTRL_PIN(37, "SLP_S0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PINCTRL_PIN(38, "PLTRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PINCTRL_PIN(39, "SPKR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PINCTRL_PIN(40, "GSPI0_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PINCTRL_PIN(41, "GSPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PINCTRL_PIN(42, "GSPI0_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PINCTRL_PIN(43, "GSPI0_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PINCTRL_PIN(44, "GSPI1_CS0B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PINCTRL_PIN(45, "GSPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) PINCTRL_PIN(46, "GSPI1_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PINCTRL_PIN(47, "GSPI1_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PINCTRL_PIN(48, "SML1ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINCTRL_PIN(51, "SD3_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PINCTRL_PIN(52, "SD3_D0_SD4_RCLK_P"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PINCTRL_PIN(53, "SD3_D1_SD4_RCLK_N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PINCTRL_PIN(54, "SD3_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PINCTRL_PIN(55, "SD3_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PINCTRL_PIN(56, "SD3_CDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PINCTRL_PIN(57, "SD3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PINCTRL_PIN(58, "SD3_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINCTRL_PIN(59, "SPI0_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINCTRL_PIN(60, "SPI0_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINCTRL_PIN(61, "SPI0_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINCTRL_PIN(62, "SPI0_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINCTRL_PIN(63, "SPI0_TPM_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINCTRL_PIN(64, "SPI0_FLASH_0_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINCTRL_PIN(65, "SPI0_FLASH_1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINCTRL_PIN(66, "SPI0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINCTRL_PIN(67, "SPI0_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINCTRL_PIN(68, "SPI1_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINCTRL_PIN(69, "SPI1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINCTRL_PIN(70, "SPI1_MISO_IO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINCTRL_PIN(71, "SPI1_MOSI_IO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINCTRL_PIN(72, "IMGCLKOUT_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINCTRL_PIN(73, "ISH_I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINCTRL_PIN(74, "ISH_I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINCTRL_PIN(75, "ISH_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PINCTRL_PIN(76, "ISH_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PINCTRL_PIN(77, "ISH_SPI_CSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINCTRL_PIN(78, "ISH_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PINCTRL_PIN(79, "ISH_SPI_MISO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PINCTRL_PIN(80, "ISH_SPI_MOSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PINCTRL_PIN(81, "ISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINCTRL_PIN(82, "ISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINCTRL_PIN(83, "ISH_UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINCTRL_PIN(84, "ISH_UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PINCTRL_PIN(85, "DMIC_CLK_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PINCTRL_PIN(86, "DMIC_DATA_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINCTRL_PIN(87, "DMIC_CLK_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINCTRL_PIN(88, "DMIC_DATA_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PINCTRL_PIN(89, "SPI1_IO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINCTRL_PIN(90, "SPI1_IO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PINCTRL_PIN(91, "SSP_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINCTRL_PIN(92, "GSPI2_CLK_LOOPBK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINCTRL_PIN(93, "CNV_GNSS_PA_BLANKING"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINCTRL_PIN(94, "CNV_GNSS_FTA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINCTRL_PIN(95, "CNV_GNSS_SYSCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PINCTRL_PIN(96, "EMMC_HIP_MON"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINCTRL_PIN(97, "CNV_BRI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINCTRL_PIN(98, "CNV_BRI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINCTRL_PIN(99, "CNV_RGI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINCTRL_PIN(100, "CNV_RGI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINCTRL_PIN(101, "CNV_MFUART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINCTRL_PIN(102, "CNV_MFUART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINCTRL_PIN(103, "GPP_F_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINCTRL_PIN(104, "EMMC_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINCTRL_PIN(105, "EMMC_DATA_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINCTRL_PIN(106, "EMMC_DATA_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINCTRL_PIN(107, "EMMC_DATA_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINCTRL_PIN(108, "EMMC_DATA_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINCTRL_PIN(109, "EMMC_DATA_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINCTRL_PIN(110, "EMMC_DATA_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINCTRL_PIN(111, "EMMC_DATA_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINCTRL_PIN(112, "EMMC_DATA_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PINCTRL_PIN(113, "EMMC_RCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINCTRL_PIN(114, "EMMC_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINCTRL_PIN(115, "EMMC_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINCTRL_PIN(116, "A4WP_PRESENT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINCTRL_PIN(117, "SSP2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINCTRL_PIN(118, "SSP2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINCTRL_PIN(119, "SSP2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINCTRL_PIN(120, "SSP2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINCTRL_PIN(121, "I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINCTRL_PIN(122, "I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINCTRL_PIN(123, "I2C3_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINCTRL_PIN(124, "I2C3_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINCTRL_PIN(125, "I2C4_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PINCTRL_PIN(126, "I2C4_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINCTRL_PIN(127, "I2C5_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINCTRL_PIN(128, "I2C5_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINCTRL_PIN(129, "M2_SKT2_CFG_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINCTRL_PIN(130, "M2_SKT2_CFG_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINCTRL_PIN(131, "M2_SKT2_CFG_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINCTRL_PIN(132, "M2_SKT2_CFG_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINCTRL_PIN(133, "DDPF_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINCTRL_PIN(134, "DDPF_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINCTRL_PIN(135, "CPU_VCCIO_PWR_GATEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINCTRL_PIN(136, "TIMESYNC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINCTRL_PIN(137, "IMGCLKOUT_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PINCTRL_PIN(138, "GPPC_H_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINCTRL_PIN(139, "GPPC_H_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PINCTRL_PIN(140, "GPPC_H_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* vGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINCTRL_PIN(141, "CNV_BTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINCTRL_PIN(142, "CNV_GNEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PINCTRL_PIN(143, "CNV_WFEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINCTRL_PIN(144, "CNV_WCEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PINCTRL_PIN(155, "vCNV_GNSS_UART_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINCTRL_PIN(156, "vCNV_GNSS_UART_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINCTRL_PIN(157, "vCNV_GNSS_UART_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINCTRL_PIN(158, "vCNV_GNSS_UART_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PINCTRL_PIN(159, "vUART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINCTRL_PIN(160, "vUART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINCTRL_PIN(161, "vUART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINCTRL_PIN(162, "vUART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PINCTRL_PIN(163, "vISH_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINCTRL_PIN(164, "vISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINCTRL_PIN(165, "vISH_UART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PINCTRL_PIN(166, "vISH_UART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PINCTRL_PIN(167, "vISH_UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINCTRL_PIN(168, "vISH_UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINCTRL_PIN(169, "vISH_UART1_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINCTRL_PIN(170, "vISH_UART1_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PINCTRL_PIN(171, "vCNV_BT_I2S_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINCTRL_PIN(172, "vCNV_BT_I2S_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINCTRL_PIN(173, "vCNV_BT_I2S_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINCTRL_PIN(174, "vCNV_BT_I2S_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINCTRL_PIN(175, "vSSP2_SCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINCTRL_PIN(176, "vSSP2_SFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINCTRL_PIN(177, "vSSP2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINCTRL_PIN(178, "vSSP2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PINCTRL_PIN(179, "vCNV_GNSS_HOST_WAKEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINCTRL_PIN(180, "vSD3_CD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINCTRL_PIN(181, "SMBCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PINCTRL_PIN(182, "SMBDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINCTRL_PIN(183, "SMBALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINCTRL_PIN(184, "SML0CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PINCTRL_PIN(185, "SML0DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINCTRL_PIN(186, "SML0ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PINCTRL_PIN(187, "SML1CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINCTRL_PIN(188, "SML1DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINCTRL_PIN(189, "UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINCTRL_PIN(190, "UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PINCTRL_PIN(191, "UART0_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINCTRL_PIN(192, "UART0_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINCTRL_PIN(193, "UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PINCTRL_PIN(194, "UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINCTRL_PIN(195, "UART1_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINCTRL_PIN(196, "UART1_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PINCTRL_PIN(197, "I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINCTRL_PIN(198, "I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINCTRL_PIN(199, "I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINCTRL_PIN(200, "I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PINCTRL_PIN(201, "UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINCTRL_PIN(202, "UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINCTRL_PIN(203, "UART2_RTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PINCTRL_PIN(204, "UART2_CTSB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINCTRL_PIN(205, "SATAXPCIE_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINCTRL_PIN(206, "SATAXPCIE_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINCTRL_PIN(207, "SATAXPCIE_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINCTRL_PIN(208, "CPU_GP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINCTRL_PIN(209, "SATA_DEVSLP_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PINCTRL_PIN(210, "SATA_DEVSLP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINCTRL_PIN(211, "SATA_DEVSLP_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINCTRL_PIN(212, "CPU_GP_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINCTRL_PIN(213, "SATA_LEDB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINCTRL_PIN(214, "USB2_OCB_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PINCTRL_PIN(215, "USB2_OCB_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PINCTRL_PIN(216, "USB2_OCB_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINCTRL_PIN(217, "USB2_OCB_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINCTRL_PIN(218, "DDSP_HPD_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINCTRL_PIN(219, "DDSP_HPD_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINCTRL_PIN(220, "DDSP_HPD_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PINCTRL_PIN(221, "DDSP_HPD_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINCTRL_PIN(222, "EDP_HPD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINCTRL_PIN(223, "DDPB_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINCTRL_PIN(224, "DDPB_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINCTRL_PIN(225, "DDPC_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PINCTRL_PIN(226, "DDPC_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINCTRL_PIN(227, "DDPD_CTRLCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PINCTRL_PIN(228, "DDPD_CTRLDATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* JTAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINCTRL_PIN(229, "JTAG_TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PINCTRL_PIN(230, "JTAGX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PINCTRL_PIN(231, "PRDYB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINCTRL_PIN(232, "PREQB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINCTRL_PIN(233, "CPU_TRSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINCTRL_PIN(234, "JTAG_TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINCTRL_PIN(235, "JTAG_TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINCTRL_PIN(236, "JTAG_TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PINCTRL_PIN(237, "ITP_PMODE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* HVCMOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINCTRL_PIN(238, "L_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PINCTRL_PIN(239, "L_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINCTRL_PIN(240, "L_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINCTRL_PIN(241, "SYS_PWROK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PINCTRL_PIN(242, "SYS_RESETB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PINCTRL_PIN(243, "MLK_RSTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const unsigned int cnllp_spi0_pins[] = { 40, 41, 42, 43, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static const unsigned int cnllp_spi0_modes[] = { 1, 1, 1, 1, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const unsigned int cnllp_spi1_pins[] = { 44, 45, 46, 47, 11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const unsigned int cnllp_spi1_modes[] = { 1, 1, 1, 1, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static const unsigned int cnllp_spi2_pins[] = { 77, 78, 79, 80, 83 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const unsigned int cnllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const unsigned int cnllp_i2c0_pins[] = { 197, 198 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const unsigned int cnllp_i2c1_pins[] = { 199, 200 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const unsigned int cnllp_i2c2_pins[] = { 121, 122 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const unsigned int cnllp_i2c3_pins[] = { 123, 124 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static const unsigned int cnllp_i2c4_pins[] = { 125, 126 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const unsigned int cnllp_i2c5_pins[] = { 127, 128 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static const unsigned int cnllp_uart0_pins[] = { 189, 190, 191, 192 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const unsigned int cnllp_uart1_pins[] = { 193, 194, 195, 196 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static const unsigned int cnllp_uart2_pins[] = { 201, 202, 203, 204 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static const struct intel_pingroup cnllp_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PIN_GROUP("spi0_grp", cnllp_spi0_pins, cnllp_spi0_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PIN_GROUP("spi1_grp", cnllp_spi1_pins, cnllp_spi1_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PIN_GROUP("spi2_grp", cnllp_spi2_pins, cnllp_spi2_modes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PIN_GROUP("i2c0_grp", cnllp_i2c0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PIN_GROUP("i2c1_grp", cnllp_i2c1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PIN_GROUP("i2c2_grp", cnllp_i2c2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PIN_GROUP("i2c3_grp", cnllp_i2c3_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PIN_GROUP("i2c4_grp", cnllp_i2c4_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PIN_GROUP("i2c5_grp", cnllp_i2c5_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) PIN_GROUP("uart0_grp", cnllp_uart0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) PIN_GROUP("uart1_grp", cnllp_uart1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PIN_GROUP("uart2_grp", cnllp_uart2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const char * const cnllp_spi0_groups[] = { "spi0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static const char * const cnllp_spi1_groups[] = { "spi1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const char * const cnllp_spi2_groups[] = { "spi2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static const char * const cnllp_i2c0_groups[] = { "i2c0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static const char * const cnllp_i2c1_groups[] = { "i2c1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static const char * const cnllp_i2c2_groups[] = { "i2c2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const char * const cnllp_i2c3_groups[] = { "i2c3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static const char * const cnllp_i2c4_groups[] = { "i2c4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static const char * const cnllp_i2c5_groups[] = { "i2c5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static const char * const cnllp_uart0_groups[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const char * const cnllp_uart1_groups[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static const char * const cnllp_uart2_groups[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const struct intel_function cnllp_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) FUNCTION("spi0", cnllp_spi0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) FUNCTION("spi1", cnllp_spi1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) FUNCTION("spi2", cnllp_spi2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) FUNCTION("i2c0", cnllp_i2c0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) FUNCTION("i2c1", cnllp_i2c1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) FUNCTION("i2c2", cnllp_i2c2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) FUNCTION("i2c3", cnllp_i2c3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) FUNCTION("i2c4", cnllp_i2c4_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) FUNCTION("i2c5", cnllp_i2c5_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) FUNCTION("uart0", cnllp_uart0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) FUNCTION("uart1", cnllp_uart1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) FUNCTION("uart2", cnllp_uart2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const struct intel_padgroup cnllp_community0_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) CNL_GPP(0, 0, 24, 0), /* GPP_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) CNL_GPP(1, 25, 50, 32), /* GPP_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) CNL_GPP(2, 51, 58, 64), /* GPP_G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static const struct intel_padgroup cnllp_community1_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) CNL_GPP(0, 68, 92, 96), /* GPP_D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) CNL_GPP(1, 93, 116, 128), /* GPP_F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) CNL_GPP(2, 117, 140, 160), /* GPP_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) CNL_GPP(3, 141, 172, 192), /* vGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) CNL_GPP(4, 173, 180, 224), /* vGPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static const struct intel_padgroup cnllp_community4_gpps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) CNL_GPP(0, 181, 204, 256), /* GPP_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) CNL_GPP(1, 205, 228, 288), /* GPP_E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const struct intel_community cnllp_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) CNL_LP_COMMUNITY(0, 0, 67, cnllp_community0_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) CNL_LP_COMMUNITY(1, 68, 180, cnllp_community1_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) CNL_LP_COMMUNITY(2, 181, 243, cnllp_community4_gpps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static const struct intel_pinctrl_soc_data cnllp_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .pins = cnllp_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .npins = ARRAY_SIZE(cnllp_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .groups = cnllp_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .ngroups = ARRAY_SIZE(cnllp_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .functions = cnllp_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .nfunctions = ARRAY_SIZE(cnllp_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .communities = cnllp_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .ncommunities = ARRAY_SIZE(cnllp_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) { "INT3450", (kernel_ulong_t)&cnlh_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) { "INT34BB", (kernel_ulong_t)&cnllp_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) MODULE_DEVICE_TABLE(acpi, cnl_pinctrl_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static INTEL_PINCTRL_PM_OPS(cnl_pinctrl_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static struct platform_driver cnl_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .probe = intel_pinctrl_probe_by_hid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .name = "cannonlake-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .acpi_match_table = cnl_pinctrl_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .pm = &cnl_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) module_platform_driver(cnl_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) MODULE_DESCRIPTION("Intel Cannon Lake PCH pinctrl/GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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