^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel Broxton SoC pinctrl/GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015, 2016 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pinctrl-intel.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BXT_PAD_OWN 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BXT_PADCFGLOCK 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BXT_HOSTSW_OWN 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BXT_GPI_IS 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BXT_GPI_IE 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BXT_COMMUNITY(s, e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .padown_offset = BXT_PAD_OWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .padcfglock_offset = BXT_PADCFGLOCK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .hostown_offset = BXT_HOSTSW_OWN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .is_offset = BXT_GPI_IS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .ie_offset = BXT_GPI_IE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .gpp_size = 32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .pin_base = (s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .npins = ((e) - (s) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* BXT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const struct pinctrl_pin_desc bxt_north_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PINCTRL_PIN(0, "GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PINCTRL_PIN(1, "GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PINCTRL_PIN(2, "GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PINCTRL_PIN(3, "GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PINCTRL_PIN(4, "GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PINCTRL_PIN(5, "GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PINCTRL_PIN(6, "GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PINCTRL_PIN(7, "GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PINCTRL_PIN(8, "GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PINCTRL_PIN(9, "GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PINCTRL_PIN(10, "GPIO_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PINCTRL_PIN(11, "GPIO_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PINCTRL_PIN(12, "GPIO_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PINCTRL_PIN(13, "GPIO_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PINCTRL_PIN(14, "GPIO_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PINCTRL_PIN(15, "GPIO_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PINCTRL_PIN(16, "GPIO_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINCTRL_PIN(17, "GPIO_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PINCTRL_PIN(18, "GPIO_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINCTRL_PIN(19, "GPIO_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PINCTRL_PIN(20, "GPIO_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN(21, "GPIO_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN(22, "GPIO_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN(23, "GPIO_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN(24, "GPIO_24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN(25, "GPIO_25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN(26, "GPIO_26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINCTRL_PIN(27, "GPIO_27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN(28, "GPIO_28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN(29, "GPIO_29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN(30, "GPIO_30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN(31, "GPIO_31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN(32, "GPIO_32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(33, "GPIO_33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINCTRL_PIN(34, "PWM0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(35, "PWM1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(36, "PWM2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINCTRL_PIN(37, "PWM3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(38, "LPSS_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINCTRL_PIN(39, "LPSS_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINCTRL_PIN(42, "LPSS_UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINCTRL_PIN(43, "LPSS_UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PINCTRL_PIN(46, "LPSS_UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINCTRL_PIN(47, "LPSS_UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(50, "ISH_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINCTRL_PIN(51, "ISH_UART0_TXT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(52, "ISH_UART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(53, "ISH_UART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(54, "ISH_UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(55, "ISH_UART1_TXT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(56, "ISH_UART1_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(57, "ISH_UART1_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(58, "ISH_UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(59, "ISH_UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(60, "ISH_UART2_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(61, "ISH_UART2_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(62, "GP_CAMERASB00"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(63, "GP_CAMERASB01"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(64, "GP_CAMERASB02"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(65, "GP_CAMERASB03"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(66, "GP_CAMERASB04"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(67, "GP_CAMERASB05"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(68, "GP_CAMERASB06"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(69, "GP_CAMERASB07"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(70, "GP_CAMERASB08"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(71, "GP_CAMERASB09"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(72, "GP_CAMERASB10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(73, "GP_CAMERASB11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(74, "TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(75, "TRST_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(76, "TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(77, "TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(78, "CX_PMODE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(79, "CX_PREQ_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(80, "JTAGX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(81, "CX_PRDY_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(82, "TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const unsigned int bxt_north_pwm0_pins[] = { 34 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const unsigned int bxt_north_pwm1_pins[] = { 35 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const unsigned int bxt_north_pwm2_pins[] = { 36 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const unsigned int bxt_north_pwm3_pins[] = { 37 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const unsigned int bxt_north_uart0_pins[] = { 38, 39, 40, 41 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const unsigned int bxt_north_uart1_pins[] = { 42, 43, 44, 45 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const unsigned int bxt_north_uart2_pins[] = { 46, 47, 48, 49 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const unsigned int bxt_north_uart0b_pins[] = { 50, 51, 52, 53 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const unsigned int bxt_north_uart1b_pins[] = { 54, 55, 56, 57 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const unsigned int bxt_north_uart2b_pins[] = { 58, 59, 60, 61 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const unsigned int bxt_north_uart3_pins[] = { 58, 59, 60, 61 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct intel_pingroup bxt_north_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PIN_GROUP("pwm0_grp", bxt_north_pwm0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PIN_GROUP("pwm1_grp", bxt_north_pwm1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PIN_GROUP("pwm2_grp", bxt_north_pwm2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PIN_GROUP("pwm3_grp", bxt_north_pwm3_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PIN_GROUP("uart0_grp", bxt_north_uart0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PIN_GROUP("uart1_grp", bxt_north_uart1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PIN_GROUP("uart2_grp", bxt_north_uart2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PIN_GROUP("uart0b_grp", bxt_north_uart0b_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PIN_GROUP("uart1b_grp", bxt_north_uart1b_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PIN_GROUP("uart2b_grp", bxt_north_uart2b_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PIN_GROUP("uart3_grp", bxt_north_uart3_pins, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const char * const bxt_north_pwm0_groups[] = { "pwm0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const char * const bxt_north_pwm1_groups[] = { "pwm1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const char * const bxt_north_pwm2_groups[] = { "pwm2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const char * const bxt_north_pwm3_groups[] = { "pwm3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const char * const bxt_north_uart0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "uart0_grp", "uart0b_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const char * const bxt_north_uart1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "uart1_grp", "uart1b_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const char * const bxt_north_uart2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "uart2_grp", "uart2b_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const char * const bxt_north_uart3_groups[] = { "uart3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct intel_function bxt_north_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) FUNCTION("pwm0", bxt_north_pwm0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) FUNCTION("pwm1", bxt_north_pwm1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FUNCTION("pwm2", bxt_north_pwm2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) FUNCTION("pwm3", bxt_north_pwm3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) FUNCTION("uart0", bxt_north_uart0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) FUNCTION("uart1", bxt_north_uart1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FUNCTION("uart2", bxt_north_uart2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) FUNCTION("uart3", bxt_north_uart3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct intel_community bxt_north_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) BXT_COMMUNITY(0, 82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct intel_pinctrl_soc_data bxt_north_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .uid = "1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .pins = bxt_north_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .npins = ARRAY_SIZE(bxt_north_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .groups = bxt_north_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .ngroups = ARRAY_SIZE(bxt_north_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .functions = bxt_north_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .nfunctions = ARRAY_SIZE(bxt_north_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .communities = bxt_north_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .ncommunities = ARRAY_SIZE(bxt_north_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct pinctrl_pin_desc bxt_northwest_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(0, "PMC_SPI_FS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(1, "PMC_SPI_FS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(2, "PMC_SPI_FS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(3, "PMC_SPI_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(4, "PMC_SPI_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(5, "PMC_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(6, "PMC_UART_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(7, "PMC_UART_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(8, "PMIC_PWRGOOD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(9, "PMIC_RESET_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(10, "RTC_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(11, "PMIC_SDWN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(12, "PMIC_BCUDISW2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(13, "PMIC_BCUDISCRIT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(14, "PMIC_THERMTRIP_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(15, "PMIC_STDBY"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(16, "SVID0_ALERT_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(17, "SVID0_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(18, "SVID0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(19, "PMIC_I2C_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(20, "PMIC_I2C_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(21, "AVS_I2S1_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(22, "AVS_I2S1_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(23, "AVS_I2S1_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(24, "AVS_I2S1_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(25, "AVS_I2S1_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(26, "AVS_M_CLK_A1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(27, "AVS_M_CLK_B1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(28, "AVS_M_DATA_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(29, "AVS_M_CLK_AB2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(30, "AVS_M_DATA_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(31, "AVS_I2S2_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(32, "AVS_I2S2_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(33, "AVS_I2S2_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(34, "AVS_I2S2_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(35, "AVS_I2S2_SDOK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(36, "AVS_I2S3_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(37, "AVS_I2S3_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(38, "AVS_I2S3_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(39, "AVS_I2S3_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(40, "AVS_I2S4_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(41, "AVS_I2S4_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(42, "AVS_I2S4_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(43, "AVS_I2S4_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(44, "PROCHOT_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(45, "FST_SPI_CS0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(46, "FST_SPI_CS1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(47, "FST_SPI_MOSI_IO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(48, "FST_SPI_MISO_IO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(49, "FST_SPI_IO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(50, "FST_SPI_IO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(51, "FST_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(52, "FST_SPI_CLK_FB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(53, "GP_SSP_0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(54, "GP_SSP_0_FS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(55, "GP_SSP_0_FS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(56, "GP_SSP_0_FS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(57, "GP_SSP_0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(58, "GP_SSP_0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(59, "GP_SSP_1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(60, "GP_SSP_1_FS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(61, "GP_SSP_1_FS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(62, "GP_SSP_1_FS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(63, "GP_SSP_1_FS3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(64, "GP_SSP_1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(65, "GP_SSP_1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(66, "GP_SSP_2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(67, "GP_SSP_2_FS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(68, "GP_SSP_2_FS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(69, "GP_SSP_2_FS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(70, "GP_SSP_2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(71, "GP_SSP_2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const unsigned int bxt_northwest_ssp0_pins[] = { 53, 54, 55, 56, 57, 58 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const unsigned int bxt_northwest_ssp1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 59, 60, 61, 62, 63, 64, 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const unsigned int bxt_northwest_ssp2_pins[] = { 66, 67, 68, 69, 70, 71 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const unsigned int bxt_northwest_uart3_pins[] = { 67, 68, 69, 70 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct intel_pingroup bxt_northwest_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PIN_GROUP("ssp0_grp", bxt_northwest_ssp0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PIN_GROUP("ssp1_grp", bxt_northwest_ssp1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PIN_GROUP("ssp2_grp", bxt_northwest_ssp2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PIN_GROUP("uart3_grp", bxt_northwest_uart3_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const char * const bxt_northwest_ssp0_groups[] = { "ssp0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const char * const bxt_northwest_ssp1_groups[] = { "ssp1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const char * const bxt_northwest_ssp2_groups[] = { "ssp2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const char * const bxt_northwest_uart3_groups[] = { "uart3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct intel_function bxt_northwest_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) FUNCTION("ssp0", bxt_northwest_ssp0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) FUNCTION("ssp1", bxt_northwest_ssp1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) FUNCTION("ssp2", bxt_northwest_ssp2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) FUNCTION("uart3", bxt_northwest_uart3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct intel_community bxt_northwest_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) BXT_COMMUNITY(0, 71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .uid = "2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .pins = bxt_northwest_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .npins = ARRAY_SIZE(bxt_northwest_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .groups = bxt_northwest_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .ngroups = ARRAY_SIZE(bxt_northwest_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .functions = bxt_northwest_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .nfunctions = ARRAY_SIZE(bxt_northwest_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .communities = bxt_northwest_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .ncommunities = ARRAY_SIZE(bxt_northwest_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const struct pinctrl_pin_desc bxt_west_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(16, "ISH_I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(17, "ISH_I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(18, "ISH_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(19, "ISH_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(20, "ISH_I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(21, "ISH_I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(22, "ISH_GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(23, "ISH_GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(24, "ISH_GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(25, "ISH_GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(26, "ISH_GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(27, "ISH_GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(28, "ISH_GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(29, "ISH_GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_PIN(30, "ISH_GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(31, "ISH_GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(32, "MODEM_CLKREQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(33, "DGCLKDBG_PMC_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(34, "DGCLKDBG_PMC_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(35, "DGCLKDBG_PMC_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(36, "DGCLKDBG_ICLK_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(37, "DGCLKDBG_ICLK_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(38, "OSC_CLK_OUT_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(39, "OSC_CLK_OUT_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_PIN(40, "OSC_CLK_OUT_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINCTRL_PIN(41, "OSC_CLK_OUT_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const unsigned int bxt_west_i2c0_pins[] = { 0, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const unsigned int bxt_west_i2c1_pins[] = { 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const unsigned int bxt_west_i2c2_pins[] = { 4, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const unsigned int bxt_west_i2c3_pins[] = { 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const unsigned int bxt_west_i2c4_pins[] = { 8, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const unsigned int bxt_west_i2c5_pins[] = { 10, 11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const unsigned int bxt_west_i2c6_pins[] = { 12, 13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const unsigned int bxt_west_i2c7_pins[] = { 14, 15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const unsigned int bxt_west_i2c5b_pins[] = { 16, 17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const unsigned int bxt_west_i2c6b_pins[] = { 18, 19 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const unsigned int bxt_west_i2c7b_pins[] = { 20, 21 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct intel_pingroup bxt_west_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PIN_GROUP("i2c0_grp", bxt_west_i2c0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PIN_GROUP("i2c1_grp", bxt_west_i2c1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PIN_GROUP("i2c2_grp", bxt_west_i2c2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PIN_GROUP("i2c3_grp", bxt_west_i2c3_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PIN_GROUP("i2c4_grp", bxt_west_i2c4_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PIN_GROUP("i2c5_grp", bxt_west_i2c5_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PIN_GROUP("i2c6_grp", bxt_west_i2c6_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PIN_GROUP("i2c7_grp", bxt_west_i2c7_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PIN_GROUP("i2c5b_grp", bxt_west_i2c5b_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PIN_GROUP("i2c6b_grp", bxt_west_i2c6b_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PIN_GROUP("i2c7b_grp", bxt_west_i2c7b_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const char * const bxt_west_i2c0_groups[] = { "i2c0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const char * const bxt_west_i2c1_groups[] = { "i2c1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const char * const bxt_west_i2c2_groups[] = { "i2c2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const char * const bxt_west_i2c3_groups[] = { "i2c3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const char * const bxt_west_i2c4_groups[] = { "i2c4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const char * const bxt_west_i2c5_groups[] = { "i2c5_grp", "i2c5b_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static const char * const bxt_west_i2c6_groups[] = { "i2c6_grp", "i2c6b_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const char * const bxt_west_i2c7_groups[] = { "i2c7_grp", "i2c7b_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct intel_function bxt_west_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) FUNCTION("i2c0", bxt_west_i2c0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) FUNCTION("i2c1", bxt_west_i2c1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) FUNCTION("i2c2", bxt_west_i2c2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) FUNCTION("i2c3", bxt_west_i2c3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) FUNCTION("i2c4", bxt_west_i2c4_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) FUNCTION("i2c5", bxt_west_i2c5_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) FUNCTION("i2c6", bxt_west_i2c6_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) FUNCTION("i2c7", bxt_west_i2c7_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const struct intel_community bxt_west_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) BXT_COMMUNITY(0, 41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const struct intel_pinctrl_soc_data bxt_west_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .uid = "3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .pins = bxt_west_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .npins = ARRAY_SIZE(bxt_west_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .groups = bxt_west_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .ngroups = ARRAY_SIZE(bxt_west_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .functions = bxt_west_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .nfunctions = ARRAY_SIZE(bxt_west_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .communities = bxt_west_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .ncommunities = ARRAY_SIZE(bxt_west_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const struct pinctrl_pin_desc bxt_southwest_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINCTRL_PIN(0, "EMMC0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PINCTRL_PIN(1, "EMMC0_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINCTRL_PIN(2, "EMMC0_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PINCTRL_PIN(3, "EMMC0_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINCTRL_PIN(4, "EMMC0_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINCTRL_PIN(5, "EMMC0_D4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINCTRL_PIN(6, "EMMC0_D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINCTRL_PIN(7, "EMMC0_D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINCTRL_PIN(8, "EMMC0_D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINCTRL_PIN(9, "EMMC0_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINCTRL_PIN(10, "SDIO_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINCTRL_PIN(11, "SDIO_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINCTRL_PIN(12, "SDIO_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINCTRL_PIN(13, "SDIO_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINCTRL_PIN(14, "SDIO_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINCTRL_PIN(15, "SDIO_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINCTRL_PIN(16, "SDCARD_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINCTRL_PIN(17, "SDCARD_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINCTRL_PIN(18, "SDCARD_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINCTRL_PIN(19, "SDCARD_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINCTRL_PIN(20, "SDCARD_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINCTRL_PIN(21, "SDCARD_CD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PINCTRL_PIN(22, "SDCARD_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINCTRL_PIN(23, "SDCARD_LVL_CLK_FB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINCTRL_PIN(24, "SDCARD_LVL_CMD_DIR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINCTRL_PIN(25, "SDCARD_LVL_DAT_DIR"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINCTRL_PIN(26, "EMMC0_STROBE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINCTRL_PIN(27, "SDIO_PWR_DOWN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINCTRL_PIN(28, "SDCARD_PWR_DOWN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINCTRL_PIN(29, "SDCARD_LVL_SEL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINCTRL_PIN(30, "SDCARD_LVL_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const unsigned int bxt_southwest_emmc0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const unsigned int bxt_southwest_sdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 10, 11, 12, 13, 14, 15, 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const unsigned int bxt_southwest_sdcard_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct intel_pingroup bxt_southwest_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PIN_GROUP("emmc0_grp", bxt_southwest_emmc0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PIN_GROUP("sdio_grp", bxt_southwest_sdio_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PIN_GROUP("sdcard_grp", bxt_southwest_sdcard_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const char * const bxt_southwest_emmc0_groups[] = { "emmc0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const char * const bxt_southwest_sdio_groups[] = { "sdio_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static const char * const bxt_southwest_sdcard_groups[] = { "sdcard_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct intel_function bxt_southwest_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) FUNCTION("emmc0", bxt_southwest_emmc0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) FUNCTION("sdio", bxt_southwest_sdio_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) FUNCTION("sdcard", bxt_southwest_sdcard_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const struct intel_community bxt_southwest_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) BXT_COMMUNITY(0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .uid = "4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .pins = bxt_southwest_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .npins = ARRAY_SIZE(bxt_southwest_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .groups = bxt_southwest_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .ngroups = ARRAY_SIZE(bxt_southwest_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .functions = bxt_southwest_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .nfunctions = ARRAY_SIZE(bxt_southwest_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .communities = bxt_southwest_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .ncommunities = ARRAY_SIZE(bxt_southwest_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct pinctrl_pin_desc bxt_south_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINCTRL_PIN(4, "DBI_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PINCTRL_PIN(5, "DBI_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PINCTRL_PIN(6, "PANEL0_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINCTRL_PIN(7, "PANEL0_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINCTRL_PIN(9, "PANEL1_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINCTRL_PIN(10, "PANEL1_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PINCTRL_PIN(12, "DBI_CSX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PINCTRL_PIN(13, "DBI_RESX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINCTRL_PIN(16, "USB_OC0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINCTRL_PIN(17, "USB_OC1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PINCTRL_PIN(18, "MEX_WAKE0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PINCTRL_PIN(19, "MEX_WAKE1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const struct intel_community bxt_south_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) BXT_COMMUNITY(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct intel_pinctrl_soc_data bxt_south_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .uid = "5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .pins = bxt_south_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .npins = ARRAY_SIZE(bxt_south_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .communities = bxt_south_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .ncommunities = ARRAY_SIZE(bxt_south_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const struct intel_pinctrl_soc_data *bxt_pinctrl_soc_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) &bxt_north_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) &bxt_northwest_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &bxt_west_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &bxt_southwest_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &bxt_south_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* APL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct pinctrl_pin_desc apl_north_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINCTRL_PIN(0, "GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINCTRL_PIN(1, "GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINCTRL_PIN(2, "GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINCTRL_PIN(3, "GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINCTRL_PIN(4, "GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINCTRL_PIN(5, "GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINCTRL_PIN(6, "GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PINCTRL_PIN(7, "GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINCTRL_PIN(8, "GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINCTRL_PIN(9, "GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINCTRL_PIN(10, "GPIO_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINCTRL_PIN(11, "GPIO_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINCTRL_PIN(12, "GPIO_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINCTRL_PIN(13, "GPIO_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINCTRL_PIN(14, "GPIO_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINCTRL_PIN(15, "GPIO_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PINCTRL_PIN(16, "GPIO_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PINCTRL_PIN(17, "GPIO_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINCTRL_PIN(18, "GPIO_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PINCTRL_PIN(19, "GPIO_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PINCTRL_PIN(20, "GPIO_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PINCTRL_PIN(21, "GPIO_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINCTRL_PIN(22, "GPIO_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINCTRL_PIN(23, "GPIO_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINCTRL_PIN(24, "GPIO_24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PINCTRL_PIN(25, "GPIO_25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PINCTRL_PIN(26, "GPIO_26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINCTRL_PIN(27, "GPIO_27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINCTRL_PIN(28, "GPIO_28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PINCTRL_PIN(29, "GPIO_29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINCTRL_PIN(30, "GPIO_30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PINCTRL_PIN(31, "GPIO_31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINCTRL_PIN(32, "GPIO_32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PINCTRL_PIN(33, "GPIO_33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINCTRL_PIN(34, "PWM0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINCTRL_PIN(35, "PWM1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINCTRL_PIN(36, "PWM2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PINCTRL_PIN(37, "PWM3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINCTRL_PIN(38, "LPSS_UART0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINCTRL_PIN(39, "LPSS_UART0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINCTRL_PIN(40, "LPSS_UART0_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINCTRL_PIN(41, "LPSS_UART0_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINCTRL_PIN(42, "LPSS_UART1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINCTRL_PIN(43, "LPSS_UART1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINCTRL_PIN(44, "LPSS_UART1_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINCTRL_PIN(45, "LPSS_UART1_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINCTRL_PIN(46, "LPSS_UART2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINCTRL_PIN(47, "LPSS_UART2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINCTRL_PIN(48, "LPSS_UART2_RTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINCTRL_PIN(49, "LPSS_UART2_CTS_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINCTRL_PIN(50, "GP_CAMERASB00"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINCTRL_PIN(51, "GP_CAMERASB01"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINCTRL_PIN(52, "GP_CAMERASB02"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINCTRL_PIN(53, "GP_CAMERASB03"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PINCTRL_PIN(54, "GP_CAMERASB04"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINCTRL_PIN(55, "GP_CAMERASB05"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINCTRL_PIN(56, "GP_CAMERASB06"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINCTRL_PIN(57, "GP_CAMERASB07"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINCTRL_PIN(58, "GP_CAMERASB08"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINCTRL_PIN(59, "GP_CAMERASB09"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINCTRL_PIN(60, "GP_CAMERASB10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINCTRL_PIN(61, "GP_CAMERASB11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINCTRL_PIN(62, "TCK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINCTRL_PIN(63, "TRST_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINCTRL_PIN(64, "TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINCTRL_PIN(65, "TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINCTRL_PIN(66, "CX_PMODE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINCTRL_PIN(67, "CX_PREQ_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PINCTRL_PIN(68, "JTAGX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINCTRL_PIN(69, "CX_PRDY_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINCTRL_PIN(70, "TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINCTRL_PIN(71, "CNV_BRI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINCTRL_PIN(72, "CNV_BRI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINCTRL_PIN(73, "CNV_RGI_DT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINCTRL_PIN(74, "CNV_RGI_RSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINCTRL_PIN(75, "SVID0_ALERT_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINCTRL_PIN(76, "SVID0_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINCTRL_PIN(77, "SVID0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const unsigned int apl_north_pwm0_pins[] = { 34 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const unsigned int apl_north_pwm1_pins[] = { 35 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static const unsigned int apl_north_pwm2_pins[] = { 36 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const unsigned int apl_north_pwm3_pins[] = { 37 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const unsigned int apl_north_uart0_pins[] = { 38, 39, 40, 41 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const unsigned int apl_north_uart1_pins[] = { 42, 43, 44, 45 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const unsigned int apl_north_uart2_pins[] = { 46, 47, 48, 49 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const struct intel_pingroup apl_north_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PIN_GROUP("pwm0_grp", apl_north_pwm0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PIN_GROUP("pwm1_grp", apl_north_pwm1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PIN_GROUP("pwm2_grp", apl_north_pwm2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PIN_GROUP("pwm3_grp", apl_north_pwm3_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PIN_GROUP("uart0_grp", apl_north_uart0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PIN_GROUP("uart1_grp", apl_north_uart1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PIN_GROUP("uart2_grp", apl_north_uart2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const char * const apl_north_pwm0_groups[] = { "pwm0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static const char * const apl_north_pwm1_groups[] = { "pwm1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const char * const apl_north_pwm2_groups[] = { "pwm2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const char * const apl_north_pwm3_groups[] = { "pwm3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static const char * const apl_north_uart0_groups[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const char * const apl_north_uart1_groups[] = { "uart1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const char * const apl_north_uart2_groups[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const struct intel_function apl_north_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) FUNCTION("pwm0", apl_north_pwm0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) FUNCTION("pwm1", apl_north_pwm1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) FUNCTION("pwm2", apl_north_pwm2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) FUNCTION("pwm3", apl_north_pwm3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) FUNCTION("uart0", apl_north_uart0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) FUNCTION("uart1", apl_north_uart1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) FUNCTION("uart2", apl_north_uart2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const struct intel_community apl_north_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) BXT_COMMUNITY(0, 77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const struct intel_pinctrl_soc_data apl_north_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .uid = "1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .pins = apl_north_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .npins = ARRAY_SIZE(apl_north_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .groups = apl_north_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .ngroups = ARRAY_SIZE(apl_north_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .functions = apl_north_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .nfunctions = ARRAY_SIZE(apl_north_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .communities = apl_north_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .ncommunities = ARRAY_SIZE(apl_north_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const struct pinctrl_pin_desc apl_northwest_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINCTRL_PIN(0, "HV_DDI0_DDC_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINCTRL_PIN(1, "HV_DDI0_DDC_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PINCTRL_PIN(2, "HV_DDI1_DDC_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINCTRL_PIN(3, "HV_DDI1_DDC_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINCTRL_PIN(4, "DBI_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PINCTRL_PIN(5, "DBI_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINCTRL_PIN(6, "PANEL0_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINCTRL_PIN(7, "PANEL0_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PINCTRL_PIN(8, "PANEL0_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINCTRL_PIN(9, "PANEL1_VDDEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINCTRL_PIN(10, "PANEL1_BKLTEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINCTRL_PIN(11, "PANEL1_BKLTCTL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PINCTRL_PIN(12, "DBI_CSX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINCTRL_PIN(13, "DBI_RESX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINCTRL_PIN(14, "GP_INTD_DSI_TE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PINCTRL_PIN(15, "GP_INTD_DSI_TE2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINCTRL_PIN(16, "USB_OC0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINCTRL_PIN(17, "USB_OC1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINCTRL_PIN(18, "PMC_SPI_FS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINCTRL_PIN(19, "PMC_SPI_FS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINCTRL_PIN(20, "PMC_SPI_FS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINCTRL_PIN(21, "PMC_SPI_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PINCTRL_PIN(22, "PMC_SPI_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINCTRL_PIN(23, "PMC_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINCTRL_PIN(24, "PMIC_PWRGOOD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINCTRL_PIN(25, "PMIC_RESET_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINCTRL_PIN(26, "PMIC_SDWN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PINCTRL_PIN(27, "PMIC_BCUDISW2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PINCTRL_PIN(28, "PMIC_BCUDISCRIT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINCTRL_PIN(29, "PMIC_THERMTRIP_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINCTRL_PIN(30, "PMIC_STDBY"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINCTRL_PIN(31, "PROCHOT_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINCTRL_PIN(32, "PMIC_I2C_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PINCTRL_PIN(33, "PMIC_I2C_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINCTRL_PIN(34, "AVS_I2S1_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINCTRL_PIN(35, "AVS_I2S1_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINCTRL_PIN(36, "AVS_I2S1_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINCTRL_PIN(37, "AVS_I2S1_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PINCTRL_PIN(38, "AVS_I2S1_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINCTRL_PIN(39, "AVS_M_CLK_A1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PINCTRL_PIN(40, "AVS_M_CLK_B1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINCTRL_PIN(41, "AVS_M_DATA_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINCTRL_PIN(42, "AVS_M_CLK_AB2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PINCTRL_PIN(43, "AVS_M_DATA_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PINCTRL_PIN(44, "AVS_I2S2_MCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINCTRL_PIN(45, "AVS_I2S2_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINCTRL_PIN(46, "AVS_I2S2_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINCTRL_PIN(47, "AVS_I2S2_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINCTRL_PIN(48, "AVS_I2S2_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINCTRL_PIN(49, "AVS_I2S3_BCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PINCTRL_PIN(50, "AVS_I2S3_WS_SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINCTRL_PIN(51, "AVS_I2S3_SDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINCTRL_PIN(52, "AVS_I2S3_SDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PINCTRL_PIN(53, "FST_SPI_CS0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINCTRL_PIN(54, "FST_SPI_CS1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINCTRL_PIN(55, "FST_SPI_MOSI_IO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PINCTRL_PIN(56, "FST_SPI_MISO_IO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PINCTRL_PIN(57, "FST_SPI_IO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PINCTRL_PIN(58, "FST_SPI_IO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PINCTRL_PIN(59, "FST_SPI_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PINCTRL_PIN(60, "FST_SPI_CLK_FB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PINCTRL_PIN(61, "GP_SSP_0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PINCTRL_PIN(62, "GP_SSP_0_FS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PINCTRL_PIN(63, "GP_SSP_0_FS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PINCTRL_PIN(64, "GP_SSP_0_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PINCTRL_PIN(65, "GP_SSP_0_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PINCTRL_PIN(66, "GP_SSP_1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PINCTRL_PIN(67, "GP_SSP_1_FS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PINCTRL_PIN(68, "GP_SSP_1_FS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PINCTRL_PIN(69, "GP_SSP_1_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINCTRL_PIN(70, "GP_SSP_1_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PINCTRL_PIN(71, "GP_SSP_2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PINCTRL_PIN(72, "GP_SSP_2_FS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PINCTRL_PIN(73, "GP_SSP_2_FS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PINCTRL_PIN(74, "GP_SSP_2_FS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PINCTRL_PIN(75, "GP_SSP_2_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PINCTRL_PIN(76, "GP_SSP_2_TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const unsigned int apl_northwest_ssp0_pins[] = { 61, 62, 63, 64, 65 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static const unsigned int apl_northwest_ssp1_pins[] = { 66, 67, 68, 69, 70 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const unsigned int apl_northwest_ssp2_pins[] = { 71, 72, 73, 74, 75, 76 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const unsigned int apl_northwest_uart3_pins[] = { 67, 68, 69, 70 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static const struct intel_pingroup apl_northwest_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PIN_GROUP("ssp0_grp", apl_northwest_ssp0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PIN_GROUP("ssp1_grp", apl_northwest_ssp1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PIN_GROUP("ssp2_grp", apl_northwest_ssp2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) PIN_GROUP("uart3_grp", apl_northwest_uart3_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const char * const apl_northwest_ssp0_groups[] = { "ssp0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static const char * const apl_northwest_ssp1_groups[] = { "ssp1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const char * const apl_northwest_ssp2_groups[] = { "ssp2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static const char * const apl_northwest_uart3_groups[] = { "uart3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static const struct intel_function apl_northwest_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) FUNCTION("ssp0", apl_northwest_ssp0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) FUNCTION("ssp1", apl_northwest_ssp1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) FUNCTION("ssp2", apl_northwest_ssp2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) FUNCTION("uart3", apl_northwest_uart3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const struct intel_community apl_northwest_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) BXT_COMMUNITY(0, 76),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static const struct intel_pinctrl_soc_data apl_northwest_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .uid = "2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .pins = apl_northwest_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .npins = ARRAY_SIZE(apl_northwest_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .groups = apl_northwest_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .ngroups = ARRAY_SIZE(apl_northwest_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .functions = apl_northwest_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .nfunctions = ARRAY_SIZE(apl_northwest_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .communities = apl_northwest_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .ncommunities = ARRAY_SIZE(apl_northwest_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const struct pinctrl_pin_desc apl_west_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PINCTRL_PIN(0, "LPSS_I2C0_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PINCTRL_PIN(1, "LPSS_I2C0_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) PINCTRL_PIN(2, "LPSS_I2C1_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINCTRL_PIN(3, "LPSS_I2C1_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINCTRL_PIN(4, "LPSS_I2C2_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINCTRL_PIN(5, "LPSS_I2C2_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) PINCTRL_PIN(6, "LPSS_I2C3_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) PINCTRL_PIN(7, "LPSS_I2C3_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINCTRL_PIN(8, "LPSS_I2C4_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PINCTRL_PIN(9, "LPSS_I2C4_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PINCTRL_PIN(10, "LPSS_I2C5_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) PINCTRL_PIN(11, "LPSS_I2C5_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) PINCTRL_PIN(12, "LPSS_I2C6_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) PINCTRL_PIN(13, "LPSS_I2C6_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PINCTRL_PIN(14, "LPSS_I2C7_SDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PINCTRL_PIN(15, "LPSS_I2C7_SCL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINCTRL_PIN(16, "ISH_GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINCTRL_PIN(17, "ISH_GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) PINCTRL_PIN(18, "ISH_GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PINCTRL_PIN(19, "ISH_GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINCTRL_PIN(20, "ISH_GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) PINCTRL_PIN(21, "ISH_GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PINCTRL_PIN(22, "ISH_GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) PINCTRL_PIN(23, "ISH_GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PINCTRL_PIN(24, "ISH_GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINCTRL_PIN(25, "ISH_GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINCTRL_PIN(26, "PCIE_CLKREQ0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINCTRL_PIN(27, "PCIE_CLKREQ1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) PINCTRL_PIN(28, "PCIE_CLKREQ2_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) PINCTRL_PIN(29, "PCIE_CLKREQ3_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PINCTRL_PIN(30, "OSC_CLK_OUT_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINCTRL_PIN(31, "OSC_CLK_OUT_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINCTRL_PIN(32, "OSC_CLK_OUT_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PINCTRL_PIN(33, "OSC_CLK_OUT_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) PINCTRL_PIN(34, "OSC_CLK_OUT_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PINCTRL_PIN(35, "PMU_AC_PRESENT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINCTRL_PIN(36, "PMU_BATLOW_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINCTRL_PIN(37, "PMU_PLTRST_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) PINCTRL_PIN(38, "PMU_PWRBTN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PINCTRL_PIN(39, "PMU_RESETBUTTON_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINCTRL_PIN(40, "PMU_SLP_S0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) PINCTRL_PIN(41, "PMU_SLP_S3_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PINCTRL_PIN(42, "PMU_SLP_S4_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) PINCTRL_PIN(43, "PMU_SUSCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) PINCTRL_PIN(44, "PMU_WAKE_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) PINCTRL_PIN(45, "SUS_STAT_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINCTRL_PIN(46, "SUSPWRDNACK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static const unsigned int apl_west_i2c0_pins[] = { 0, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static const unsigned int apl_west_i2c1_pins[] = { 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static const unsigned int apl_west_i2c2_pins[] = { 4, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static const unsigned int apl_west_i2c3_pins[] = { 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static const unsigned int apl_west_i2c4_pins[] = { 8, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static const unsigned int apl_west_i2c5_pins[] = { 10, 11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static const unsigned int apl_west_i2c6_pins[] = { 12, 13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static const unsigned int apl_west_i2c7_pins[] = { 14, 15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const unsigned int apl_west_uart2_pins[] = { 20, 21, 22, 34 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const struct intel_pingroup apl_west_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PIN_GROUP("i2c0_grp", apl_west_i2c0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) PIN_GROUP("i2c1_grp", apl_west_i2c1_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PIN_GROUP("i2c2_grp", apl_west_i2c2_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PIN_GROUP("i2c3_grp", apl_west_i2c3_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PIN_GROUP("i2c4_grp", apl_west_i2c4_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PIN_GROUP("i2c5_grp", apl_west_i2c5_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PIN_GROUP("i2c6_grp", apl_west_i2c6_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PIN_GROUP("i2c7_grp", apl_west_i2c7_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PIN_GROUP("uart2_grp", apl_west_uart2_pins, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const char * const apl_west_i2c0_groups[] = { "i2c0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const char * const apl_west_i2c1_groups[] = { "i2c1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const char * const apl_west_i2c2_groups[] = { "i2c2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const char * const apl_west_i2c3_groups[] = { "i2c3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const char * const apl_west_i2c4_groups[] = { "i2c4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static const char * const apl_west_i2c5_groups[] = { "i2c5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static const char * const apl_west_i2c6_groups[] = { "i2c6_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const char * const apl_west_i2c7_groups[] = { "i2c7_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const char * const apl_west_uart2_groups[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static const struct intel_function apl_west_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) FUNCTION("i2c0", apl_west_i2c0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) FUNCTION("i2c1", apl_west_i2c1_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) FUNCTION("i2c2", apl_west_i2c2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) FUNCTION("i2c3", apl_west_i2c3_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) FUNCTION("i2c4", apl_west_i2c4_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) FUNCTION("i2c5", apl_west_i2c5_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) FUNCTION("i2c6", apl_west_i2c6_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) FUNCTION("i2c7", apl_west_i2c7_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) FUNCTION("uart2", apl_west_uart2_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static const struct intel_community apl_west_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) BXT_COMMUNITY(0, 46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static const struct intel_pinctrl_soc_data apl_west_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .uid = "3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .pins = apl_west_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .npins = ARRAY_SIZE(apl_west_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .groups = apl_west_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .ngroups = ARRAY_SIZE(apl_west_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .functions = apl_west_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .nfunctions = ARRAY_SIZE(apl_west_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .communities = apl_west_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) .ncommunities = ARRAY_SIZE(apl_west_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static const struct pinctrl_pin_desc apl_southwest_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINCTRL_PIN(0, "PCIE_WAKE0_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PINCTRL_PIN(1, "PCIE_WAKE1_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINCTRL_PIN(2, "PCIE_WAKE2_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINCTRL_PIN(3, "PCIE_WAKE3_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINCTRL_PIN(4, "EMMC0_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PINCTRL_PIN(5, "EMMC0_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) PINCTRL_PIN(6, "EMMC0_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PINCTRL_PIN(7, "EMMC0_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINCTRL_PIN(8, "EMMC0_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PINCTRL_PIN(9, "EMMC0_D4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) PINCTRL_PIN(10, "EMMC0_D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PINCTRL_PIN(11, "EMMC0_D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINCTRL_PIN(12, "EMMC0_D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PINCTRL_PIN(13, "EMMC0_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINCTRL_PIN(14, "SDIO_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) PINCTRL_PIN(15, "SDIO_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PINCTRL_PIN(16, "SDIO_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PINCTRL_PIN(17, "SDIO_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PINCTRL_PIN(18, "SDIO_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINCTRL_PIN(19, "SDIO_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) PINCTRL_PIN(20, "SDCARD_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) PINCTRL_PIN(21, "SDCARD_CLK_FB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINCTRL_PIN(22, "SDCARD_D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINCTRL_PIN(23, "SDCARD_D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) PINCTRL_PIN(24, "SDCARD_D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) PINCTRL_PIN(25, "SDCARD_D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PINCTRL_PIN(26, "SDCARD_CD_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINCTRL_PIN(27, "SDCARD_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PINCTRL_PIN(28, "SDCARD_LVL_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PINCTRL_PIN(29, "EMMC0_STROBE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINCTRL_PIN(30, "SDIO_PWR_DOWN_B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINCTRL_PIN(31, "SMB_ALERTB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINCTRL_PIN(32, "SMB_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) PINCTRL_PIN(33, "SMB_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PINCTRL_PIN(34, "LPC_ILB_SERIRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINCTRL_PIN(35, "LPC_CLKOUT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINCTRL_PIN(36, "LPC_CLKOUT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PINCTRL_PIN(37, "LPC_AD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PINCTRL_PIN(38, "LPC_AD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINCTRL_PIN(39, "LPC_AD2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PINCTRL_PIN(40, "LPC_AD3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) PINCTRL_PIN(41, "LPC_CLKRUNB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PINCTRL_PIN(42, "LPC_FRAMEB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static const unsigned int apl_southwest_emmc0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static const unsigned int apl_southwest_sdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) 14, 15, 16, 17, 18, 19, 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static const unsigned int apl_southwest_sdcard_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) 20, 21, 22, 23, 24, 25, 26, 27, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static const unsigned int apl_southwest_i2c7_pins[] = { 32, 33 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const struct intel_pingroup apl_southwest_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PIN_GROUP("emmc0_grp", apl_southwest_emmc0_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PIN_GROUP("sdio_grp", apl_southwest_sdio_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PIN_GROUP("sdcard_grp", apl_southwest_sdcard_pins, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PIN_GROUP("i2c7_grp", apl_southwest_i2c7_pins, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const char * const apl_southwest_emmc0_groups[] = { "emmc0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static const char * const apl_southwest_sdio_groups[] = { "sdio_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const char * const apl_southwest_sdcard_groups[] = { "sdcard_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static const char * const apl_southwest_i2c7_groups[] = { "i2c7_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static const struct intel_function apl_southwest_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) FUNCTION("emmc0", apl_southwest_emmc0_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) FUNCTION("sdio", apl_southwest_sdio_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) FUNCTION("sdcard", apl_southwest_sdcard_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) FUNCTION("i2c7", apl_southwest_i2c7_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const struct intel_community apl_southwest_communities[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) BXT_COMMUNITY(0, 42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const struct intel_pinctrl_soc_data apl_southwest_soc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .uid = "4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .pins = apl_southwest_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .npins = ARRAY_SIZE(apl_southwest_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .groups = apl_southwest_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .ngroups = ARRAY_SIZE(apl_southwest_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .functions = apl_southwest_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .nfunctions = ARRAY_SIZE(apl_southwest_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .communities = apl_southwest_communities,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .ncommunities = ARRAY_SIZE(apl_southwest_communities),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const struct intel_pinctrl_soc_data *apl_pinctrl_soc_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) &apl_north_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) &apl_northwest_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) &apl_west_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) &apl_southwest_soc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static const struct acpi_device_id bxt_pinctrl_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) { "INT3452", (kernel_ulong_t)apl_pinctrl_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) { "INT34D1", (kernel_ulong_t)bxt_pinctrl_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) MODULE_DEVICE_TABLE(acpi, bxt_pinctrl_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static const struct platform_device_id bxt_pinctrl_platform_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) { "apollolake-pinctrl", (kernel_ulong_t)apl_pinctrl_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) { "broxton-pinctrl", (kernel_ulong_t)bxt_pinctrl_soc_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static INTEL_PINCTRL_PM_OPS(bxt_pinctrl_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static struct platform_driver bxt_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .probe = intel_pinctrl_probe_by_uid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .name = "broxton-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .acpi_match_table = bxt_pinctrl_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .pm = &bxt_pinctrl_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .id_table = bxt_pinctrl_platform_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int __init bxt_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return platform_driver_register(&bxt_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) subsys_initcall(bxt_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static void __exit bxt_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) platform_driver_unregister(&bxt_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) module_exit(bxt_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) MODULE_DESCRIPTION("Intel Broxton SoC pinctrl/GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) MODULE_ALIAS("platform:broxton-pinctrl");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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