^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2017-2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Dong Aisheng <aisheng.dong@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/firmware/imx/sci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-imx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum pad_func_e {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) IMX_SC_PAD_FUNC_SET = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) IMX_SC_PAD_FUNC_GET = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct imx_sc_msg_req_pad_set {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct imx_sc_rpc_msg hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u16 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) } __packed __aligned(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct imx_sc_msg_req_pad_get {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct imx_sc_rpc_msg hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u16 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) } __packed __aligned(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct imx_sc_msg_resp_pad_get {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct imx_sc_rpc_msg hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct imx_sc_ipc *pinctrl_ipc_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return imx_scu_get_handle(&pinctrl_ipc_handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) EXPORT_SYMBOL_GPL(imx_pinctrl_sc_ipc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct imx_sc_msg_req_pad_get msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct imx_sc_msg_resp_pad_get *resp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct imx_sc_rpc_msg *hdr = &msg.hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) hdr->ver = IMX_SC_RPC_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) hdr->svc = IMX_SC_RPC_SVC_PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) hdr->func = IMX_SC_PAD_FUNC_GET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) hdr->size = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) msg.pad = pin_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) resp = (struct imx_sc_msg_resp_pad_get *)&msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *config = resp->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) EXPORT_SYMBOL_GPL(imx_pinconf_get_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct imx_sc_msg_req_pad_set msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct imx_sc_rpc_msg *hdr = &msg.hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int mux = configs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int conf = configs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Set mux and conf together in one IPC call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) WARN_ON(num_configs != 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) val = conf | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) val |= mux << BP_PAD_CTL_IFMUX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) hdr->ver = IMX_SC_RPC_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) hdr->svc = IMX_SC_RPC_SVC_PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) hdr->func = IMX_SC_PAD_FUNC_SET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) hdr->size = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) msg.pad = pin_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) msg.val = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_dbg(ipctl->dev, "write: pin_id %u config 0x%x val 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pin_id, conf, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) EXPORT_SYMBOL_GPL(imx_pinconf_set_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int *pin_id, struct imx_pin *pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const __be32 **list_p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct imx_pin_scu *pin_scu = &pin->conf.scu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const __be32 *list = *list_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pin->pin = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *pin_id = pin->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) pin_scu->mux_mode = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pin_scu->config = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *list_p = list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pin_scu->mux_mode, pin_scu->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EXPORT_SYMBOL_GPL(imx_pinctrl_parse_pin_scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MODULE_DESCRIPTION("NXP i.MX SCU common pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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