^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __PINCTRL_MXS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __PINCTRL_MXS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SET 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLR 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TOG 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PINID(bank, pin) ((bank) * 32 + (pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * pinmux-id bit field definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * bank: 15..12 (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * pin: 11..4 (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * muxsel: 3..0 (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MUXID_TO_MUXSEL(m) ((m) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PINID_TO_BANK(p) ((p) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PINID_TO_PIN(p) ((p) % 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * pin config bit field definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * pull-up: 6..5 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * voltage: 4..3 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * mA: 2..0 (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * MSB of each field is presence bit for the config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PULL_PRESENT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PULL_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VOL_PRESENT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VOL_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MA_PRESENT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct mxs_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct mxs_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 *muxsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct mxs_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u16 muxsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u16 drive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u16 pull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct mxs_pinctrl_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const struct mxs_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct mxs_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct mxs_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int mxs_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct mxs_pinctrl_soc_data *soc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif /* __PINCTRL_MXS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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