^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2017-2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pinctrl-imx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) enum imx8mm_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) MX8MM_PAD_RESERVE0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) MX8MM_PAD_RESERVE1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MX8MM_PAD_RESERVE2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MX8MM_PAD_RESERVE3 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MX8MM_PAD_RESERVE4 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MX8MM_PAD_RESERVE5 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MX8MM_PAD_RESERVE6 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MX8MM_PAD_RESERVE7 = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MX8MM_PAD_RESERVE8 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MX8MM_PAD_RESERVE9 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MX8MM_IOMUXC_GPIO1_IO00 = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MX8MM_IOMUXC_GPIO1_IO01 = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MX8MM_IOMUXC_GPIO1_IO02 = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MX8MM_IOMUXC_GPIO1_IO03 = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MX8MM_IOMUXC_GPIO1_IO04 = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MX8MM_IOMUXC_GPIO1_IO05 = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MX8MM_IOMUXC_GPIO1_IO06 = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MX8MM_IOMUXC_GPIO1_IO07 = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MX8MM_IOMUXC_GPIO1_IO08 = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MX8MM_IOMUXC_GPIO1_IO09 = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MX8MM_IOMUXC_GPIO1_IO10 = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MX8MM_IOMUXC_GPIO1_IO11 = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MX8MM_IOMUXC_GPIO1_IO12 = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MX8MM_IOMUXC_GPIO1_IO13 = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MX8MM_IOMUXC_GPIO1_IO14 = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MX8MM_IOMUXC_GPIO1_IO15 = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MX8MM_IOMUXC_ENET_MDC = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MX8MM_IOMUXC_ENET_MDIO = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MX8MM_IOMUXC_ENET_TD3 = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MX8MM_IOMUXC_ENET_TD2 = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MX8MM_IOMUXC_ENET_TD1 = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MX8MM_IOMUXC_ENET_TD0 = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MX8MM_IOMUXC_ENET_TX_CTL = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MX8MM_IOMUXC_ENET_TXC = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MX8MM_IOMUXC_ENET_RX_CTL = 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MX8MM_IOMUXC_ENET_RXC = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MX8MM_IOMUXC_ENET_RD0 = 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MX8MM_IOMUXC_ENET_RD1 = 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MX8MM_IOMUXC_ENET_RD2 = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MX8MM_IOMUXC_ENET_RD3 = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MX8MM_IOMUXC_SD1_CLK = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MX8MM_IOMUXC_SD1_CMD = 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MX8MM_IOMUXC_SD1_DATA0 = 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MX8MM_IOMUXC_SD1_DATA1 = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MX8MM_IOMUXC_SD1_DATA2 = 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MX8MM_IOMUXC_SD1_DATA3 = 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MX8MM_IOMUXC_SD1_DATA4 = 46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MX8MM_IOMUXC_SD1_DATA5 = 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MX8MM_IOMUXC_SD1_DATA6 = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MX8MM_IOMUXC_SD1_DATA7 = 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MX8MM_IOMUXC_SD1_RESET_B = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MX8MM_IOMUXC_SD1_STROBE = 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MX8MM_IOMUXC_SD2_CD_B = 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MX8MM_IOMUXC_SD2_CLK = 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MX8MM_IOMUXC_SD2_CMD = 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MX8MM_IOMUXC_SD2_DATA0 = 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MX8MM_IOMUXC_SD2_DATA1 = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MX8MM_IOMUXC_SD2_DATA2 = 57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MX8MM_IOMUXC_SD2_DATA3 = 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MX8MM_IOMUXC_SD2_RESET_B = 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MX8MM_IOMUXC_SD2_WP = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MX8MM_IOMUXC_NAND_ALE = 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MX8MM_IOMUXC_NAND_CE0 = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MX8MM_IOMUXC_NAND_CE1 = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MX8MM_IOMUXC_NAND_CE2 = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MX8MM_IOMUXC_NAND_CE3 = 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MX8MM_IOMUXC_NAND_CLE = 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MX8MM_IOMUXC_NAND_DATA00 = 67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MX8MM_IOMUXC_NAND_DATA01 = 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MX8MM_IOMUXC_NAND_DATA02 = 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MX8MM_IOMUXC_NAND_DATA03 = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MX8MM_IOMUXC_NAND_DATA04 = 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MX8MM_IOMUXC_NAND_DATA05 = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MX8MM_IOMUXC_NAND_DATA06 = 73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MX8MM_IOMUXC_NAND_DATA07 = 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MX8MM_IOMUXC_NAND_DQS = 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MX8MM_IOMUXC_NAND_RE_B = 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MX8MM_IOMUXC_NAND_READY_B = 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MX8MM_IOMUXC_NAND_WE_B = 78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MX8MM_IOMUXC_NAND_WP_B = 79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MX8MM_IOMUXC_SAI5_RXFS = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MX8MM_IOMUXC_SAI5_RXC = 81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MX8MM_IOMUXC_SAI5_RXD0 = 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MX8MM_IOMUXC_SAI5_RXD1 = 83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MX8MM_IOMUXC_SAI5_RXD2 = 84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MX8MM_IOMUXC_SAI5_RXD3 = 85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MX8MM_IOMUXC_SAI5_MCLK = 86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MX8MM_IOMUXC_SAI1_RXFS = 87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MX8MM_IOMUXC_SAI1_RXC = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MX8MM_IOMUXC_SAI1_RXD0 = 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MX8MM_IOMUXC_SAI1_RXD1 = 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MX8MM_IOMUXC_SAI1_RXD2 = 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MX8MM_IOMUXC_SAI1_RXD3 = 92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MX8MM_IOMUXC_SAI1_RXD4 = 93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MX8MM_IOMUXC_SAI1_RXD5 = 94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MX8MM_IOMUXC_SAI1_RXD6 = 95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MX8MM_IOMUXC_SAI1_RXD7 = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MX8MM_IOMUXC_SAI1_TXFS = 97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MX8MM_IOMUXC_SAI1_TXC = 98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MX8MM_IOMUXC_SAI1_TXD0 = 99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MX8MM_IOMUXC_SAI1_TXD1 = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MX8MM_IOMUXC_SAI1_TXD2 = 101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MX8MM_IOMUXC_SAI1_TXD3 = 102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MX8MM_IOMUXC_SAI1_TXD4 = 103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MX8MM_IOMUXC_SAI1_TXD5 = 104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MX8MM_IOMUXC_SAI1_TXD6 = 105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MX8MM_IOMUXC_SAI1_TXD7 = 106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MX8MM_IOMUXC_SAI1_MCLK = 107,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MX8MM_IOMUXC_SAI2_RXFS = 108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MX8MM_IOMUXC_SAI2_RXC = 109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MX8MM_IOMUXC_SAI2_RXD0 = 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MX8MM_IOMUXC_SAI2_TXFS = 111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MX8MM_IOMUXC_SAI2_TXC = 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MX8MM_IOMUXC_SAI2_TXD0 = 113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MX8MM_IOMUXC_SAI2_MCLK = 114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MX8MM_IOMUXC_SAI3_RXFS = 115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MX8MM_IOMUXC_SAI3_RXC = 116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MX8MM_IOMUXC_SAI3_RXD = 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MX8MM_IOMUXC_SAI3_TXFS = 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MX8MM_IOMUXC_SAI3_TXC = 119,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MX8MM_IOMUXC_SAI3_TXD = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MX8MM_IOMUXC_SAI3_MCLK = 121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MX8MM_IOMUXC_SPDIF_TX = 122,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MX8MM_IOMUXC_SPDIF_RX = 123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MX8MM_IOMUXC_SPDIF_EXT_CLK = 124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MX8MM_IOMUXC_ECSPI1_SCLK = 125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MX8MM_IOMUXC_ECSPI1_MOSI = 126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MX8MM_IOMUXC_ECSPI1_MISO = 127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MX8MM_IOMUXC_ECSPI1_SS0 = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MX8MM_IOMUXC_ECSPI2_SCLK = 129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MX8MM_IOMUXC_ECSPI2_MOSI = 130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MX8MM_IOMUXC_ECSPI2_MISO = 131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MX8MM_IOMUXC_ECSPI2_SS0 = 132,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MX8MM_IOMUXC_I2C1_SCL = 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MX8MM_IOMUXC_I2C1_SDA = 134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MX8MM_IOMUXC_I2C2_SCL = 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MX8MM_IOMUXC_I2C2_SDA = 136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MX8MM_IOMUXC_I2C3_SCL = 137,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MX8MM_IOMUXC_I2C3_SDA = 138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MX8MM_IOMUXC_I2C4_SCL = 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MX8MM_IOMUXC_I2C4_SDA = 140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MX8MM_IOMUXC_UART1_RXD = 141,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MX8MM_IOMUXC_UART1_TXD = 142,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MX8MM_IOMUXC_UART2_RXD = 143,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MX8MM_IOMUXC_UART2_TXD = 144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MX8MM_IOMUXC_UART3_RXD = 145,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MX8MM_IOMUXC_UART3_TXD = 146,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MX8MM_IOMUXC_UART4_RXD = 147,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MX8MM_IOMUXC_UART4_TXD = 148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Pad names for the pinmux subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct pinctrl_pin_desc imx8mm_pinctrl_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) IMX_PINCTRL_PIN(MX8MM_PAD_RESERVE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) IMX_PINCTRL_PIN(MX8MM_IOMUXC_GPIO1_IO15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TX_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_TXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RX_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ENET_RD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_RESET_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD1_STROBE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CD_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_RESET_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SD2_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_ALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CE3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_CLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DATA07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_DQS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_RE_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_READY_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WE_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) IMX_PINCTRL_PIN(MX8MM_IOMUXC_NAND_WP_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXFS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI5_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXFS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_RXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXFS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_TXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI1_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXFS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXFS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI2_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXFS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXFS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SAI3_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) IMX_PINCTRL_PIN(MX8MM_IOMUXC_SPDIF_EXT_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI1_SS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) IMX_PINCTRL_PIN(MX8MM_IOMUXC_ECSPI2_SS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C1_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C2_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C3_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) IMX_PINCTRL_PIN(MX8MM_IOMUXC_I2C4_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART2_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART3_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) IMX_PINCTRL_PIN(MX8MM_IOMUXC_UART4_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct imx_pinctrl_soc_info imx8mm_pinctrl_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .pins = imx8mm_pinctrl_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .npins = ARRAY_SIZE(imx8mm_pinctrl_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .gpr_compatible = "fsl,imx8mm-iomuxc-gpr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct of_device_id imx8mm_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { .compatible = "fsl,imx8mm-iomuxc", .data = &imx8mm_pinctrl_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MODULE_DEVICE_TABLE(of, imx8mm_pinctrl_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int imx8mm_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return imx_pinctrl_probe(pdev, &imx8mm_pinctrl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static struct platform_driver imx8mm_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .name = "imx8mm-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .of_match_table = of_match_ptr(imx8mm_pinctrl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .probe = imx8mm_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int __init imx8mm_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return platform_driver_register(&imx8mm_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) arch_initcall(imx8mm_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_DESCRIPTION("NXP i.MX8MM pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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