^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright (C) 2017 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: Dong Aisheng <aisheng.dong@nxp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-imx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum imx7ulp_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) IMX7ULP_PAD_PTC0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) IMX7ULP_PAD_PTC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) IMX7ULP_PAD_PTC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) IMX7ULP_PAD_PTC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) IMX7ULP_PAD_PTC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) IMX7ULP_PAD_PTC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) IMX7ULP_PAD_PTC6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) IMX7ULP_PAD_PTC7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) IMX7ULP_PAD_PTC8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) IMX7ULP_PAD_PTC9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) IMX7ULP_PAD_PTC10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) IMX7ULP_PAD_PTC11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) IMX7ULP_PAD_PTC12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) IMX7ULP_PAD_PTC13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) IMX7ULP_PAD_PTC14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) IMX7ULP_PAD_PTC15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) IMX7ULP_PAD_PTC16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) IMX7ULP_PAD_PTC17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) IMX7ULP_PAD_PTC18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) IMX7ULP_PAD_PTC19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) IMX7ULP_PAD_RESERVE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) IMX7ULP_PAD_RESERVE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) IMX7ULP_PAD_RESERVE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) IMX7ULP_PAD_RESERVE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) IMX7ULP_PAD_RESERVE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) IMX7ULP_PAD_RESERVE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) IMX7ULP_PAD_RESERVE6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) IMX7ULP_PAD_RESERVE7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) IMX7ULP_PAD_RESERVE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) IMX7ULP_PAD_RESERVE9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) IMX7ULP_PAD_RESERVE10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) IMX7ULP_PAD_RESERVE11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) IMX7ULP_PAD_PTD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) IMX7ULP_PAD_PTD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) IMX7ULP_PAD_PTD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) IMX7ULP_PAD_PTD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) IMX7ULP_PAD_PTD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) IMX7ULP_PAD_PTD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) IMX7ULP_PAD_PTD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) IMX7ULP_PAD_PTD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) IMX7ULP_PAD_PTD8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) IMX7ULP_PAD_PTD9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) IMX7ULP_PAD_PTD10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) IMX7ULP_PAD_PTD11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) IMX7ULP_PAD_RESERVE12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) IMX7ULP_PAD_RESERVE13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) IMX7ULP_PAD_RESERVE14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) IMX7ULP_PAD_RESERVE15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) IMX7ULP_PAD_RESERVE16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) IMX7ULP_PAD_RESERVE17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) IMX7ULP_PAD_RESERVE18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) IMX7ULP_PAD_RESERVE19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) IMX7ULP_PAD_RESERVE20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) IMX7ULP_PAD_RESERVE21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) IMX7ULP_PAD_RESERVE22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) IMX7ULP_PAD_RESERVE23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) IMX7ULP_PAD_RESERVE24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) IMX7ULP_PAD_RESERVE25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) IMX7ULP_PAD_RESERVE26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) IMX7ULP_PAD_RESERVE27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) IMX7ULP_PAD_RESERVE28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) IMX7ULP_PAD_RESERVE29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) IMX7ULP_PAD_RESERVE30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) IMX7ULP_PAD_RESERVE31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) IMX7ULP_PAD_PTE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) IMX7ULP_PAD_PTE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) IMX7ULP_PAD_PTE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) IMX7ULP_PAD_PTE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) IMX7ULP_PAD_PTE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) IMX7ULP_PAD_PTE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) IMX7ULP_PAD_PTE6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) IMX7ULP_PAD_PTE7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) IMX7ULP_PAD_PTE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) IMX7ULP_PAD_PTE9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) IMX7ULP_PAD_PTE10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) IMX7ULP_PAD_PTE11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) IMX7ULP_PAD_PTE12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) IMX7ULP_PAD_PTE13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) IMX7ULP_PAD_PTE14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) IMX7ULP_PAD_PTE15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) IMX7ULP_PAD_RESERVE32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) IMX7ULP_PAD_RESERVE33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) IMX7ULP_PAD_RESERVE34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) IMX7ULP_PAD_RESERVE35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) IMX7ULP_PAD_RESERVE36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) IMX7ULP_PAD_RESERVE37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) IMX7ULP_PAD_RESERVE38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) IMX7ULP_PAD_RESERVE39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) IMX7ULP_PAD_RESERVE40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) IMX7ULP_PAD_RESERVE41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) IMX7ULP_PAD_RESERVE42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) IMX7ULP_PAD_RESERVE43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) IMX7ULP_PAD_RESERVE44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) IMX7ULP_PAD_RESERVE45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) IMX7ULP_PAD_RESERVE46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) IMX7ULP_PAD_RESERVE47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) IMX7ULP_PAD_PTF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) IMX7ULP_PAD_PTF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) IMX7ULP_PAD_PTF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) IMX7ULP_PAD_PTF3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) IMX7ULP_PAD_PTF4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) IMX7ULP_PAD_PTF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) IMX7ULP_PAD_PTF6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) IMX7ULP_PAD_PTF7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) IMX7ULP_PAD_PTF8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) IMX7ULP_PAD_PTF9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) IMX7ULP_PAD_PTF10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) IMX7ULP_PAD_PTF11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) IMX7ULP_PAD_PTF12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) IMX7ULP_PAD_PTF13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) IMX7ULP_PAD_PTF14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) IMX7ULP_PAD_PTF15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) IMX7ULP_PAD_PTF16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) IMX7ULP_PAD_PTF17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) IMX7ULP_PAD_PTF18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) IMX7ULP_PAD_PTF19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Pad names for the pinmux subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define BM_OBE_ENABLED BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define BM_IBE_ENABLED BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define BM_MUX_MODE 0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define BP_MUX_MODE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned offset, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) const struct imx_pin_reg *pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pin_reg = &ipctl->pin_regs[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (pin_reg->mux_reg == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) reg = readl(ipctl->base + pin_reg->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) writel(reg, ipctl->base + pin_reg->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .pins = imx7ulp_pinctrl_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .mux_mask = BM_MUX_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .mux_shift = BP_MUX_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const struct of_device_id imx7ulp_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { .compatible = "fsl,imx7ulp-iomuxc1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int imx7ulp_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return imx_pinctrl_probe(pdev, &imx7ulp_pinctrl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct platform_driver imx7ulp_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .name = "imx7ulp-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .of_match_table = of_match_ptr(imx7ulp_pinctrl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .probe = imx7ulp_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int __init imx7ulp_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return platform_driver_register(&imx7ulp_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) arch_initcall(imx7ulp_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags