^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Freescale imx6ul pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Author: Anson Huang <Anson.Huang@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright (C) 2015 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pinctrl-imx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum imx6ul_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MX6UL_PAD_RESERVE0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MX6UL_PAD_RESERVE1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MX6UL_PAD_RESERVE2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MX6UL_PAD_RESERVE3 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MX6UL_PAD_RESERVE4 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MX6UL_PAD_RESERVE5 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MX6UL_PAD_RESERVE6 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MX6UL_PAD_RESERVE7 = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MX6UL_PAD_RESERVE8 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MX6UL_PAD_RESERVE9 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MX6UL_PAD_RESERVE10 = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MX6UL_PAD_SNVS_TAMPER4 = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MX6UL_PAD_RESERVE12 = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MX6UL_PAD_RESERVE13 = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MX6UL_PAD_RESERVE14 = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MX6UL_PAD_RESERVE15 = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MX6UL_PAD_RESERVE16 = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MX6UL_PAD_JTAG_MOD = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MX6UL_PAD_JTAG_TMS = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MX6UL_PAD_JTAG_TDO = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MX6UL_PAD_JTAG_TDI = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MX6UL_PAD_JTAG_TCK = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MX6UL_PAD_JTAG_TRST_B = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MX6UL_PAD_GPIO1_IO00 = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MX6UL_PAD_GPIO1_IO01 = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MX6UL_PAD_GPIO1_IO02 = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MX6UL_PAD_GPIO1_IO03 = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MX6UL_PAD_GPIO1_IO04 = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MX6UL_PAD_GPIO1_IO05 = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MX6UL_PAD_GPIO1_IO06 = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MX6UL_PAD_GPIO1_IO07 = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MX6UL_PAD_GPIO1_IO08 = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MX6UL_PAD_GPIO1_IO09 = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MX6UL_PAD_UART1_TX_DATA = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MX6UL_PAD_UART1_RX_DATA = 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MX6UL_PAD_UART1_CTS_B = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MX6UL_PAD_UART1_RTS_B = 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MX6UL_PAD_UART2_TX_DATA = 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MX6UL_PAD_UART2_RX_DATA = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MX6UL_PAD_UART2_CTS_B = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MX6UL_PAD_UART2_RTS_B = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MX6UL_PAD_UART3_TX_DATA = 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MX6UL_PAD_UART3_RX_DATA = 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MX6UL_PAD_UART3_CTS_B = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MX6UL_PAD_UART3_RTS_B = 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MX6UL_PAD_UART4_TX_DATA = 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MX6UL_PAD_UART4_RX_DATA = 46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MX6UL_PAD_UART5_TX_DATA = 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MX6UL_PAD_UART5_RX_DATA = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MX6UL_PAD_ENET1_RX_DATA0 = 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MX6UL_PAD_ENET1_RX_DATA1 = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MX6UL_PAD_ENET1_RX_EN = 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MX6UL_PAD_ENET1_TX_DATA0 = 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MX6UL_PAD_ENET1_TX_DATA1 = 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MX6UL_PAD_ENET1_TX_EN = 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MX6UL_PAD_ENET1_TX_CLK = 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MX6UL_PAD_ENET1_RX_ER = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MX6UL_PAD_ENET2_RX_DATA0 = 57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MX6UL_PAD_ENET2_RX_DATA1 = 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MX6UL_PAD_ENET2_RX_EN = 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MX6UL_PAD_ENET2_TX_DATA0 = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MX6UL_PAD_ENET2_TX_DATA1 = 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MX6UL_PAD_ENET2_TX_EN = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MX6UL_PAD_ENET2_TX_CLK = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MX6UL_PAD_ENET2_RX_ER = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MX6UL_PAD_LCD_CLK = 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MX6UL_PAD_LCD_ENABLE = 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MX6UL_PAD_LCD_HSYNC = 67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MX6UL_PAD_LCD_VSYNC = 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MX6UL_PAD_LCD_RESET = 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MX6UL_PAD_LCD_DATA00 = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MX6UL_PAD_LCD_DATA01 = 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MX6UL_PAD_LCD_DATA02 = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MX6UL_PAD_LCD_DATA03 = 73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MX6UL_PAD_LCD_DATA04 = 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MX6UL_PAD_LCD_DATA05 = 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MX6UL_PAD_LCD_DATA06 = 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MX6UL_PAD_LCD_DATA07 = 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MX6UL_PAD_LCD_DATA08 = 78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MX6UL_PAD_LCD_DATA09 = 79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MX6UL_PAD_LCD_DATA10 = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MX6UL_PAD_LCD_DATA11 = 81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MX6UL_PAD_LCD_DATA12 = 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MX6UL_PAD_LCD_DATA13 = 83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MX6UL_PAD_LCD_DATA14 = 84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MX6UL_PAD_LCD_DATA15 = 85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MX6UL_PAD_LCD_DATA16 = 86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MX6UL_PAD_LCD_DATA17 = 87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MX6UL_PAD_LCD_DATA18 = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MX6UL_PAD_LCD_DATA19 = 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MX6UL_PAD_LCD_DATA20 = 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MX6UL_PAD_LCD_DATA21 = 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MX6UL_PAD_LCD_DATA22 = 92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MX6UL_PAD_LCD_DATA23 = 93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MX6UL_PAD_NAND_RE_B = 94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MX6UL_PAD_NAND_WE_B = 95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MX6UL_PAD_NAND_DATA00 = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MX6UL_PAD_NAND_DATA01 = 97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MX6UL_PAD_NAND_DATA02 = 98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MX6UL_PAD_NAND_DATA03 = 99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MX6UL_PAD_NAND_DATA04 = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MX6UL_PAD_NAND_DATA05 = 101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MX6UL_PAD_NAND_DATA06 = 102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MX6UL_PAD_NAND_DATA07 = 103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MX6UL_PAD_NAND_ALE = 104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MX6UL_PAD_NAND_WP_B = 105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MX6UL_PAD_NAND_READY_B = 106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MX6UL_PAD_NAND_CE0_B = 107,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MX6UL_PAD_NAND_CE1_B = 108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MX6UL_PAD_NAND_CLE = 109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MX6UL_PAD_NAND_DQS = 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MX6UL_PAD_SD1_CMD = 111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MX6UL_PAD_SD1_CLK = 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MX6UL_PAD_SD1_DATA0 = 113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MX6UL_PAD_SD1_DATA1 = 114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MX6UL_PAD_SD1_DATA2 = 115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MX6UL_PAD_SD1_DATA3 = 116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MX6UL_PAD_CSI_MCLK = 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MX6UL_PAD_CSI_PIXCLK = 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MX6UL_PAD_CSI_VSYNC = 119,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MX6UL_PAD_CSI_HSYNC = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MX6UL_PAD_CSI_DATA00 = 121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MX6UL_PAD_CSI_DATA01 = 122,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MX6UL_PAD_CSI_DATA02 = 123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MX6UL_PAD_CSI_DATA03 = 124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MX6UL_PAD_CSI_DATA04 = 125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MX6UL_PAD_CSI_DATA05 = 126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MX6UL_PAD_CSI_DATA06 = 127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MX6UL_PAD_CSI_DATA07 = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) enum imx6ull_lpsr_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MX6ULL_PAD_BOOT_MODE0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MX6ULL_PAD_BOOT_MODE1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MX6ULL_PAD_SNVS_TAMPER0 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MX6ULL_PAD_SNVS_TAMPER1 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MX6ULL_PAD_SNVS_TAMPER2 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MX6ULL_PAD_SNVS_TAMPER3 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MX6ULL_PAD_SNVS_TAMPER4 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MX6ULL_PAD_SNVS_TAMPER5 = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MX6ULL_PAD_SNVS_TAMPER6 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MX6ULL_PAD_SNVS_TAMPER7 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MX6ULL_PAD_SNVS_TAMPER8 = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MX6ULL_PAD_SNVS_TAMPER9 = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Pad names for the pinmux subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static const struct pinctrl_pin_desc imx6ul_pinctrl_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) IMX_PINCTRL_PIN(MX6UL_PAD_SNVS_TAMPER4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) IMX_PINCTRL_PIN(MX6UL_PAD_RESERVE16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_MOD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TMS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TDI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) IMX_PINCTRL_PIN(MX6UL_PAD_JTAG_TRST_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) IMX_PINCTRL_PIN(MX6UL_PAD_GPIO1_IO09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) IMX_PINCTRL_PIN(MX6UL_PAD_UART1_TX_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RX_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) IMX_PINCTRL_PIN(MX6UL_PAD_UART1_CTS_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) IMX_PINCTRL_PIN(MX6UL_PAD_UART1_RTS_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) IMX_PINCTRL_PIN(MX6UL_PAD_UART2_TX_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RX_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) IMX_PINCTRL_PIN(MX6UL_PAD_UART2_CTS_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) IMX_PINCTRL_PIN(MX6UL_PAD_UART2_RTS_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) IMX_PINCTRL_PIN(MX6UL_PAD_UART3_TX_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RX_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) IMX_PINCTRL_PIN(MX6UL_PAD_UART3_CTS_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) IMX_PINCTRL_PIN(MX6UL_PAD_UART3_RTS_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) IMX_PINCTRL_PIN(MX6UL_PAD_UART4_TX_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) IMX_PINCTRL_PIN(MX6UL_PAD_UART4_RX_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) IMX_PINCTRL_PIN(MX6UL_PAD_UART5_TX_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) IMX_PINCTRL_PIN(MX6UL_PAD_UART5_RX_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_TX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) IMX_PINCTRL_PIN(MX6UL_PAD_ENET1_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_TX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) IMX_PINCTRL_PIN(MX6UL_PAD_ENET2_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) IMX_PINCTRL_PIN(MX6UL_PAD_LCD_DATA23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_RE_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WE_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DATA07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_ALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_WP_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_READY_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CE1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_CLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) IMX_PINCTRL_PIN(MX6UL_PAD_NAND_DQS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) IMX_PINCTRL_PIN(MX6UL_PAD_SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) IMX_PINCTRL_PIN(MX6UL_PAD_SD1_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) IMX_PINCTRL_PIN(MX6UL_PAD_CSI_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) IMX_PINCTRL_PIN(MX6UL_PAD_CSI_PIXCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) IMX_PINCTRL_PIN(MX6UL_PAD_CSI_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) IMX_PINCTRL_PIN(MX6UL_PAD_CSI_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) IMX_PINCTRL_PIN(MX6UL_PAD_CSI_DATA07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* pad for i.MX6ULL lpsr pinmux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const struct pinctrl_pin_desc imx6ull_snvs_pinctrl_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) IMX_PINCTRL_PIN(MX6ULL_PAD_BOOT_MODE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) IMX_PINCTRL_PIN(MX6ULL_PAD_SNVS_TAMPER9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct imx_pinctrl_soc_info imx6ul_pinctrl_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .pins = imx6ul_pinctrl_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .npins = ARRAY_SIZE(imx6ul_pinctrl_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .gpr_compatible = "fsl,imx6ul-iomuxc-gpr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct imx_pinctrl_soc_info imx6ull_snvs_pinctrl_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .pins = imx6ull_snvs_pinctrl_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .npins = ARRAY_SIZE(imx6ull_snvs_pinctrl_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .flags = ZERO_OFFSET_VALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct of_device_id imx6ul_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { .compatible = "fsl,imx6ul-iomuxc", .data = &imx6ul_pinctrl_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { .compatible = "fsl,imx6ull-iomuxc-snvs", .data = &imx6ull_snvs_pinctrl_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int imx6ul_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) const struct imx_pinctrl_soc_info *pinctrl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) pinctrl_info = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!pinctrl_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return imx_pinctrl_probe(pdev, pinctrl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static struct platform_driver imx6ul_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .name = "imx6ul-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .of_match_table = of_match_ptr(imx6ul_pinctrl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .probe = imx6ul_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static int __init imx6ul_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return platform_driver_register(&imx6ul_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) arch_initcall(imx6ul_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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