^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright 2017-2018 NXP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pinctrl-imx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) enum imx6sll_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) MX6SLL_PAD_RESERVE0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MX6SLL_PAD_RESERVE1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MX6SLL_PAD_RESERVE2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MX6SLL_PAD_RESERVE3 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MX6SLL_PAD_RESERVE4 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MX6SLL_PAD_WDOG_B = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MX6SLL_PAD_REF_CLK_24M = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MX6SLL_PAD_REF_CLK_32K = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MX6SLL_PAD_PWM1 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MX6SLL_PAD_KEY_COL0 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MX6SLL_PAD_KEY_ROW0 = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MX6SLL_PAD_KEY_COL1 = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MX6SLL_PAD_KEY_ROW1 = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MX6SLL_PAD_KEY_COL2 = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MX6SLL_PAD_KEY_ROW2 = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MX6SLL_PAD_KEY_COL3 = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MX6SLL_PAD_KEY_ROW3 = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MX6SLL_PAD_KEY_COL4 = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MX6SLL_PAD_KEY_ROW4 = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MX6SLL_PAD_KEY_COL5 = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MX6SLL_PAD_KEY_ROW5 = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MX6SLL_PAD_KEY_COL6 = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MX6SLL_PAD_KEY_ROW6 = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MX6SLL_PAD_KEY_COL7 = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MX6SLL_PAD_KEY_ROW7 = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MX6SLL_PAD_EPDC_DATA00 = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MX6SLL_PAD_EPDC_DATA01 = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MX6SLL_PAD_EPDC_DATA02 = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MX6SLL_PAD_EPDC_DATA03 = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MX6SLL_PAD_EPDC_DATA04 = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MX6SLL_PAD_EPDC_DATA05 = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MX6SLL_PAD_EPDC_DATA06 = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MX6SLL_PAD_EPDC_DATA07 = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MX6SLL_PAD_EPDC_DATA08 = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MX6SLL_PAD_EPDC_DATA09 = 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MX6SLL_PAD_EPDC_DATA10 = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MX6SLL_PAD_EPDC_DATA11 = 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MX6SLL_PAD_EPDC_DATA12 = 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MX6SLL_PAD_EPDC_DATA13 = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MX6SLL_PAD_EPDC_DATA14 = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MX6SLL_PAD_EPDC_DATA15 = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MX6SLL_PAD_EPDC_SDCLK = 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MX6SLL_PAD_EPDC_SDLE = 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MX6SLL_PAD_EPDC_SDOE = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MX6SLL_PAD_EPDC_SDSHR = 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MX6SLL_PAD_EPDC_SDCE0 = 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MX6SLL_PAD_EPDC_SDCE1 = 46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MX6SLL_PAD_EPDC_SDCE2 = 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MX6SLL_PAD_EPDC_SDCE3 = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MX6SLL_PAD_EPDC_GDCLK = 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MX6SLL_PAD_EPDC_GDOE = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MX6SLL_PAD_EPDC_GDRL = 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MX6SLL_PAD_EPDC_GDSP = 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MX6SLL_PAD_EPDC_VCOM0 = 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MX6SLL_PAD_EPDC_VCOM1 = 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MX6SLL_PAD_EPDC_BDR0 = 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MX6SLL_PAD_EPDC_BDR1 = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MX6SLL_PAD_EPDC_PWR_CTRL0 = 57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MX6SLL_PAD_EPDC_PWR_CTRL1 = 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MX6SLL_PAD_EPDC_PWR_CTRL2 = 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MX6SLL_PAD_EPDC_PWR_CTRL3 = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MX6SLL_PAD_EPDC_PWR_COM = 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MX6SLL_PAD_EPDC_PWR_INT = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MX6SLL_PAD_EPDC_PWR_STAT = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MX6SLL_PAD_EPDC_PWR_WAKE = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MX6SLL_PAD_LCD_CLK = 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MX6SLL_PAD_LCD_ENABLE = 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MX6SLL_PAD_LCD_HSYNC = 67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MX6SLL_PAD_LCD_VSYNC = 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MX6SLL_PAD_LCD_RESET = 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MX6SLL_PAD_LCD_DATA00 = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MX6SLL_PAD_LCD_DATA01 = 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MX6SLL_PAD_LCD_DATA02 = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MX6SLL_PAD_LCD_DATA03 = 73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MX6SLL_PAD_LCD_DATA04 = 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MX6SLL_PAD_LCD_DATA05 = 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MX6SLL_PAD_LCD_DATA06 = 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MX6SLL_PAD_LCD_DATA07 = 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MX6SLL_PAD_LCD_DATA08 = 78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MX6SLL_PAD_LCD_DATA09 = 79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MX6SLL_PAD_LCD_DATA10 = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MX6SLL_PAD_LCD_DATA11 = 81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MX6SLL_PAD_LCD_DATA12 = 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MX6SLL_PAD_LCD_DATA13 = 83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MX6SLL_PAD_LCD_DATA14 = 84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MX6SLL_PAD_LCD_DATA15 = 85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MX6SLL_PAD_LCD_DATA16 = 86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MX6SLL_PAD_LCD_DATA17 = 87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MX6SLL_PAD_LCD_DATA18 = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MX6SLL_PAD_LCD_DATA19 = 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MX6SLL_PAD_LCD_DATA20 = 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MX6SLL_PAD_LCD_DATA21 = 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MX6SLL_PAD_LCD_DATA22 = 92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MX6SLL_PAD_LCD_DATA23 = 93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MX6SLL_PAD_AUD_RXFS = 94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MX6SLL_PAD_AUD_RXC = 95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MX6SLL_PAD_AUD_RXD = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MX6SLL_PAD_AUD_TXC = 97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MX6SLL_PAD_AUD_TXFS = 98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MX6SLL_PAD_AUD_TXD = 99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MX6SLL_PAD_AUD_MCLK = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MX6SLL_PAD_UART1_RXD = 101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MX6SLL_PAD_UART1_TXD = 102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MX6SLL_PAD_I2C1_SCL = 103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MX6SLL_PAD_I2C1_SDA = 104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MX6SLL_PAD_I2C2_SCL = 105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MX6SLL_PAD_I2C2_SDA = 106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MX6SLL_PAD_ECSPI1_SCLK = 107,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MX6SLL_PAD_ECSPI1_MOSI = 108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MX6SLL_PAD_ECSPI1_MISO = 109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MX6SLL_PAD_ECSPI1_SS0 = 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MX6SLL_PAD_ECSPI2_SCLK = 111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MX6SLL_PAD_ECSPI2_MOSI = 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MX6SLL_PAD_ECSPI2_MISO = 113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MX6SLL_PAD_ECSPI2_SS0 = 114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MX6SLL_PAD_SD1_CLK = 115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MX6SLL_PAD_SD1_CMD = 116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MX6SLL_PAD_SD1_DATA0 = 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MX6SLL_PAD_SD1_DATA1 = 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MX6SLL_PAD_SD1_DATA2 = 119,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MX6SLL_PAD_SD1_DATA3 = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MX6SLL_PAD_SD1_DATA4 = 121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MX6SLL_PAD_SD1_DATA5 = 122,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MX6SLL_PAD_SD1_DATA6 = 123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MX6SLL_PAD_SD1_DATA7 = 124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MX6SLL_PAD_SD2_RESET = 125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MX6SLL_PAD_SD2_CLK = 126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MX6SLL_PAD_SD2_CMD = 127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MX6SLL_PAD_SD2_DATA0 = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MX6SLL_PAD_SD2_DATA1 = 129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MX6SLL_PAD_SD2_DATA2 = 130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MX6SLL_PAD_SD2_DATA3 = 131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MX6SLL_PAD_SD2_DATA4 = 132,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MX6SLL_PAD_SD2_DATA5 = 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MX6SLL_PAD_SD2_DATA6 = 134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MX6SLL_PAD_SD2_DATA7 = 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MX6SLL_PAD_SD3_CLK = 136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MX6SLL_PAD_SD3_CMD = 137,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MX6SLL_PAD_SD3_DATA0 = 138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MX6SLL_PAD_SD3_DATA1 = 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MX6SLL_PAD_SD3_DATA2 = 140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MX6SLL_PAD_SD3_DATA3 = 141,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MX6SLL_PAD_GPIO4_IO20 = 142,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MX6SLL_PAD_GPIO4_IO21 = 143,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MX6SLL_PAD_GPIO4_IO19 = 144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MX6SLL_PAD_GPIO4_IO25 = 145,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MX6SLL_PAD_GPIO4_IO18 = 146,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MX6SLL_PAD_GPIO4_IO24 = 147,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MX6SLL_PAD_GPIO4_IO23 = 148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MX6SLL_PAD_GPIO4_IO17 = 149,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MX6SLL_PAD_GPIO4_IO22 = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MX6SLL_PAD_GPIO4_IO16 = 151,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MX6SLL_PAD_GPIO4_IO26 = 152,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Pad names for the pinmux subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct pinctrl_pin_desc imx6sll_pinctrl_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) IMX_PINCTRL_PIN(MX6SLL_PAD_WDOG_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_24M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_32K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) IMX_PINCTRL_PIN(MX6SLL_PAD_PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDOE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDSHR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDOE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDSP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_COM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_INT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_STAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_WAKE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_ENABLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXFS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXFS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct imx_pinctrl_soc_info imx6sll_pinctrl_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .pins = imx6sll_pinctrl_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .npins = ARRAY_SIZE(imx6sll_pinctrl_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .gpr_compatible = "fsl,imx6sll-iomuxc-gpr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const struct of_device_id imx6sll_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { .compatible = "fsl,imx6sll-iomuxc", .data = &imx6sll_pinctrl_info, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int imx6sll_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return imx_pinctrl_probe(pdev, &imx6sll_pinctrl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static struct platform_driver imx6sll_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .name = "imx6sll-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .of_match_table = of_match_ptr(imx6sll_pinctrl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .probe = imx6sll_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int __init imx6sll_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return platform_driver_register(&imx6sll_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) arch_initcall(imx6sll_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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