Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // imx50 pinctrl driver based on imx pinmux core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Copyright (C) 2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Copyright (C) 2012 Linaro, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "pinctrl-imx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) enum imx50_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	MX50_PAD_RESERVE0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	MX50_PAD_RESERVE1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	MX50_PAD_RESERVE2 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	MX50_PAD_RESERVE3 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	MX50_PAD_RESERVE4 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	MX50_PAD_RESERVE5 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	MX50_PAD_RESERVE6 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	MX50_PAD_RESERVE7 = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	MX50_PAD_KEY_COL0 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	MX50_PAD_KEY_ROW0 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	MX50_PAD_KEY_COL1 = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	MX50_PAD_KEY_ROW1 = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	MX50_PAD_KEY_COL2 = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	MX50_PAD_KEY_ROW2 = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	MX50_PAD_KEY_COL3 = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	MX50_PAD_KEY_ROW3 = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	MX50_PAD_I2C1_SCL = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	MX50_PAD_I2C1_SDA = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	MX50_PAD_I2C2_SCL = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	MX50_PAD_I2C2_SDA = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	MX50_PAD_I2C3_SCL = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	MX50_PAD_I2C3_SDA = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	MX50_PAD_PWM1 = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	MX50_PAD_PWM2 = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	MX50_PAD_0WIRE = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	MX50_PAD_EPITO = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	MX50_PAD_WDOG = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	MX50_PAD_SSI_TXFS = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	MX50_PAD_SSI_TXC = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	MX50_PAD_SSI_TXD = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	MX50_PAD_SSI_RXD = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	MX50_PAD_SSI_RXF = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	MX50_PAD_SSI_RXC = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	MX50_PAD_UART1_TXD = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	MX50_PAD_UART1_RXD = 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	MX50_PAD_UART1_CTS = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	MX50_PAD_UART1_RTS = 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	MX50_PAD_UART2_TXD = 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	MX50_PAD_UART2_RXD = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	MX50_PAD_UART2_CTS = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	MX50_PAD_UART2_RTS = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	MX50_PAD_UART3_TXD = 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	MX50_PAD_UART3_RXD = 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	MX50_PAD_UART4_TXD = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	MX50_PAD_UART4_RXD = 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	MX50_PAD_CSPI_CLK = 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	MX50_PAD_CSPI_MOSI = 46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	MX50_PAD_CSPI_MISO = 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	MX50_PAD_CSPI_SS0 = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	MX50_PAD_ECSPI1_CLK = 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	MX50_PAD_ECSPI1_MOSI = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	MX50_PAD_ECSPI1_MISO = 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	MX50_PAD_ECSPI1_SS0 = 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	MX50_PAD_ECSPI2_CLK = 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	MX50_PAD_ECSPI2_MOSI = 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	MX50_PAD_ECSPI2_MISO = 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	MX50_PAD_ECSPI2_SS0 = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	MX50_PAD_SD1_CLK = 57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	MX50_PAD_SD1_CMD = 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	MX50_PAD_SD1_D0 = 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	MX50_PAD_SD1_D1 = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	MX50_PAD_SD1_D2 = 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	MX50_PAD_SD1_D3 = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	MX50_PAD_SD2_CLK = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	MX50_PAD_SD2_CMD = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	MX50_PAD_SD2_D0 = 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	MX50_PAD_SD2_D1 = 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	MX50_PAD_SD2_D2 = 67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	MX50_PAD_SD2_D3 = 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	MX50_PAD_SD2_D4 = 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	MX50_PAD_SD2_D5 = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	MX50_PAD_SD2_D6 = 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	MX50_PAD_SD2_D7 = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	MX50_PAD_SD2_WP = 73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	MX50_PAD_SD2_CD = 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	MX50_PAD_DISP_D0 = 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	MX50_PAD_DISP_D1 = 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	MX50_PAD_DISP_D2 = 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	MX50_PAD_DISP_D3 = 78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	MX50_PAD_DISP_D4 = 79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	MX50_PAD_DISP_D5 = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	MX50_PAD_DISP_D6 = 81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	MX50_PAD_DISP_D7 = 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	MX50_PAD_DISP_WR = 83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	MX50_PAD_DISP_RD = 84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	MX50_PAD_DISP_RS = 85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	MX50_PAD_DISP_CS = 86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	MX50_PAD_DISP_BUSY = 87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	MX50_PAD_DISP_RESET = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	MX50_PAD_SD3_CLK = 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	MX50_PAD_SD3_CMD = 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	MX50_PAD_SD3_D0 = 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	MX50_PAD_SD3_D1 = 92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	MX50_PAD_SD3_D2 = 93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	MX50_PAD_SD3_D3 = 94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	MX50_PAD_SD3_D4 = 95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	MX50_PAD_SD3_D5 = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	MX50_PAD_SD3_D6 = 97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	MX50_PAD_SD3_D7 = 98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	MX50_PAD_SD3_WP = 99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	MX50_PAD_DISP_D8 = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	MX50_PAD_DISP_D9 = 101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	MX50_PAD_DISP_D10 = 102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	MX50_PAD_DISP_D11 = 103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	MX50_PAD_DISP_D12 = 104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	MX50_PAD_DISP_D13 = 105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	MX50_PAD_DISP_D14 = 106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	MX50_PAD_DISP_D15 = 107,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	MX50_PAD_EPDC_D0 = 108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	MX50_PAD_EPDC_D1 = 109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	MX50_PAD_EPDC_D2 = 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	MX50_PAD_EPDC_D3 = 111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	MX50_PAD_EPDC_D4 = 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	MX50_PAD_EPDC_D5 = 113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	MX50_PAD_EPDC_D6 = 114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	MX50_PAD_EPDC_D7 = 115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	MX50_PAD_EPDC_D8 = 116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	MX50_PAD_EPDC_D9 = 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	MX50_PAD_EPDC_D10 = 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	MX50_PAD_EPDC_D11 = 119,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	MX50_PAD_EPDC_D12 = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	MX50_PAD_EPDC_D13 = 121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	MX50_PAD_EPDC_D14 = 122,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	MX50_PAD_EPDC_D15 = 123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	MX50_PAD_EPDC_GDCLK = 124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	MX50_PAD_EPDC_GDSP = 125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	MX50_PAD_EPDC_GDOE = 126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	MX50_PAD_EPDC_GDRL = 127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	MX50_PAD_EPDC_SDCLK = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	MX50_PAD_EPDC_SDOEZ = 129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	MX50_PAD_EPDC_SDOED = 130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	MX50_PAD_EPDC_SDOE = 131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	MX50_PAD_EPDC_SDLE = 132,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	MX50_PAD_EPDC_SDCLKN = 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	MX50_PAD_EPDC_SDSHR = 134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	MX50_PAD_EPDC_PWRCOM = 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	MX50_PAD_EPDC_PWRSTAT = 136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	MX50_PAD_EPDC_PWRCTRL0 = 137,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	MX50_PAD_EPDC_PWRCTRL1 = 138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	MX50_PAD_EPDC_PWRCTRL2 = 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	MX50_PAD_EPDC_PWRCTRL3 = 140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	MX50_PAD_EPDC_VCOM0 = 141,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	MX50_PAD_EPDC_VCOM1 = 142,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	MX50_PAD_EPDC_BDR0 = 143,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	MX50_PAD_EPDC_BDR1 = 144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	MX50_PAD_EPDC_SDCE0 = 145,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	MX50_PAD_EPDC_SDCE1 = 146,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	MX50_PAD_EPDC_SDCE2 = 147,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	MX50_PAD_EPDC_SDCE3 = 148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	MX50_PAD_EPDC_SDCE4 = 149,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	MX50_PAD_EPDC_SDCE5 = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	MX50_PAD_EIM_DA0 = 151,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	MX50_PAD_EIM_DA1 = 152,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	MX50_PAD_EIM_DA2 = 153,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	MX50_PAD_EIM_DA3 = 154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	MX50_PAD_EIM_DA4 = 155,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	MX50_PAD_EIM_DA5 = 156,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	MX50_PAD_EIM_DA6 = 157,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	MX50_PAD_EIM_DA7 = 158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	MX50_PAD_EIM_DA8 = 159,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	MX50_PAD_EIM_DA9 = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	MX50_PAD_EIM_DA10 = 161,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	MX50_PAD_EIM_DA11 = 162,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	MX50_PAD_EIM_DA12 = 163,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	MX50_PAD_EIM_DA13 = 164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	MX50_PAD_EIM_DA14 = 165,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	MX50_PAD_EIM_DA15 = 166,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	MX50_PAD_EIM_CS2 = 167,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	MX50_PAD_EIM_CS1 = 168,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	MX50_PAD_EIM_CS0 = 169,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	MX50_PAD_EIM_EB0 = 170,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	MX50_PAD_EIM_EB1 = 171,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	MX50_PAD_EIM_WAIT = 172,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	MX50_PAD_EIM_BCLK = 173,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	MX50_PAD_EIM_RDY = 174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	MX50_PAD_EIM_OE = 175,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	MX50_PAD_EIM_RW = 176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	MX50_PAD_EIM_LBA = 177,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	MX50_PAD_EIM_CRE = 178,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Pad names for the pinmux subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	IMX_PINCTRL_PIN(MX50_PAD_PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	IMX_PINCTRL_PIN(MX50_PAD_PWM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	IMX_PINCTRL_PIN(MX50_PAD_EPITO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	IMX_PINCTRL_PIN(MX50_PAD_WDOG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct imx_pinctrl_soc_info imx50_pinctrl_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	.pins = imx50_pinctrl_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	.npins = ARRAY_SIZE(imx50_pinctrl_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	.gpr_compatible = "fsl,imx50-iomuxc-gpr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct of_device_id imx50_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	{ .compatible = "fsl,imx50-iomuxc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int imx50_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static struct platform_driver imx50_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		.name = "imx50-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		.of_match_table = of_match_ptr(imx50_pinctrl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.probe = imx50_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int __init imx50_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	return platform_driver_register(&imx50_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) arch_initcall(imx50_pinctrl_init);