^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // imx25 pinctrl driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // This driver was mostly copied from the imx51 pinctrl driver which has:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Copyright (C) 2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Copyright (C) 2012 Linaro, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) // Author: Denis Carikli <denis@eukrea.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "pinctrl-imx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum imx25_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MX25_PAD_RESERVE0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MX25_PAD_RESERVE1 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MX25_PAD_A10 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MX25_PAD_A13 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MX25_PAD_A14 = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MX25_PAD_A15 = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MX25_PAD_A16 = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MX25_PAD_A17 = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MX25_PAD_A18 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MX25_PAD_A19 = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MX25_PAD_A20 = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MX25_PAD_A21 = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MX25_PAD_A22 = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MX25_PAD_A23 = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MX25_PAD_A24 = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MX25_PAD_A25 = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MX25_PAD_EB0 = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MX25_PAD_EB1 = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MX25_PAD_OE = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MX25_PAD_CS0 = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MX25_PAD_CS1 = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MX25_PAD_CS4 = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MX25_PAD_CS5 = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MX25_PAD_NF_CE0 = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MX25_PAD_ECB = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MX25_PAD_LBA = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MX25_PAD_BCLK = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MX25_PAD_RW = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MX25_PAD_NFWE_B = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MX25_PAD_NFRE_B = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MX25_PAD_NFALE = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MX25_PAD_NFCLE = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MX25_PAD_NFWP_B = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MX25_PAD_NFRB = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MX25_PAD_D15 = 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MX25_PAD_D14 = 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MX25_PAD_D13 = 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MX25_PAD_D12 = 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MX25_PAD_D11 = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MX25_PAD_D10 = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MX25_PAD_D9 = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MX25_PAD_D8 = 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MX25_PAD_D7 = 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MX25_PAD_D6 = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MX25_PAD_D5 = 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MX25_PAD_D4 = 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MX25_PAD_D3 = 46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MX25_PAD_D2 = 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MX25_PAD_D1 = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MX25_PAD_D0 = 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MX25_PAD_LD0 = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MX25_PAD_LD1 = 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MX25_PAD_LD2 = 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MX25_PAD_LD3 = 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MX25_PAD_LD4 = 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MX25_PAD_LD5 = 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MX25_PAD_LD6 = 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MX25_PAD_LD7 = 57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MX25_PAD_LD8 = 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MX25_PAD_LD9 = 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MX25_PAD_LD10 = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MX25_PAD_LD11 = 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MX25_PAD_LD12 = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MX25_PAD_LD13 = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MX25_PAD_LD14 = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MX25_PAD_LD15 = 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MX25_PAD_HSYNC = 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MX25_PAD_VSYNC = 67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MX25_PAD_LSCLK = 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MX25_PAD_OE_ACD = 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MX25_PAD_CONTRAST = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MX25_PAD_PWM = 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MX25_PAD_CSI_D2 = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MX25_PAD_CSI_D3 = 73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MX25_PAD_CSI_D4 = 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MX25_PAD_CSI_D5 = 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MX25_PAD_CSI_D6 = 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MX25_PAD_CSI_D7 = 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MX25_PAD_CSI_D8 = 78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MX25_PAD_CSI_D9 = 79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MX25_PAD_CSI_MCLK = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MX25_PAD_CSI_VSYNC = 81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MX25_PAD_CSI_HSYNC = 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MX25_PAD_CSI_PIXCLK = 83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MX25_PAD_I2C1_CLK = 84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MX25_PAD_I2C1_DAT = 85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MX25_PAD_CSPI1_MOSI = 86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MX25_PAD_CSPI1_MISO = 87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MX25_PAD_CSPI1_SS0 = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MX25_PAD_CSPI1_SS1 = 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MX25_PAD_CSPI1_SCLK = 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MX25_PAD_CSPI1_RDY = 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MX25_PAD_UART1_RXD = 92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MX25_PAD_UART1_TXD = 93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MX25_PAD_UART1_RTS = 94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MX25_PAD_UART1_CTS = 95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MX25_PAD_UART2_RXD = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MX25_PAD_UART2_TXD = 97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MX25_PAD_UART2_RTS = 98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MX25_PAD_UART2_CTS = 99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MX25_PAD_SD1_CMD = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MX25_PAD_SD1_CLK = 101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MX25_PAD_SD1_DATA0 = 102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MX25_PAD_SD1_DATA1 = 103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MX25_PAD_SD1_DATA2 = 104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MX25_PAD_SD1_DATA3 = 105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MX25_PAD_KPP_ROW0 = 106,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MX25_PAD_KPP_ROW1 = 107,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MX25_PAD_KPP_ROW2 = 108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MX25_PAD_KPP_ROW3 = 109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MX25_PAD_KPP_COL0 = 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MX25_PAD_KPP_COL1 = 111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MX25_PAD_KPP_COL2 = 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MX25_PAD_KPP_COL3 = 113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MX25_PAD_FEC_MDC = 114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MX25_PAD_FEC_MDIO = 115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MX25_PAD_FEC_TDATA0 = 116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MX25_PAD_FEC_TDATA1 = 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MX25_PAD_FEC_TX_EN = 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MX25_PAD_FEC_RDATA0 = 119,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MX25_PAD_FEC_RDATA1 = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MX25_PAD_FEC_RX_DV = 121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MX25_PAD_FEC_TX_CLK = 122,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MX25_PAD_RTCK = 123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MX25_PAD_DE_B = 124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MX25_PAD_GPIO_A = 125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MX25_PAD_GPIO_B = 126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MX25_PAD_GPIO_C = 127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MX25_PAD_GPIO_D = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MX25_PAD_GPIO_E = 129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MX25_PAD_GPIO_F = 130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MX25_PAD_EXT_ARMCLK = 131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MX25_PAD_UPLL_BYPCLK = 132,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MX25_PAD_VSTBY_REQ = 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MX25_PAD_VSTBY_ACK = 134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MX25_PAD_POWER_FAIL = 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MX25_PAD_CLKO = 136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MX25_PAD_BOOT_MODE0 = 137,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MX25_PAD_BOOT_MODE1 = 138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Pad names for the pinmux subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) IMX_PINCTRL_PIN(MX25_PAD_RESERVE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) IMX_PINCTRL_PIN(MX25_PAD_RESERVE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) IMX_PINCTRL_PIN(MX25_PAD_A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) IMX_PINCTRL_PIN(MX25_PAD_A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) IMX_PINCTRL_PIN(MX25_PAD_A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) IMX_PINCTRL_PIN(MX25_PAD_A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) IMX_PINCTRL_PIN(MX25_PAD_A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) IMX_PINCTRL_PIN(MX25_PAD_A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) IMX_PINCTRL_PIN(MX25_PAD_A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) IMX_PINCTRL_PIN(MX25_PAD_A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) IMX_PINCTRL_PIN(MX25_PAD_A20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) IMX_PINCTRL_PIN(MX25_PAD_A21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) IMX_PINCTRL_PIN(MX25_PAD_A22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) IMX_PINCTRL_PIN(MX25_PAD_A23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) IMX_PINCTRL_PIN(MX25_PAD_A24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) IMX_PINCTRL_PIN(MX25_PAD_A25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IMX_PINCTRL_PIN(MX25_PAD_EB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) IMX_PINCTRL_PIN(MX25_PAD_EB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) IMX_PINCTRL_PIN(MX25_PAD_OE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) IMX_PINCTRL_PIN(MX25_PAD_CS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) IMX_PINCTRL_PIN(MX25_PAD_CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) IMX_PINCTRL_PIN(MX25_PAD_CS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) IMX_PINCTRL_PIN(MX25_PAD_CS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) IMX_PINCTRL_PIN(MX25_PAD_NF_CE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) IMX_PINCTRL_PIN(MX25_PAD_ECB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) IMX_PINCTRL_PIN(MX25_PAD_LBA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) IMX_PINCTRL_PIN(MX25_PAD_BCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) IMX_PINCTRL_PIN(MX25_PAD_RW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) IMX_PINCTRL_PIN(MX25_PAD_NFWE_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) IMX_PINCTRL_PIN(MX25_PAD_NFRE_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) IMX_PINCTRL_PIN(MX25_PAD_NFALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) IMX_PINCTRL_PIN(MX25_PAD_NFCLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) IMX_PINCTRL_PIN(MX25_PAD_NFWP_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) IMX_PINCTRL_PIN(MX25_PAD_NFRB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) IMX_PINCTRL_PIN(MX25_PAD_D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) IMX_PINCTRL_PIN(MX25_PAD_D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) IMX_PINCTRL_PIN(MX25_PAD_D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) IMX_PINCTRL_PIN(MX25_PAD_D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) IMX_PINCTRL_PIN(MX25_PAD_D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) IMX_PINCTRL_PIN(MX25_PAD_D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) IMX_PINCTRL_PIN(MX25_PAD_D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) IMX_PINCTRL_PIN(MX25_PAD_D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) IMX_PINCTRL_PIN(MX25_PAD_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) IMX_PINCTRL_PIN(MX25_PAD_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) IMX_PINCTRL_PIN(MX25_PAD_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) IMX_PINCTRL_PIN(MX25_PAD_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) IMX_PINCTRL_PIN(MX25_PAD_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) IMX_PINCTRL_PIN(MX25_PAD_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) IMX_PINCTRL_PIN(MX25_PAD_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) IMX_PINCTRL_PIN(MX25_PAD_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) IMX_PINCTRL_PIN(MX25_PAD_LD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IMX_PINCTRL_PIN(MX25_PAD_LD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) IMX_PINCTRL_PIN(MX25_PAD_LD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) IMX_PINCTRL_PIN(MX25_PAD_LD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) IMX_PINCTRL_PIN(MX25_PAD_LD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) IMX_PINCTRL_PIN(MX25_PAD_LD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) IMX_PINCTRL_PIN(MX25_PAD_LD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) IMX_PINCTRL_PIN(MX25_PAD_LD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) IMX_PINCTRL_PIN(MX25_PAD_LD8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) IMX_PINCTRL_PIN(MX25_PAD_LD9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) IMX_PINCTRL_PIN(MX25_PAD_LD10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) IMX_PINCTRL_PIN(MX25_PAD_LD11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) IMX_PINCTRL_PIN(MX25_PAD_LD12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) IMX_PINCTRL_PIN(MX25_PAD_LD13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) IMX_PINCTRL_PIN(MX25_PAD_LD14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) IMX_PINCTRL_PIN(MX25_PAD_LD15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) IMX_PINCTRL_PIN(MX25_PAD_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) IMX_PINCTRL_PIN(MX25_PAD_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) IMX_PINCTRL_PIN(MX25_PAD_LSCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) IMX_PINCTRL_PIN(MX25_PAD_OE_ACD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) IMX_PINCTRL_PIN(MX25_PAD_CONTRAST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) IMX_PINCTRL_PIN(MX25_PAD_PWM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) IMX_PINCTRL_PIN(MX25_PAD_CSI_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) IMX_PINCTRL_PIN(MX25_PAD_CSI_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) IMX_PINCTRL_PIN(MX25_PAD_CSI_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) IMX_PINCTRL_PIN(MX25_PAD_CSI_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) IMX_PINCTRL_PIN(MX25_PAD_CSI_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) IMX_PINCTRL_PIN(MX25_PAD_CSI_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) IMX_PINCTRL_PIN(MX25_PAD_CSI_D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) IMX_PINCTRL_PIN(MX25_PAD_CSI_D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) IMX_PINCTRL_PIN(MX25_PAD_CSI_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) IMX_PINCTRL_PIN(MX25_PAD_CSI_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) IMX_PINCTRL_PIN(MX25_PAD_CSI_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) IMX_PINCTRL_PIN(MX25_PAD_CSI_PIXCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) IMX_PINCTRL_PIN(MX25_PAD_I2C1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) IMX_PINCTRL_PIN(MX25_PAD_I2C1_DAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) IMX_PINCTRL_PIN(MX25_PAD_CSPI1_RDY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) IMX_PINCTRL_PIN(MX25_PAD_UART1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) IMX_PINCTRL_PIN(MX25_PAD_UART1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) IMX_PINCTRL_PIN(MX25_PAD_UART1_RTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) IMX_PINCTRL_PIN(MX25_PAD_UART1_CTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) IMX_PINCTRL_PIN(MX25_PAD_UART2_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) IMX_PINCTRL_PIN(MX25_PAD_UART2_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) IMX_PINCTRL_PIN(MX25_PAD_UART2_RTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) IMX_PINCTRL_PIN(MX25_PAD_UART2_CTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) IMX_PINCTRL_PIN(MX25_PAD_SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) IMX_PINCTRL_PIN(MX25_PAD_SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) IMX_PINCTRL_PIN(MX25_PAD_KPP_COL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) IMX_PINCTRL_PIN(MX25_PAD_KPP_COL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) IMX_PINCTRL_PIN(MX25_PAD_KPP_COL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) IMX_PINCTRL_PIN(MX25_PAD_KPP_COL3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) IMX_PINCTRL_PIN(MX25_PAD_FEC_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) IMX_PINCTRL_PIN(MX25_PAD_FEC_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) IMX_PINCTRL_PIN(MX25_PAD_FEC_RX_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) IMX_PINCTRL_PIN(MX25_PAD_RTCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) IMX_PINCTRL_PIN(MX25_PAD_DE_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) IMX_PINCTRL_PIN(MX25_PAD_GPIO_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) IMX_PINCTRL_PIN(MX25_PAD_GPIO_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) IMX_PINCTRL_PIN(MX25_PAD_GPIO_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) IMX_PINCTRL_PIN(MX25_PAD_GPIO_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) IMX_PINCTRL_PIN(MX25_PAD_GPIO_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) IMX_PINCTRL_PIN(MX25_PAD_GPIO_F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) IMX_PINCTRL_PIN(MX25_PAD_EXT_ARMCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) IMX_PINCTRL_PIN(MX25_PAD_UPLL_BYPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) IMX_PINCTRL_PIN(MX25_PAD_VSTBY_REQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) IMX_PINCTRL_PIN(MX25_PAD_VSTBY_ACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) IMX_PINCTRL_PIN(MX25_PAD_POWER_FAIL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) IMX_PINCTRL_PIN(MX25_PAD_CLKO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct imx_pinctrl_soc_info imx25_pinctrl_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .pins = imx25_pinctrl_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .npins = ARRAY_SIZE(imx25_pinctrl_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct of_device_id imx25_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { .compatible = "fsl,imx25-iomuxc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int imx25_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return imx_pinctrl_probe(pdev, &imx25_pinctrl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct platform_driver imx25_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .name = "imx25-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .of_match_table = of_match_ptr(imx25_pinctrl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .probe = imx25_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static int __init imx25_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return platform_driver_register(&imx25_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) arch_initcall(imx25_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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