Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // i.MX21 pinctrl driver based on imx pinmux core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "pinctrl-imx1.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define PAD_ID(port, pin)	((port) * 32 + (pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define PA	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define PB	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define PC	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PD	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PE	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PF	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) enum imx21_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	MX21_PAD_LSCLK		= PAD_ID(PA, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	MX21_PAD_LD0		= PAD_ID(PA, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	MX21_PAD_LD1		= PAD_ID(PA, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	MX21_PAD_LD2		= PAD_ID(PA, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	MX21_PAD_LD3		= PAD_ID(PA, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	MX21_PAD_LD4		= PAD_ID(PA, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	MX21_PAD_LD5		= PAD_ID(PA, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	MX21_PAD_LD6		= PAD_ID(PA, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	MX21_PAD_LD7		= PAD_ID(PA, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	MX21_PAD_LD8		= PAD_ID(PA, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	MX21_PAD_LD9		= PAD_ID(PA, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	MX21_PAD_LD10		= PAD_ID(PA, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	MX21_PAD_LD11		= PAD_ID(PA, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	MX21_PAD_LD12		= PAD_ID(PA, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	MX21_PAD_LD13		= PAD_ID(PA, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	MX21_PAD_LD14		= PAD_ID(PA, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	MX21_PAD_LD15		= PAD_ID(PA, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	MX21_PAD_LD16		= PAD_ID(PA, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	MX21_PAD_LD17		= PAD_ID(PA, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	MX21_PAD_REV		= PAD_ID(PA, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	MX21_PAD_CLS		= PAD_ID(PA, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	MX21_PAD_PS		= PAD_ID(PA, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	MX21_PAD_SPL_SPR	= PAD_ID(PA, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	MX21_PAD_HSYNC		= PAD_ID(PA, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	MX21_PAD_VSYNC		= PAD_ID(PA, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	MX21_PAD_CONTRAST	= PAD_ID(PA, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	MX21_PAD_OE_ACD		= PAD_ID(PA, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	MX21_PAD_SD2_D0		= PAD_ID(PB, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	MX21_PAD_SD2_D1		= PAD_ID(PB, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	MX21_PAD_SD2_D2		= PAD_ID(PB, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	MX21_PAD_SD2_D3		= PAD_ID(PB, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	MX21_PAD_SD2_CMD	= PAD_ID(PB, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	MX21_PAD_SD2_CLK	= PAD_ID(PB, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	MX21_PAD_CSI_D0		= PAD_ID(PB, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	MX21_PAD_CSI_D1		= PAD_ID(PB, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	MX21_PAD_CSI_D2		= PAD_ID(PB, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	MX21_PAD_CSI_D3		= PAD_ID(PB, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	MX21_PAD_CSI_D4		= PAD_ID(PB, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	MX21_PAD_CSI_MCLK	= PAD_ID(PB, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	MX21_PAD_CSI_PIXCLK	= PAD_ID(PB, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	MX21_PAD_CSI_D5		= PAD_ID(PB, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	MX21_PAD_CSI_D6		= PAD_ID(PB, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	MX21_PAD_CSI_D7		= PAD_ID(PB, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	MX21_PAD_CSI_VSYNC	= PAD_ID(PB, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	MX21_PAD_CSI_HSYNC	= PAD_ID(PB, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	MX21_PAD_USB_BYP	= PAD_ID(PB, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	MX21_PAD_USB_PWR	= PAD_ID(PB, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	MX21_PAD_USB_OC		= PAD_ID(PB, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	MX21_PAD_USBH_ON	= PAD_ID(PB, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	MX21_PAD_USBH1_FS	= PAD_ID(PB, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	MX21_PAD_USBH1_OE	= PAD_ID(PB, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	MX21_PAD_USBH1_TXDM	= PAD_ID(PB, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	MX21_PAD_USBH1_TXDP	= PAD_ID(PB, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	MX21_PAD_USBH1_RXDM	= PAD_ID(PB, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	MX21_PAD_USBH1_RXDP	= PAD_ID(PB, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	MX21_PAD_USBG_SDA	= PAD_ID(PC, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	MX21_PAD_USBG_SCL	= PAD_ID(PC, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	MX21_PAD_USBG_ON	= PAD_ID(PC, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	MX21_PAD_USBG_FS	= PAD_ID(PC, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	MX21_PAD_USBG_OE	= PAD_ID(PC, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	MX21_PAD_USBG_TXDM	= PAD_ID(PC, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	MX21_PAD_USBG_TXDP	= PAD_ID(PC, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	MX21_PAD_USBG_RXDM	= PAD_ID(PC, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	MX21_PAD_USBG_RXDP	= PAD_ID(PC, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	MX21_PAD_TOUT		= PAD_ID(PC, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	MX21_PAD_TIN		= PAD_ID(PC, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	MX21_PAD_SAP_FS		= PAD_ID(PC, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	MX21_PAD_SAP_RXD	= PAD_ID(PC, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	MX21_PAD_SAP_TXD	= PAD_ID(PC, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	MX21_PAD_SAP_CLK	= PAD_ID(PC, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	MX21_PAD_SSI1_FS	= PAD_ID(PC, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	MX21_PAD_SSI1_RXD	= PAD_ID(PC, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	MX21_PAD_SSI1_TXD	= PAD_ID(PC, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	MX21_PAD_SSI1_CLK	= PAD_ID(PC, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	MX21_PAD_SSI2_FS	= PAD_ID(PC, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	MX21_PAD_SSI2_RXD	= PAD_ID(PC, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	MX21_PAD_SSI2_TXD	= PAD_ID(PC, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	MX21_PAD_SSI2_CLK	= PAD_ID(PC, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	MX21_PAD_SSI3_FS	= PAD_ID(PC, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	MX21_PAD_SSI3_RXD	= PAD_ID(PC, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	MX21_PAD_SSI3_TXD	= PAD_ID(PC, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	MX21_PAD_SSI3_CLK	= PAD_ID(PC, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	MX21_PAD_I2C_DATA	= PAD_ID(PD, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	MX21_PAD_I2C_CLK	= PAD_ID(PD, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	MX21_PAD_CSPI2_SS2	= PAD_ID(PD, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	MX21_PAD_CSPI2_SS1	= PAD_ID(PD, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	MX21_PAD_CSPI2_SS0	= PAD_ID(PD, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	MX21_PAD_CSPI2_SCLK	= PAD_ID(PD, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	MX21_PAD_CSPI2_MISO	= PAD_ID(PD, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	MX21_PAD_CSPI2_MOSI	= PAD_ID(PD, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	MX21_PAD_CSPI1_RDY	= PAD_ID(PD, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	MX21_PAD_CSPI1_SS2	= PAD_ID(PD, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	MX21_PAD_CSPI1_SS1	= PAD_ID(PD, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	MX21_PAD_CSPI1_SS0	= PAD_ID(PD, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	MX21_PAD_CSPI1_SCLK	= PAD_ID(PD, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	MX21_PAD_CSPI1_MISO	= PAD_ID(PD, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	MX21_PAD_CSPI1_MOSI	= PAD_ID(PD, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	MX21_PAD_TEST_WB2	= PAD_ID(PE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	MX21_PAD_TEST_WB1	= PAD_ID(PE, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	MX21_PAD_TEST_WB0	= PAD_ID(PE, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	MX21_PAD_UART2_CTS	= PAD_ID(PE, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	MX21_PAD_UART2_RTS	= PAD_ID(PE, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	MX21_PAD_PWMO		= PAD_ID(PE, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	MX21_PAD_UART2_TXD	= PAD_ID(PE, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	MX21_PAD_UART2_RXD	= PAD_ID(PE, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	MX21_PAD_UART3_TXD	= PAD_ID(PE, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	MX21_PAD_UART3_RXD	= PAD_ID(PE, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	MX21_PAD_UART3_CTS	= PAD_ID(PE, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	MX21_PAD_UART3_RTS	= PAD_ID(PE, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	MX21_PAD_UART1_TXD	= PAD_ID(PE, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	MX21_PAD_UART1_RXD	= PAD_ID(PE, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	MX21_PAD_UART1_CTS	= PAD_ID(PE, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	MX21_PAD_UART1_RTS	= PAD_ID(PE, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	MX21_PAD_RTCK		= PAD_ID(PE, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	MX21_PAD_RESET_OUT	= PAD_ID(PE, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	MX21_PAD_SD1_D0		= PAD_ID(PE, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	MX21_PAD_SD1_D1		= PAD_ID(PE, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	MX21_PAD_SD1_D2		= PAD_ID(PE, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	MX21_PAD_SD1_D3		= PAD_ID(PE, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	MX21_PAD_SD1_CMD	= PAD_ID(PE, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	MX21_PAD_SD1_CLK	= PAD_ID(PE, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	MX21_PAD_NFRB		= PAD_ID(PF, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	MX21_PAD_NFCE		= PAD_ID(PF, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	MX21_PAD_NFWP		= PAD_ID(PF, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	MX21_PAD_NFCLE		= PAD_ID(PF, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	MX21_PAD_NFALE		= PAD_ID(PF, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	MX21_PAD_NFRE		= PAD_ID(PF, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	MX21_PAD_NFWE		= PAD_ID(PF, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	MX21_PAD_NFIO0		= PAD_ID(PF, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	MX21_PAD_NFIO1		= PAD_ID(PF, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	MX21_PAD_NFIO2		= PAD_ID(PF, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	MX21_PAD_NFIO3		= PAD_ID(PF, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	MX21_PAD_NFIO4		= PAD_ID(PF, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	MX21_PAD_NFIO5		= PAD_ID(PF, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	MX21_PAD_NFIO6		= PAD_ID(PF, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	MX21_PAD_NFIO7		= PAD_ID(PF, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	MX21_PAD_CLKO		= PAD_ID(PF, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	MX21_PAD_RESERVED	= PAD_ID(PF, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	MX21_PAD_CS4		= PAD_ID(PF, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	MX21_PAD_CS5		= PAD_ID(PF, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Pad names for the pinmux subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct pinctrl_pin_desc imx21_pinctrl_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	IMX_PINCTRL_PIN(MX21_PAD_LSCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	IMX_PINCTRL_PIN(MX21_PAD_LD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	IMX_PINCTRL_PIN(MX21_PAD_LD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	IMX_PINCTRL_PIN(MX21_PAD_LD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	IMX_PINCTRL_PIN(MX21_PAD_LD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	IMX_PINCTRL_PIN(MX21_PAD_LD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	IMX_PINCTRL_PIN(MX21_PAD_LD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	IMX_PINCTRL_PIN(MX21_PAD_LD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	IMX_PINCTRL_PIN(MX21_PAD_LD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	IMX_PINCTRL_PIN(MX21_PAD_LD8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	IMX_PINCTRL_PIN(MX21_PAD_LD9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	IMX_PINCTRL_PIN(MX21_PAD_LD10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	IMX_PINCTRL_PIN(MX21_PAD_LD11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	IMX_PINCTRL_PIN(MX21_PAD_LD12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	IMX_PINCTRL_PIN(MX21_PAD_LD13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	IMX_PINCTRL_PIN(MX21_PAD_LD14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	IMX_PINCTRL_PIN(MX21_PAD_LD15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	IMX_PINCTRL_PIN(MX21_PAD_LD16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	IMX_PINCTRL_PIN(MX21_PAD_LD17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	IMX_PINCTRL_PIN(MX21_PAD_REV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	IMX_PINCTRL_PIN(MX21_PAD_CLS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	IMX_PINCTRL_PIN(MX21_PAD_PS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	IMX_PINCTRL_PIN(MX21_PAD_SPL_SPR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	IMX_PINCTRL_PIN(MX21_PAD_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	IMX_PINCTRL_PIN(MX21_PAD_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	IMX_PINCTRL_PIN(MX21_PAD_CONTRAST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	IMX_PINCTRL_PIN(MX21_PAD_OE_ACD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	IMX_PINCTRL_PIN(MX21_PAD_SD2_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	IMX_PINCTRL_PIN(MX21_PAD_SD2_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	IMX_PINCTRL_PIN(MX21_PAD_SD2_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	IMX_PINCTRL_PIN(MX21_PAD_SD2_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	IMX_PINCTRL_PIN(MX21_PAD_SD2_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	IMX_PINCTRL_PIN(MX21_PAD_SD2_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	IMX_PINCTRL_PIN(MX21_PAD_CSI_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	IMX_PINCTRL_PIN(MX21_PAD_CSI_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	IMX_PINCTRL_PIN(MX21_PAD_CSI_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	IMX_PINCTRL_PIN(MX21_PAD_CSI_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	IMX_PINCTRL_PIN(MX21_PAD_CSI_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	IMX_PINCTRL_PIN(MX21_PAD_CSI_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	IMX_PINCTRL_PIN(MX21_PAD_CSI_PIXCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	IMX_PINCTRL_PIN(MX21_PAD_CSI_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	IMX_PINCTRL_PIN(MX21_PAD_CSI_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	IMX_PINCTRL_PIN(MX21_PAD_CSI_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	IMX_PINCTRL_PIN(MX21_PAD_CSI_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	IMX_PINCTRL_PIN(MX21_PAD_CSI_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	IMX_PINCTRL_PIN(MX21_PAD_USB_BYP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	IMX_PINCTRL_PIN(MX21_PAD_USB_PWR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	IMX_PINCTRL_PIN(MX21_PAD_USB_OC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	IMX_PINCTRL_PIN(MX21_PAD_USBH_ON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	IMX_PINCTRL_PIN(MX21_PAD_USBH1_FS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	IMX_PINCTRL_PIN(MX21_PAD_USBH1_OE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	IMX_PINCTRL_PIN(MX21_PAD_USBH1_TXDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	IMX_PINCTRL_PIN(MX21_PAD_USBH1_RXDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	IMX_PINCTRL_PIN(MX21_PAD_USBG_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	IMX_PINCTRL_PIN(MX21_PAD_USBG_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	IMX_PINCTRL_PIN(MX21_PAD_USBG_ON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	IMX_PINCTRL_PIN(MX21_PAD_USBG_FS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	IMX_PINCTRL_PIN(MX21_PAD_USBG_OE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	IMX_PINCTRL_PIN(MX21_PAD_USBG_TXDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	IMX_PINCTRL_PIN(MX21_PAD_USBG_RXDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	IMX_PINCTRL_PIN(MX21_PAD_TOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	IMX_PINCTRL_PIN(MX21_PAD_TIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	IMX_PINCTRL_PIN(MX21_PAD_SAP_FS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	IMX_PINCTRL_PIN(MX21_PAD_SAP_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	IMX_PINCTRL_PIN(MX21_PAD_SAP_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	IMX_PINCTRL_PIN(MX21_PAD_SAP_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	IMX_PINCTRL_PIN(MX21_PAD_SSI1_FS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	IMX_PINCTRL_PIN(MX21_PAD_SSI1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	IMX_PINCTRL_PIN(MX21_PAD_SSI1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	IMX_PINCTRL_PIN(MX21_PAD_SSI1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	IMX_PINCTRL_PIN(MX21_PAD_SSI2_FS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	IMX_PINCTRL_PIN(MX21_PAD_SSI2_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	IMX_PINCTRL_PIN(MX21_PAD_SSI2_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	IMX_PINCTRL_PIN(MX21_PAD_SSI2_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	IMX_PINCTRL_PIN(MX21_PAD_SSI3_FS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	IMX_PINCTRL_PIN(MX21_PAD_SSI3_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	IMX_PINCTRL_PIN(MX21_PAD_SSI3_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	IMX_PINCTRL_PIN(MX21_PAD_SSI3_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	IMX_PINCTRL_PIN(MX21_PAD_I2C_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	IMX_PINCTRL_PIN(MX21_PAD_I2C_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI2_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI2_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI1_RDY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI1_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	IMX_PINCTRL_PIN(MX21_PAD_CSPI1_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	IMX_PINCTRL_PIN(MX21_PAD_TEST_WB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	IMX_PINCTRL_PIN(MX21_PAD_TEST_WB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	IMX_PINCTRL_PIN(MX21_PAD_TEST_WB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	IMX_PINCTRL_PIN(MX21_PAD_UART2_CTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	IMX_PINCTRL_PIN(MX21_PAD_UART2_RTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	IMX_PINCTRL_PIN(MX21_PAD_PWMO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	IMX_PINCTRL_PIN(MX21_PAD_UART2_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	IMX_PINCTRL_PIN(MX21_PAD_UART2_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	IMX_PINCTRL_PIN(MX21_PAD_UART3_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	IMX_PINCTRL_PIN(MX21_PAD_UART3_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	IMX_PINCTRL_PIN(MX21_PAD_UART3_CTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	IMX_PINCTRL_PIN(MX21_PAD_UART3_RTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	IMX_PINCTRL_PIN(MX21_PAD_UART1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	IMX_PINCTRL_PIN(MX21_PAD_UART1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	IMX_PINCTRL_PIN(MX21_PAD_UART1_CTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	IMX_PINCTRL_PIN(MX21_PAD_UART1_RTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	IMX_PINCTRL_PIN(MX21_PAD_RTCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	IMX_PINCTRL_PIN(MX21_PAD_RESET_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	IMX_PINCTRL_PIN(MX21_PAD_SD1_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	IMX_PINCTRL_PIN(MX21_PAD_SD1_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	IMX_PINCTRL_PIN(MX21_PAD_SD1_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	IMX_PINCTRL_PIN(MX21_PAD_SD1_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	IMX_PINCTRL_PIN(MX21_PAD_SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	IMX_PINCTRL_PIN(MX21_PAD_SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	IMX_PINCTRL_PIN(MX21_PAD_NFRB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	IMX_PINCTRL_PIN(MX21_PAD_NFCE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	IMX_PINCTRL_PIN(MX21_PAD_NFWP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	IMX_PINCTRL_PIN(MX21_PAD_NFCLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	IMX_PINCTRL_PIN(MX21_PAD_NFALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	IMX_PINCTRL_PIN(MX21_PAD_NFRE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	IMX_PINCTRL_PIN(MX21_PAD_NFWE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	IMX_PINCTRL_PIN(MX21_PAD_NFIO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	IMX_PINCTRL_PIN(MX21_PAD_NFIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	IMX_PINCTRL_PIN(MX21_PAD_NFIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	IMX_PINCTRL_PIN(MX21_PAD_NFIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	IMX_PINCTRL_PIN(MX21_PAD_NFIO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	IMX_PINCTRL_PIN(MX21_PAD_NFIO5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	IMX_PINCTRL_PIN(MX21_PAD_NFIO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	IMX_PINCTRL_PIN(MX21_PAD_NFIO7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	IMX_PINCTRL_PIN(MX21_PAD_CLKO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	IMX_PINCTRL_PIN(MX21_PAD_RESERVED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	IMX_PINCTRL_PIN(MX21_PAD_CS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	IMX_PINCTRL_PIN(MX21_PAD_CS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static struct imx1_pinctrl_soc_info imx21_pinctrl_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.pins	= imx21_pinctrl_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.npins	= ARRAY_SIZE(imx21_pinctrl_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int __init imx21_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return imx1_pinctrl_core_probe(pdev, &imx21_pinctrl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const struct of_device_id imx21_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	{ .compatible = "fsl,imx21-iomuxc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static struct platform_driver imx21_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		.name		= "imx21-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		.of_match_table	= imx21_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) builtin_platform_driver_probe(imx21_pinctrl_driver, imx21_pinctrl_probe);