Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // i.MX1 pinctrl driver based on imx pinmux core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "pinctrl-imx1.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define PAD_ID(port, pin)	((port) * 32 + (pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define PA	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define PB	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define PC	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PD	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) enum imx1_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	MX1_PAD_A24		= PAD_ID(PA, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	MX1_PAD_TIN		= PAD_ID(PA, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	MX1_PAD_PWMO		= PAD_ID(PA, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	MX1_PAD_CSI_MCLK	= PAD_ID(PA, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	MX1_PAD_CSI_D0		= PAD_ID(PA, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	MX1_PAD_CSI_D1		= PAD_ID(PA, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	MX1_PAD_CSI_D2		= PAD_ID(PA, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	MX1_PAD_CSI_D3		= PAD_ID(PA, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	MX1_PAD_CSI_D4		= PAD_ID(PA, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	MX1_PAD_CSI_D5		= PAD_ID(PA, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	MX1_PAD_CSI_D6		= PAD_ID(PA, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	MX1_PAD_CSI_D7		= PAD_ID(PA, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	MX1_PAD_CSI_VSYNC	= PAD_ID(PA, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	MX1_PAD_CSI_HSYNC	= PAD_ID(PA, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	MX1_PAD_CSI_PIXCLK	= PAD_ID(PA, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	MX1_PAD_I2C_SDA		= PAD_ID(PA, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	MX1_PAD_I2C_SCL		= PAD_ID(PA, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	MX1_PAD_DTACK		= PAD_ID(PA, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	MX1_PAD_BCLK		= PAD_ID(PA, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	MX1_PAD_LBA		= PAD_ID(PA, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	MX1_PAD_ECB		= PAD_ID(PA, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	MX1_PAD_A0		= PAD_ID(PA, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	MX1_PAD_CS4		= PAD_ID(PA, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	MX1_PAD_CS5		= PAD_ID(PA, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	MX1_PAD_A16		= PAD_ID(PA, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	MX1_PAD_A17		= PAD_ID(PA, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	MX1_PAD_A18		= PAD_ID(PA, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	MX1_PAD_A19		= PAD_ID(PA, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	MX1_PAD_A20		= PAD_ID(PA, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	MX1_PAD_A21		= PAD_ID(PA, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	MX1_PAD_A22		= PAD_ID(PA, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	MX1_PAD_A23		= PAD_ID(PA, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	MX1_PAD_SD_DAT0		= PAD_ID(PB, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	MX1_PAD_SD_DAT1		= PAD_ID(PB, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	MX1_PAD_SD_DAT2		= PAD_ID(PB, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	MX1_PAD_SD_DAT3		= PAD_ID(PB, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	MX1_PAD_SD_SCLK		= PAD_ID(PB, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	MX1_PAD_SD_CMD		= PAD_ID(PB, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	MX1_PAD_SIM_SVEN	= PAD_ID(PB, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	MX1_PAD_SIM_PD		= PAD_ID(PB, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	MX1_PAD_SIM_TX		= PAD_ID(PB, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	MX1_PAD_SIM_RX		= PAD_ID(PB, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	MX1_PAD_SIM_RST		= PAD_ID(PB, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	MX1_PAD_SIM_CLK		= PAD_ID(PB, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	MX1_PAD_USBD_AFE	= PAD_ID(PB, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	MX1_PAD_USBD_OE		= PAD_ID(PB, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	MX1_PAD_USBD_RCV	= PAD_ID(PB, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	MX1_PAD_USBD_SUSPND	= PAD_ID(PB, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	MX1_PAD_USBD_VP		= PAD_ID(PB, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	MX1_PAD_USBD_VM		= PAD_ID(PB, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	MX1_PAD_USBD_VPO	= PAD_ID(PB, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	MX1_PAD_USBD_VMO	= PAD_ID(PB, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	MX1_PAD_UART2_CTS	= PAD_ID(PB, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	MX1_PAD_UART2_RTS	= PAD_ID(PB, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	MX1_PAD_UART2_TXD	= PAD_ID(PB, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	MX1_PAD_UART2_RXD	= PAD_ID(PB, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	MX1_PAD_SSI_RXFS	= PAD_ID(PC, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	MX1_PAD_SSI_RXCLK	= PAD_ID(PC, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	MX1_PAD_SSI_RXDAT	= PAD_ID(PC, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	MX1_PAD_SSI_TXDAT	= PAD_ID(PC, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	MX1_PAD_SSI_TXFS	= PAD_ID(PC, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	MX1_PAD_SSI_TXCLK	= PAD_ID(PC, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	MX1_PAD_UART1_CTS	= PAD_ID(PC, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	MX1_PAD_UART1_RTS	= PAD_ID(PC, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	MX1_PAD_UART1_TXD	= PAD_ID(PC, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	MX1_PAD_UART1_RXD	= PAD_ID(PC, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	MX1_PAD_SPI1_RDY	= PAD_ID(PC, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	MX1_PAD_SPI1_SCLK	= PAD_ID(PC, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	MX1_PAD_SPI1_SS		= PAD_ID(PC, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	MX1_PAD_SPI1_MISO	= PAD_ID(PC, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	MX1_PAD_SPI1_MOSI	= PAD_ID(PC, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	MX1_PAD_BT13		= PAD_ID(PC, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	MX1_PAD_BT12		= PAD_ID(PC, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	MX1_PAD_BT11		= PAD_ID(PC, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	MX1_PAD_BT10		= PAD_ID(PC, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	MX1_PAD_BT9		= PAD_ID(PC, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	MX1_PAD_BT8		= PAD_ID(PC, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	MX1_PAD_BT7		= PAD_ID(PC, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	MX1_PAD_BT6		= PAD_ID(PC, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	MX1_PAD_BT5		= PAD_ID(PC, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	MX1_PAD_BT4		= PAD_ID(PC, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	MX1_PAD_BT3		= PAD_ID(PC, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	MX1_PAD_BT2		= PAD_ID(PC, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	MX1_PAD_BT1		= PAD_ID(PC, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	MX1_PAD_LSCLK		= PAD_ID(PD, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	MX1_PAD_REV		= PAD_ID(PD, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	MX1_PAD_CLS		= PAD_ID(PD, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	MX1_PAD_PS		= PAD_ID(PD, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	MX1_PAD_SPL_SPR		= PAD_ID(PD, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	MX1_PAD_CONTRAST	= PAD_ID(PD, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	MX1_PAD_ACD_OE		= PAD_ID(PD, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	MX1_PAD_LP_HSYNC	= PAD_ID(PD, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	MX1_PAD_FLM_VSYNC	= PAD_ID(PD, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	MX1_PAD_LD0		= PAD_ID(PD, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	MX1_PAD_LD1		= PAD_ID(PD, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	MX1_PAD_LD2		= PAD_ID(PD, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	MX1_PAD_LD3		= PAD_ID(PD, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	MX1_PAD_LD4		= PAD_ID(PD, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	MX1_PAD_LD5		= PAD_ID(PD, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	MX1_PAD_LD6		= PAD_ID(PD, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	MX1_PAD_LD7		= PAD_ID(PD, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	MX1_PAD_LD8		= PAD_ID(PD, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	MX1_PAD_LD9		= PAD_ID(PD, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	MX1_PAD_LD10		= PAD_ID(PD, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	MX1_PAD_LD11		= PAD_ID(PD, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	MX1_PAD_LD12		= PAD_ID(PD, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	MX1_PAD_LD13		= PAD_ID(PD, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	MX1_PAD_LD14		= PAD_ID(PD, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	MX1_PAD_LD15		= PAD_ID(PD, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	MX1_PAD_TMR2OUT		= PAD_ID(PD, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Pad names for the pinmux subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct pinctrl_pin_desc imx1_pinctrl_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	IMX_PINCTRL_PIN(MX1_PAD_A24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	IMX_PINCTRL_PIN(MX1_PAD_TIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	IMX_PINCTRL_PIN(MX1_PAD_PWMO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	IMX_PINCTRL_PIN(MX1_PAD_CSI_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	IMX_PINCTRL_PIN(MX1_PAD_CSI_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	IMX_PINCTRL_PIN(MX1_PAD_CSI_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	IMX_PINCTRL_PIN(MX1_PAD_CSI_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	IMX_PINCTRL_PIN(MX1_PAD_CSI_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	IMX_PINCTRL_PIN(MX1_PAD_CSI_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	IMX_PINCTRL_PIN(MX1_PAD_CSI_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	IMX_PINCTRL_PIN(MX1_PAD_CSI_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	IMX_PINCTRL_PIN(MX1_PAD_CSI_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	IMX_PINCTRL_PIN(MX1_PAD_CSI_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	IMX_PINCTRL_PIN(MX1_PAD_CSI_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	IMX_PINCTRL_PIN(MX1_PAD_CSI_PIXCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	IMX_PINCTRL_PIN(MX1_PAD_I2C_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	IMX_PINCTRL_PIN(MX1_PAD_I2C_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	IMX_PINCTRL_PIN(MX1_PAD_DTACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	IMX_PINCTRL_PIN(MX1_PAD_BCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	IMX_PINCTRL_PIN(MX1_PAD_LBA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	IMX_PINCTRL_PIN(MX1_PAD_ECB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	IMX_PINCTRL_PIN(MX1_PAD_A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	IMX_PINCTRL_PIN(MX1_PAD_CS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	IMX_PINCTRL_PIN(MX1_PAD_CS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	IMX_PINCTRL_PIN(MX1_PAD_A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	IMX_PINCTRL_PIN(MX1_PAD_A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	IMX_PINCTRL_PIN(MX1_PAD_A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	IMX_PINCTRL_PIN(MX1_PAD_A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	IMX_PINCTRL_PIN(MX1_PAD_A20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	IMX_PINCTRL_PIN(MX1_PAD_A21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	IMX_PINCTRL_PIN(MX1_PAD_A22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	IMX_PINCTRL_PIN(MX1_PAD_A23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	IMX_PINCTRL_PIN(MX1_PAD_SD_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	IMX_PINCTRL_PIN(MX1_PAD_SD_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	IMX_PINCTRL_PIN(MX1_PAD_SD_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	IMX_PINCTRL_PIN(MX1_PAD_SD_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	IMX_PINCTRL_PIN(MX1_PAD_SD_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	IMX_PINCTRL_PIN(MX1_PAD_SD_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	IMX_PINCTRL_PIN(MX1_PAD_SIM_SVEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	IMX_PINCTRL_PIN(MX1_PAD_SIM_PD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	IMX_PINCTRL_PIN(MX1_PAD_SIM_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	IMX_PINCTRL_PIN(MX1_PAD_SIM_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	IMX_PINCTRL_PIN(MX1_PAD_SIM_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	IMX_PINCTRL_PIN(MX1_PAD_USBD_AFE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	IMX_PINCTRL_PIN(MX1_PAD_USBD_OE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	IMX_PINCTRL_PIN(MX1_PAD_USBD_RCV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	IMX_PINCTRL_PIN(MX1_PAD_USBD_SUSPND),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	IMX_PINCTRL_PIN(MX1_PAD_USBD_VP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	IMX_PINCTRL_PIN(MX1_PAD_USBD_VM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	IMX_PINCTRL_PIN(MX1_PAD_USBD_VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	IMX_PINCTRL_PIN(MX1_PAD_USBD_VMO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	IMX_PINCTRL_PIN(MX1_PAD_UART2_CTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	IMX_PINCTRL_PIN(MX1_PAD_UART2_RTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	IMX_PINCTRL_PIN(MX1_PAD_UART2_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	IMX_PINCTRL_PIN(MX1_PAD_UART2_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	IMX_PINCTRL_PIN(MX1_PAD_SSI_RXFS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	IMX_PINCTRL_PIN(MX1_PAD_SSI_RXCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	IMX_PINCTRL_PIN(MX1_PAD_SSI_RXDAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	IMX_PINCTRL_PIN(MX1_PAD_SSI_TXDAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	IMX_PINCTRL_PIN(MX1_PAD_SSI_TXFS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	IMX_PINCTRL_PIN(MX1_PAD_SSI_TXCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	IMX_PINCTRL_PIN(MX1_PAD_UART1_CTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	IMX_PINCTRL_PIN(MX1_PAD_UART1_RTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	IMX_PINCTRL_PIN(MX1_PAD_UART1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	IMX_PINCTRL_PIN(MX1_PAD_UART1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	IMX_PINCTRL_PIN(MX1_PAD_SPI1_RDY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	IMX_PINCTRL_PIN(MX1_PAD_SPI1_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	IMX_PINCTRL_PIN(MX1_PAD_SPI1_SS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	IMX_PINCTRL_PIN(MX1_PAD_SPI1_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	IMX_PINCTRL_PIN(MX1_PAD_SPI1_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	IMX_PINCTRL_PIN(MX1_PAD_BT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	IMX_PINCTRL_PIN(MX1_PAD_BT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	IMX_PINCTRL_PIN(MX1_PAD_BT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	IMX_PINCTRL_PIN(MX1_PAD_BT10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	IMX_PINCTRL_PIN(MX1_PAD_BT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	IMX_PINCTRL_PIN(MX1_PAD_BT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	IMX_PINCTRL_PIN(MX1_PAD_BT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	IMX_PINCTRL_PIN(MX1_PAD_BT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	IMX_PINCTRL_PIN(MX1_PAD_BT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	IMX_PINCTRL_PIN(MX1_PAD_BT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	IMX_PINCTRL_PIN(MX1_PAD_BT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	IMX_PINCTRL_PIN(MX1_PAD_BT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	IMX_PINCTRL_PIN(MX1_PAD_BT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	IMX_PINCTRL_PIN(MX1_PAD_LSCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	IMX_PINCTRL_PIN(MX1_PAD_REV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	IMX_PINCTRL_PIN(MX1_PAD_CLS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	IMX_PINCTRL_PIN(MX1_PAD_PS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	IMX_PINCTRL_PIN(MX1_PAD_SPL_SPR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	IMX_PINCTRL_PIN(MX1_PAD_CONTRAST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	IMX_PINCTRL_PIN(MX1_PAD_ACD_OE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	IMX_PINCTRL_PIN(MX1_PAD_LP_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	IMX_PINCTRL_PIN(MX1_PAD_FLM_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	IMX_PINCTRL_PIN(MX1_PAD_LD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	IMX_PINCTRL_PIN(MX1_PAD_LD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	IMX_PINCTRL_PIN(MX1_PAD_LD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	IMX_PINCTRL_PIN(MX1_PAD_LD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	IMX_PINCTRL_PIN(MX1_PAD_LD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	IMX_PINCTRL_PIN(MX1_PAD_LD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	IMX_PINCTRL_PIN(MX1_PAD_LD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	IMX_PINCTRL_PIN(MX1_PAD_LD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	IMX_PINCTRL_PIN(MX1_PAD_LD8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	IMX_PINCTRL_PIN(MX1_PAD_LD9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	IMX_PINCTRL_PIN(MX1_PAD_LD10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	IMX_PINCTRL_PIN(MX1_PAD_LD11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	IMX_PINCTRL_PIN(MX1_PAD_LD12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	IMX_PINCTRL_PIN(MX1_PAD_LD13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	IMX_PINCTRL_PIN(MX1_PAD_LD14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	IMX_PINCTRL_PIN(MX1_PAD_LD15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	IMX_PINCTRL_PIN(MX1_PAD_TMR2OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct imx1_pinctrl_soc_info imx1_pinctrl_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.pins	= imx1_pinctrl_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.npins	= ARRAY_SIZE(imx1_pinctrl_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int __init imx1_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return imx1_pinctrl_core_probe(pdev, &imx1_pinctrl_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct of_device_id imx1_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	{ .compatible = "fsl,imx1-iomuxc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static struct platform_driver imx1_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.name		= "imx1-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.of_match_table	= imx1_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) builtin_platform_driver_probe(imx1_pinctrl_driver, imx1_pinctrl_probe);