^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IMX pinmux core definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Dong Aisheng <dong.aisheng@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __DRIVERS_PINCTRL_IMX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __DRIVERS_PINCTRL_IMX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) extern struct pinmux_ops imx_pmx_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) extern const struct dev_pm_ops imx_pinctrl_pm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * struct imx_pin_mmio - MMIO pin configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @mux_mode: the mux mode for this pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @input_reg: the select input register offset for this pin if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * 0 if no select input setting needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @input_val: the select input value for this pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @configs: the config for this pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct imx_pin_mmio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int mux_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u16 input_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int input_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * struct imx_pin_scu - SCU pin configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @mux: the mux mode for this pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @configs: the config for this pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct imx_pin_scu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int mux_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * struct imx_pin - describes a single i.MX pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @pin: the pin_id of this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @conf: config type of this pin, either mmio or scu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct imx_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct imx_pin_mmio mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct imx_pin_scu scu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * struct imx_pin_reg - describe a pin reg map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @mux_reg: mux register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @conf_reg: config register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct imx_pin_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) s16 mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) s16 conf_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* decode a generic config into raw register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct imx_cfg_params_decode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) bool invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @dev: a pointer back to containing device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @base: the offset to the controller in virtual memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct imx_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void __iomem *input_sel_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const struct imx_pinctrl_soc_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct imx_pin_reg *pin_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int group_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct imx_pinctrl_soc_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) const char *gpr_compatible;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int mux_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* generic pinconf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) bool generic_pinconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const struct pinconf_generic_params *custom_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int num_custom_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) const struct imx_cfg_params_decode *decodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int num_decodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void (*fixup)(unsigned long *configs, unsigned int num_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 *raw_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int (*gpio_set_direction)(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bool input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int (*imx_pinconf_get)(struct pinctrl_dev *pctldev, unsigned int pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int (*imx_pinconf_set)(struct pinctrl_dev *pctldev, unsigned int pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long *configs, unsigned int num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void (*imx_pinctrl_parse_pin)(struct imx_pinctrl *ipctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int *pin_id, struct imx_pin *pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const __be32 **list_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX_CFG_PARAMS_DECODE(p, m, o) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { .param = p, .mask = m, .shift = o, .invert = false, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .param = p, .mask = m, .shift = o, .invert = true, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SHARE_MUX_CONF_REG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ZERO_OFFSET_VALID BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX_USE_SCU BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define NO_MUX 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define NO_PAD 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PAD_CTL_MASK(len) ((1 << len) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX_MUX_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IOMUXC_CONFIG_SION (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int imx_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct imx_pinctrl_soc_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BM_PAD_CTL_GP_ENABLE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BM_PAD_CTL_IFMUX_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BP_PAD_CTL_IFMUX 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int imx_pinctrl_sc_ipc_init(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long *configs, unsigned num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int *pin_id, struct imx_pin *pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const __be32 **list_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif /* __DRIVERS_PINCTRL_IMX_H */
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Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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