^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Core driver for the imx pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright (C) 2012 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Author: Dong Aisheng <dong.aisheng@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "../pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "../pinmux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "pinctrl-imx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* The bits in CONFIG cell defined in binding doc*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX_PAD_SION 0x40000000 /* set SION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static inline const struct group_desc *imx_pinctrl_find_group_by_name(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const struct group_desc *grp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) for (i = 0; i < pctldev->num_groups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) grp = pinctrl_generic_get_group(pctldev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (grp && !strcmp(grp->name, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) seq_printf(s, "%s", dev_name(pctldev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct pinctrl_map **map, unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) const struct group_desc *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct pinctrl_map *new_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct device_node *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct imx_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int map_num = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * first find the group of this node and check if we need create
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * config maps for pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (!grp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) dev_err(ipctl->dev, "unable to find group for node %pOFn\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (info->flags & IMX_USE_SCU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) map_num += grp->num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) for (i = 0; i < grp->num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pin = &((struct imx_pin *)(grp->data))[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) map_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!new_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *map = new_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *num_maps = map_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* create mux map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) parent = of_get_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) kfree(new_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) new_map[0].data.mux.function = parent->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) new_map[0].data.mux.group = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* create config map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) new_map++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) for (i = j = 0; i < grp->num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pin = &((struct imx_pin *)(grp->data))[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * We only create config maps for SCU pads or MMIO pads that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * are not using the default config(a.k.a IMX_NO_PAD_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!(info->flags & IMX_USE_SCU) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) (pin->conf.mmio.config & IMX_NO_PAD_CTL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) new_map[j].data.configs.group_or_pin =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pin_get_name(pctldev, pin->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (info->flags & IMX_USE_SCU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * For SCU case, we set mux and conf together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * in one IPC call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) new_map[j].data.configs.configs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (unsigned long *)&pin->conf.scu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) new_map[j].data.configs.num_configs = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) new_map[j].data.configs.configs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) &pin->conf.mmio.config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) new_map[j].data.configs.num_configs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) j++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) (*map)->data.mux.function, (*map)->data.mux.group, map_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void imx_dt_free_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct pinctrl_map *map, unsigned num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const struct pinctrl_ops imx_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .get_groups_count = pinctrl_generic_get_group_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .get_group_name = pinctrl_generic_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .get_group_pins = pinctrl_generic_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .pin_dbg_show = imx_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .dt_node_to_map = imx_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .dt_free_map = imx_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct imx_pin *pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const struct imx_pin_reg *pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int pin_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pin_id = pin->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pin_reg = &ipctl->pin_regs[pin_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (pin_reg->mux_reg == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) info->pins[pin_id].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (info->flags & SHARE_MUX_CONF_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) reg = readl(ipctl->base + pin_reg->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) reg &= ~info->mux_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) reg |= (pin_mmio->mux_mode << info->mux_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writel(reg, ipctl->base + pin_reg->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pin_reg->mux_reg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pin_reg->mux_reg, pin_mmio->mux_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * If the select input value begins with 0xff, it's a quirky
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * select input and the value should be interpreted as below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * 31 23 15 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * | 0xff | shift | width | select |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * It's used to work around the problem that the select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * input for some pin is not implemented in the select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * input register but in some general purpose register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * We encode the select input value, width and shift of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * the bit field into input_val cell of pin function ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * in device tree, and then decode them here for setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * up the select input bits in general purpose register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (pin_mmio->input_val >> 24 == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 val = pin_mmio->input_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 select = val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 width = (val >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 shift = (val >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 mask = ((1 << width) - 1) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * The input_reg[i] here is actually some IOMUXC general
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * purpose register, not regular select input register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) val = readl(ipctl->base + pin_mmio->input_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) val |= select << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) writel(val, ipctl->base + pin_mmio->input_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } else if (pin_mmio->input_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * Regular select input register can never be at offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * 0, and we only print register value for regular case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (ipctl->input_sel_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) writel(pin_mmio->input_val, ipctl->input_sel_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pin_mmio->input_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) writel(pin_mmio->input_val, ipctl->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pin_mmio->input_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_dbg(ipctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "==>select_input: offset 0x%x val 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pin_mmio->input_reg, pin_mmio->input_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct function_desc *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct group_desc *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct imx_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Configure the mux mode for each pin in the group for a specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) grp = pinctrl_generic_get_group(pctldev, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) func = pinmux_generic_get_function(pctldev, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (!func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) npins = grp->num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) dev_dbg(ipctl->dev, "enable function %s group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) func->name, grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * For IMX_USE_SCU case, we postpone the mux setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * until config is set as we can set them together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * in one IPC call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pin = &((struct imx_pin *)(grp->data))[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!(info->flags & IMX_USE_SCU)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) err = imx_pmx_set_one_pin_mmio(ipctl, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct pinmux_ops imx_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .get_functions_count = pinmux_generic_get_function_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .get_function_name = pinmux_generic_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .get_function_groups = pinmux_generic_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .set_mux = imx_pmx_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* decode generic config into raw register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) const struct imx_cfg_params_decode *decode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 raw_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) WARN_ON(num_configs > info->num_decodes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) param_val = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) decode = info->decodes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) for (j = 0; j < info->num_decodes; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (param == decode->param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (decode->invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) param_val = !param_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) raw_config |= (param_val << decode->shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) & decode->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) decode++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (info->fixup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) info->fixup(configs, num_configs, &raw_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return raw_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static u32 imx_pinconf_parse_generic_config(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct imx_pinctrl *ipctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct pinctrl_dev *pctl = ipctl->pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int num_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned long *configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!info->generic_pinconf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = pinconf_generic_parse_dt_config(np, pctl, &configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) &num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return imx_pinconf_decode_generic_config(ipctl, configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (pin_reg->conf_reg == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) info->pins[pin_id].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *config = readl(ipctl->base + pin_reg->conf_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (info->flags & SHARE_MUX_CONF_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *config &= ~info->mux_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int imx_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned pin_id, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (info->flags & IMX_USE_SCU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return info->imx_pinconf_get(pctldev, pin_id, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return imx_pinconf_get_mmio(pctldev, pin_id, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned pin_id, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (pin_reg->conf_reg == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) info->pins[pin_id].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_dbg(ipctl->dev, "pinconf set pin %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) info->pins[pin_id].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (info->flags & SHARE_MUX_CONF_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) reg = readl(ipctl->base + pin_reg->conf_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) reg &= info->mux_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) reg |= configs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) writel(reg, ipctl->base + pin_reg->conf_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pin_reg->conf_reg, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) writel(configs[i], ipctl->base + pin_reg->conf_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pin_reg->conf_reg, configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int imx_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned pin_id, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (info->flags & IMX_USE_SCU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return info->imx_pinconf_set(pctldev, pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return imx_pinconf_set_mmio(pctldev, pin_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct seq_file *s, unsigned pin_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) const struct imx_pin_reg *pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (info->flags & IMX_USE_SCU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = info->imx_pinconf_get(pctldev, pin_id, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(ipctl->dev, "failed to get %s pinconf\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pin_get_name(pctldev, pin_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) seq_puts(s, "N/A");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pin_reg = &ipctl->pin_regs[pin_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (pin_reg->conf_reg == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) seq_puts(s, "N/A");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) config = readl(ipctl->base + pin_reg->conf_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) seq_printf(s, "0x%lx", config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct seq_file *s, unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct group_desc *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (group >= pctldev->num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) seq_puts(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) grp = pinctrl_generic_get_group(pctldev, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (!grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) for (i = 0; i < grp->num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) name = pin_get_name(pctldev, pin->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = imx_pinconf_get(pctldev, pin->pin, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) seq_printf(s, " %s: 0x%lx\n", name, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static const struct pinconf_ops imx_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .pin_config_get = imx_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .pin_config_set = imx_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .pin_config_dbg_show = imx_pinconf_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * Each pin represented in fsl,pins consists of a number of u32 PIN_FUNC_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * and 1 u32 CONFIG, the total size is PIN_FUNC_ID + CONFIG for each pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * For generic_pinconf case, there's no extra u32 CONFIG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * PIN_FUNC_ID format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * <mux_reg conf_reg input_reg mux_mode input_val>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * SHARE_MUX_CONF_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * <mux_conf_reg input_reg mux_mode input_val>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * IMX_USE_SCU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * <pin_id mux_mode>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define FSL_PIN_SIZE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define FSL_PIN_SHARE_SIZE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define FSL_SCU_PIN_SIZE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) unsigned int *pin_id, struct imx_pin *pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) const __be32 **list_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct imx_pin_mmio *pin_mmio = &pin->conf.mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct imx_pin_reg *pin_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) const __be32 *list = *list_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 mux_reg, conf_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) mux_reg = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mux_reg = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (info->flags & SHARE_MUX_CONF_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) conf_reg = mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) conf_reg = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (!conf_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) conf_reg = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pin_reg = &ipctl->pin_regs[*pin_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) pin->pin = *pin_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pin_reg->mux_reg = mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pin_reg->conf_reg = conf_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pin_mmio->input_reg = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pin_mmio->mux_mode = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) pin_mmio->input_val = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (info->generic_pinconf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* generic pin config decoded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* legacy pin config read from devicetree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) config = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* SION bit is in mux register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (config & IMX_PAD_SION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pin_mmio->mux_mode |= IOMUXC_CONFIG_SION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) pin_mmio->config = config & ~IMX_PAD_SION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) *list_p = list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pin_mmio->mux_mode, pin_mmio->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int imx_pinctrl_parse_groups(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct group_desc *grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct imx_pinctrl *ipctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) const struct imx_pinctrl_soc_info *info = ipctl->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct imx_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int size, pin_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) const __be32 *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_dbg(ipctl->dev, "group(%d): %pOFn\n", index, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (info->flags & IMX_USE_SCU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) pin_size = FSL_SCU_PIN_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) else if (info->flags & SHARE_MUX_CONF_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pin_size = FSL_PIN_SHARE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pin_size = FSL_PIN_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (info->generic_pinconf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pin_size -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* Initialise group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) grp->name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * do sanity check and calculate pins number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * First try legacy 'fsl,pins' property, then fall back to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * generic 'pinmux'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * Note: for generic 'pinmux' case, there's no CONFIG part in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * the binding format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) list = of_get_property(np, "fsl,pins", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (!list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) list = of_get_property(np, "pinmux", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev_err(ipctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) "no fsl,pins and pins property in node %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* we do not check return since it's safe node passed down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (!size || size % pin_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) grp->num_pins = size / pin_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) grp->data = devm_kcalloc(ipctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) grp->num_pins, sizeof(struct imx_pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) grp->pins = devm_kcalloc(ipctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) grp->num_pins, sizeof(unsigned int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!grp->pins || !grp->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) for (i = 0; i < grp->num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pin = &((struct imx_pin *)(grp->data))[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (info->flags & IMX_USE_SCU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pin, &list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pin, &list, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static int imx_pinctrl_parse_functions(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct imx_pinctrl *ipctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct pinctrl_dev *pctl = ipctl->pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct function_desc *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct group_desc *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dev_dbg(pctl->dev, "parse function(%d): %pOFn\n", index, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) func = pinmux_generic_get_function(pctl, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Initialise function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) func->name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) func->num_group_names = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (func->num_group_names == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) sizeof(char *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (!func->group_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) func->group_names[i] = child->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (!grp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) mutex_lock(&ipctl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) radix_tree_insert(&pctl->pin_group_tree,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ipctl->group_index++, grp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) mutex_unlock(&ipctl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) imx_pinctrl_parse_groups(child, grp, ipctl, i++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Check if the DT contains pins in the direct child nodes. This indicates the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * newer DT format to store pins. This function returns true if the first found
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * fsl,pins property is in a child of np. Otherwise false is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct device_node *function_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct device_node *pinctrl_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) for_each_child_of_node(np, function_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (of_property_read_bool(function_np, "fsl,pins")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) of_node_put(function_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) for_each_child_of_node(function_np, pinctrl_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (of_property_read_bool(pinctrl_np, "fsl,pins")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) of_node_put(pinctrl_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) of_node_put(function_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int imx_pinctrl_probe_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct imx_pinctrl *ipctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct pinctrl_dev *pctl = ipctl->pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) u32 nfuncs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u32 i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) bool flat_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (flat_funcs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) nfuncs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) nfuncs = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (nfuncs == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dev_err(&pdev->dev, "no functions defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) for (i = 0; i < nfuncs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct function_desc *function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) function = devm_kzalloc(&pdev->dev, sizeof(*function),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (!function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mutex_lock(&ipctl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) radix_tree_insert(&pctl->pin_function_tree, i, function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) mutex_unlock(&ipctl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pctl->num_functions = nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ipctl->group_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (flat_funcs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pctl->num_groups = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) pctl->num_groups = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) for_each_child_of_node(np, child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) pctl->num_groups += of_get_child_count(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (flat_funcs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) imx_pinctrl_parse_functions(np, ipctl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) for_each_child_of_node(np, child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) imx_pinctrl_parse_functions(child, ipctl, i++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int imx_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) const struct imx_pinctrl_soc_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct regmap_config config = { .name = "gpr" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct device_node *dev_np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct pinctrl_desc *imx_pinctrl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct imx_pinctrl *ipctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (!info || !info->pins || !info->npins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dev_err(&pdev->dev, "wrong pinctrl info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (info->gpr_compatible) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!IS_ERR(gpr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) regmap_attach_dev(&pdev->dev, gpr, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* Create state holders etc for this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (!ipctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (!(info->flags & IMX_USE_SCU)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) sizeof(*ipctl->pin_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (!ipctl->pin_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) for (i = 0; i < info->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ipctl->pin_regs[i].mux_reg = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ipctl->pin_regs[i].conf_reg = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ipctl->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (IS_ERR(ipctl->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return PTR_ERR(ipctl->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (of_property_read_bool(dev_np, "fsl,input-sel")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ipctl->input_sel_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!ipctl->input_sel_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "iomuxc input select base address not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (!imx_pinctrl_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) imx_pinctrl_desc->name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) imx_pinctrl_desc->pins = info->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) imx_pinctrl_desc->npins = info->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) imx_pinctrl_desc->pctlops = &imx_pctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) imx_pinctrl_desc->pmxops = &imx_pmx_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) imx_pinctrl_desc->confops = &imx_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) imx_pinctrl_desc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* for generic pinconf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) imx_pinctrl_desc->custom_params = info->custom_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) imx_pinctrl_desc->num_custom_params = info->num_custom_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* platform specific callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) mutex_init(&ipctl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ipctl->info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ipctl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) platform_set_drvdata(pdev, ipctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ret = devm_pinctrl_register_and_init(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) imx_pinctrl_desc, ipctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) &ipctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ret = imx_pinctrl_probe_dt(pdev, ipctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dev_err(&pdev->dev, "fail to probe dt properties\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return pinctrl_enable(ipctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) EXPORT_SYMBOL_GPL(imx_pinctrl_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static int __maybe_unused imx_pinctrl_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return pinctrl_force_sleep(ipctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int __maybe_unused imx_pinctrl_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct imx_pinctrl *ipctl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return pinctrl_force_default(ipctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) const struct dev_pm_ops imx_pinctrl_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) SET_LATE_SYSTEM_SLEEP_PM_OPS(imx_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) imx_pinctrl_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) MODULE_DESCRIPTION("NXP i.MX common pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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