^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Lochnagar pin and GPIO control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Cirrus Logic International Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/lochnagar.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mfd/lochnagar1_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mfd/lochnagar2_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <dt-bindings/pinctrl/lochnagar.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LN2_NUM_GPIO_CHANNELS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LN_CDC_AIF1_STR "codec-aif1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LN_CDC_AIF2_STR "codec-aif2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LN_CDC_AIF3_STR "codec-aif3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LN_DSP_AIF1_STR "dsp-aif1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LN_DSP_AIF2_STR "dsp-aif2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LN_PSIA1_STR "psia1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LN_PSIA2_STR "psia2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LN_GF_AIF1_STR "gf-aif1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LN_GF_AIF2_STR "gf-aif2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LN_GF_AIF3_STR "gf-aif3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LN_GF_AIF4_STR "gf-aif4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LN_SPDIF_AIF_STR "spdif-aif"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LN_USB_AIF1_STR "usb-aif1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LN_USB_AIF2_STR "usb-aif2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LN_ADAT_AIF_STR "adat-aif"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LN_SOUNDCARD_AIF_STR "soundcard-aif"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LN_PIN_GPIO(REV, ID, NAME, REG, SHIFT, INVERT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .name = NAME, .type = LN_PTYPE_GPIO, .reg = LOCHNAGAR##REV##_##REG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .shift = LOCHNAGAR##REV##_##SHIFT##_SHIFT, .invert = INVERT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LN_PIN_SAIF(REV, ID, NAME) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { .name = NAME, .type = LN_PTYPE_AIF, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LN_PIN_AIF(REV, ID) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) LN_PIN_SAIF(REV, ID##_BCLK, LN_##ID##_STR"-bclk"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) LN_PIN_SAIF(REV, ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) LN_PIN_SAIF(REV, ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) LN_PIN_SAIF(REV, ID##_TXDAT, LN_##ID##_STR"-txdat")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LN1_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) LN_PIN_GPIO(1, ID, NAME, REG, SHIFT, INVERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LN1_PIN_MUX(ID, NAME) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const struct lochnagar_pin lochnagar1_##ID##_pin = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR1_##ID, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LN1_PIN_AIF(ID) LN_PIN_AIF(1, ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LN2_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) LN_PIN_GPIO(2, ID, NAME, REG, SHIFT, INVERT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LN2_PIN_MUX(ID, NAME) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const struct lochnagar_pin lochnagar2_##ID##_pin = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR2_GPIO_##ID, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LN2_PIN_AIF(ID) LN_PIN_AIF(2, ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LN2_PIN_GAI(ID) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) LN2_PIN_MUX(ID##_BCLK, LN_##ID##_STR"-bclk"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) LN2_PIN_MUX(ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) LN2_PIN_MUX(ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) LN2_PIN_MUX(ID##_TXDAT, LN_##ID##_STR"-txdat")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LN_PIN(REV, ID) [LOCHNAGAR##REV##_PIN_##ID] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .number = LOCHNAGAR##REV##_PIN_##ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .name = lochnagar##REV##_##ID##_pin.name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .drv_data = (void *)&lochnagar##REV##_##ID##_pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LN1_PIN(ID) LN_PIN(1, ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LN2_PIN(ID) LN_PIN(2, ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LN_PINS(REV, ID) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) LN_PIN(REV, ID##_BCLK), LN_PIN(REV, ID##_LRCLK), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) LN_PIN(REV, ID##_RXDAT), LN_PIN(REV, ID##_TXDAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LN1_PINS(ID) LN_PINS(1, ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LN2_PINS(ID) LN_PINS(2, ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) LOCHNAGAR1_PIN_GF_GPIO2 = LOCHNAGAR1_PIN_NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) LOCHNAGAR1_PIN_GF_GPIO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) LOCHNAGAR1_PIN_GF_GPIO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) LOCHNAGAR1_PIN_LED1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) LOCHNAGAR1_PIN_LED2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) LOCHNAGAR1_PIN_CDC_AIF1_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) LOCHNAGAR1_PIN_CDC_AIF1_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) LOCHNAGAR1_PIN_CDC_AIF1_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) LOCHNAGAR1_PIN_CDC_AIF1_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) LOCHNAGAR1_PIN_CDC_AIF2_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) LOCHNAGAR1_PIN_CDC_AIF2_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) LOCHNAGAR1_PIN_CDC_AIF2_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) LOCHNAGAR1_PIN_CDC_AIF2_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) LOCHNAGAR1_PIN_CDC_AIF3_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) LOCHNAGAR1_PIN_CDC_AIF3_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) LOCHNAGAR1_PIN_CDC_AIF3_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) LOCHNAGAR1_PIN_CDC_AIF3_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) LOCHNAGAR1_PIN_DSP_AIF1_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) LOCHNAGAR1_PIN_DSP_AIF1_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) LOCHNAGAR1_PIN_DSP_AIF1_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) LOCHNAGAR1_PIN_DSP_AIF1_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) LOCHNAGAR1_PIN_DSP_AIF2_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) LOCHNAGAR1_PIN_DSP_AIF2_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) LOCHNAGAR1_PIN_DSP_AIF2_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) LOCHNAGAR1_PIN_DSP_AIF2_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) LOCHNAGAR1_PIN_PSIA1_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) LOCHNAGAR1_PIN_PSIA1_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) LOCHNAGAR1_PIN_PSIA1_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) LOCHNAGAR1_PIN_PSIA1_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) LOCHNAGAR1_PIN_PSIA2_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) LOCHNAGAR1_PIN_PSIA2_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) LOCHNAGAR1_PIN_PSIA2_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) LOCHNAGAR1_PIN_PSIA2_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) LOCHNAGAR1_PIN_SPDIF_AIF_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) LOCHNAGAR1_PIN_SPDIF_AIF_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) LOCHNAGAR1_PIN_SPDIF_AIF_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) LOCHNAGAR1_PIN_SPDIF_AIF_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) LOCHNAGAR1_PIN_GF_AIF3_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) LOCHNAGAR1_PIN_GF_AIF3_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) LOCHNAGAR1_PIN_GF_AIF3_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) LOCHNAGAR1_PIN_GF_AIF3_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) LOCHNAGAR1_PIN_GF_AIF4_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) LOCHNAGAR1_PIN_GF_AIF4_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) LOCHNAGAR1_PIN_GF_AIF4_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) LOCHNAGAR1_PIN_GF_AIF4_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) LOCHNAGAR1_PIN_GF_AIF1_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) LOCHNAGAR1_PIN_GF_AIF1_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) LOCHNAGAR1_PIN_GF_AIF1_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) LOCHNAGAR1_PIN_GF_AIF1_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) LOCHNAGAR1_PIN_GF_AIF2_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) LOCHNAGAR1_PIN_GF_AIF2_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) LOCHNAGAR1_PIN_GF_AIF2_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) LOCHNAGAR1_PIN_GF_AIF2_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) LOCHNAGAR2_PIN_SPDIF_AIF_BCLK = LOCHNAGAR2_PIN_NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) LOCHNAGAR2_PIN_SPDIF_AIF_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) LOCHNAGAR2_PIN_SPDIF_AIF_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) LOCHNAGAR2_PIN_SPDIF_AIF_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) LOCHNAGAR2_PIN_USB_AIF1_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) LOCHNAGAR2_PIN_USB_AIF1_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) LOCHNAGAR2_PIN_USB_AIF1_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) LOCHNAGAR2_PIN_USB_AIF1_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) LOCHNAGAR2_PIN_USB_AIF2_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) LOCHNAGAR2_PIN_USB_AIF2_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) LOCHNAGAR2_PIN_USB_AIF2_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) LOCHNAGAR2_PIN_USB_AIF2_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) LOCHNAGAR2_PIN_ADAT_AIF_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) LOCHNAGAR2_PIN_ADAT_AIF_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) LOCHNAGAR2_PIN_ADAT_AIF_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) LOCHNAGAR2_PIN_ADAT_AIF_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) LOCHNAGAR2_PIN_SOUNDCARD_AIF_BCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) LOCHNAGAR2_PIN_SOUNDCARD_AIF_LRCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) LOCHNAGAR2_PIN_SOUNDCARD_AIF_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) LOCHNAGAR2_PIN_SOUNDCARD_AIF_TXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) enum lochnagar_pin_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) LN_PTYPE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) LN_PTYPE_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) LN_PTYPE_AIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) LN_PTYPE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct lochnagar_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const char name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) enum lochnagar_pin_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) bool invert;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) LN1_PIN_GPIO(CDC_RESET, "codec-reset", RST, CDC_RESET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) LN1_PIN_GPIO(DSP_RESET, "dsp-reset", RST, DSP_RESET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) LN1_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", I2C_CTRL, CDC_CIF_MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) LN1_PIN_MUX(GF_GPIO2, "gf-gpio2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) LN1_PIN_MUX(GF_GPIO3, "gf-gpio3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) LN1_PIN_MUX(GF_GPIO7, "gf-gpio7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) LN1_PIN_MUX(LED1, "led1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) LN1_PIN_MUX(LED2, "led2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) LN1_PIN_AIF(CDC_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) LN1_PIN_AIF(CDC_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) LN1_PIN_AIF(CDC_AIF3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) LN1_PIN_AIF(DSP_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) LN1_PIN_AIF(DSP_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) LN1_PIN_AIF(PSIA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) LN1_PIN_AIF(PSIA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) LN1_PIN_AIF(SPDIF_AIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) LN1_PIN_AIF(GF_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) LN1_PIN_AIF(GF_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) LN1_PIN_AIF(GF_AIF3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) LN1_PIN_AIF(GF_AIF4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) LN2_PIN_GPIO(CDC_RESET, "codec-reset", MINICARD_RESETS, CDC_RESET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) LN2_PIN_GPIO(DSP_RESET, "dsp-reset", MINICARD_RESETS, DSP_RESET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) LN2_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", COMMS_CTRL4, CDC_CIF1MODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) LN2_PIN_GPIO(CDC_LDOENA, "codec-ldoena", POWER_CTRL, PWR_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) LN2_PIN_GPIO(SPDIF_HWMODE, "spdif-hwmode", SPDIF_CTRL, SPDIF_HWMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) LN2_PIN_GPIO(SPDIF_RESET, "spdif-reset", SPDIF_CTRL, SPDIF_RESET, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) LN2_PIN_MUX(FPGA_GPIO1, "fpga-gpio1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) LN2_PIN_MUX(FPGA_GPIO2, "fpga-gpio2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) LN2_PIN_MUX(FPGA_GPIO3, "fpga-gpio3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) LN2_PIN_MUX(FPGA_GPIO4, "fpga-gpio4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) LN2_PIN_MUX(FPGA_GPIO5, "fpga-gpio5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) LN2_PIN_MUX(FPGA_GPIO6, "fpga-gpio6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) LN2_PIN_MUX(CDC_GPIO1, "codec-gpio1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) LN2_PIN_MUX(CDC_GPIO2, "codec-gpio2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) LN2_PIN_MUX(CDC_GPIO3, "codec-gpio3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) LN2_PIN_MUX(CDC_GPIO4, "codec-gpio4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) LN2_PIN_MUX(CDC_GPIO5, "codec-gpio5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) LN2_PIN_MUX(CDC_GPIO6, "codec-gpio6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) LN2_PIN_MUX(CDC_GPIO7, "codec-gpio7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) LN2_PIN_MUX(CDC_GPIO8, "codec-gpio8");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) LN2_PIN_MUX(DSP_GPIO1, "dsp-gpio1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) LN2_PIN_MUX(DSP_GPIO2, "dsp-gpio2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) LN2_PIN_MUX(DSP_GPIO3, "dsp-gpio3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) LN2_PIN_MUX(DSP_GPIO4, "dsp-gpio4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) LN2_PIN_MUX(DSP_GPIO5, "dsp-gpio5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) LN2_PIN_MUX(DSP_GPIO6, "dsp-gpio6");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) LN2_PIN_MUX(GF_GPIO2, "gf-gpio2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) LN2_PIN_MUX(GF_GPIO3, "gf-gpio3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) LN2_PIN_MUX(GF_GPIO7, "gf-gpio7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) LN2_PIN_MUX(DSP_UART1_RX, "dsp-uart1-rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) LN2_PIN_MUX(DSP_UART1_TX, "dsp-uart1-tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) LN2_PIN_MUX(DSP_UART2_RX, "dsp-uart2-rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) LN2_PIN_MUX(DSP_UART2_TX, "dsp-uart2-tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) LN2_PIN_MUX(GF_UART2_RX, "gf-uart2-rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) LN2_PIN_MUX(GF_UART2_TX, "gf-uart2-tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) LN2_PIN_MUX(USB_UART_RX, "usb-uart-rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) LN2_PIN_MUX(CDC_PDMCLK1, "codec-pdmclk1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) LN2_PIN_MUX(CDC_PDMDAT1, "codec-pdmdat1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) LN2_PIN_MUX(CDC_PDMCLK2, "codec-pdmclk2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) LN2_PIN_MUX(CDC_PDMDAT2, "codec-pdmdat2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) LN2_PIN_MUX(CDC_DMICCLK1, "codec-dmicclk1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) LN2_PIN_MUX(CDC_DMICDAT1, "codec-dmicdat1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) LN2_PIN_MUX(CDC_DMICCLK2, "codec-dmicclk2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) LN2_PIN_MUX(CDC_DMICDAT2, "codec-dmicdat2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) LN2_PIN_MUX(CDC_DMICCLK3, "codec-dmicclk3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) LN2_PIN_MUX(CDC_DMICDAT3, "codec-dmicdat3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) LN2_PIN_MUX(CDC_DMICCLK4, "codec-dmicclk4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) LN2_PIN_MUX(CDC_DMICDAT4, "codec-dmicdat4");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) LN2_PIN_MUX(DSP_DMICCLK1, "dsp-dmicclk1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) LN2_PIN_MUX(DSP_DMICDAT1, "dsp-dmicdat1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) LN2_PIN_MUX(DSP_DMICCLK2, "dsp-dmicclk2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) LN2_PIN_MUX(DSP_DMICDAT2, "dsp-dmicdat2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) LN2_PIN_MUX(I2C2_SCL, "i2c2-scl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) LN2_PIN_MUX(I2C2_SDA, "i2c2-sda");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) LN2_PIN_MUX(I2C3_SCL, "i2c3-scl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) LN2_PIN_MUX(I2C3_SDA, "i2c3-sda");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) LN2_PIN_MUX(I2C4_SCL, "i2c4-scl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) LN2_PIN_MUX(I2C4_SDA, "i2c4-sda");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) LN2_PIN_MUX(DSP_STANDBY, "dsp-standby");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) LN2_PIN_MUX(CDC_MCLK1, "codec-mclk1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) LN2_PIN_MUX(CDC_MCLK2, "codec-mclk2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) LN2_PIN_MUX(DSP_CLKIN, "dsp-clkin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) LN2_PIN_MUX(PSIA1_MCLK, "psia1-mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) LN2_PIN_MUX(PSIA2_MCLK, "psia2-mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) LN2_PIN_MUX(GF_GPIO1, "gf-gpio1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) LN2_PIN_MUX(GF_GPIO5, "gf-gpio5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) LN2_PIN_MUX(DSP_GPIO20, "dsp-gpio20");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) LN2_PIN_GAI(CDC_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) LN2_PIN_GAI(CDC_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) LN2_PIN_GAI(CDC_AIF3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) LN2_PIN_GAI(DSP_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) LN2_PIN_GAI(DSP_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) LN2_PIN_GAI(PSIA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) LN2_PIN_GAI(PSIA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) LN2_PIN_GAI(GF_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) LN2_PIN_GAI(GF_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) LN2_PIN_GAI(GF_AIF3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) LN2_PIN_GAI(GF_AIF4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) LN2_PIN_AIF(SPDIF_AIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) LN2_PIN_AIF(USB_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) LN2_PIN_AIF(USB_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) LN2_PIN_AIF(ADAT_AIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) LN2_PIN_AIF(SOUNDCARD_AIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const struct pinctrl_pin_desc lochnagar1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) LN1_PIN(CDC_RESET), LN1_PIN(DSP_RESET), LN1_PIN(CDC_CIF1MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) LN1_PIN(GF_GPIO2), LN1_PIN(GF_GPIO3), LN1_PIN(GF_GPIO7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) LN1_PIN(LED1), LN1_PIN(LED2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) LN1_PINS(CDC_AIF1), LN1_PINS(CDC_AIF2), LN1_PINS(CDC_AIF3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) LN1_PINS(DSP_AIF1), LN1_PINS(DSP_AIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) LN1_PINS(PSIA1), LN1_PINS(PSIA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) LN1_PINS(SPDIF_AIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) LN1_PINS(GF_AIF1), LN1_PINS(GF_AIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) LN1_PINS(GF_AIF3), LN1_PINS(GF_AIF4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct pinctrl_pin_desc lochnagar2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) LN2_PIN(CDC_RESET), LN2_PIN(DSP_RESET), LN2_PIN(CDC_CIF1MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) LN2_PIN(CDC_LDOENA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) LN2_PIN(SPDIF_HWMODE), LN2_PIN(SPDIF_RESET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) LN2_PIN(FPGA_GPIO1), LN2_PIN(FPGA_GPIO2), LN2_PIN(FPGA_GPIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) LN2_PIN(FPGA_GPIO4), LN2_PIN(FPGA_GPIO5), LN2_PIN(FPGA_GPIO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) LN2_PIN(CDC_GPIO1), LN2_PIN(CDC_GPIO2), LN2_PIN(CDC_GPIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) LN2_PIN(CDC_GPIO4), LN2_PIN(CDC_GPIO5), LN2_PIN(CDC_GPIO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) LN2_PIN(CDC_GPIO7), LN2_PIN(CDC_GPIO8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) LN2_PIN(DSP_GPIO1), LN2_PIN(DSP_GPIO2), LN2_PIN(DSP_GPIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) LN2_PIN(DSP_GPIO4), LN2_PIN(DSP_GPIO5), LN2_PIN(DSP_GPIO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) LN2_PIN(DSP_GPIO20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) LN2_PIN(GF_GPIO1), LN2_PIN(GF_GPIO2), LN2_PIN(GF_GPIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) LN2_PIN(GF_GPIO5), LN2_PIN(GF_GPIO7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) LN2_PINS(CDC_AIF1), LN2_PINS(CDC_AIF2), LN2_PINS(CDC_AIF3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) LN2_PINS(DSP_AIF1), LN2_PINS(DSP_AIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) LN2_PINS(PSIA1), LN2_PINS(PSIA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) LN2_PINS(GF_AIF1), LN2_PINS(GF_AIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) LN2_PINS(GF_AIF3), LN2_PINS(GF_AIF4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) LN2_PIN(DSP_UART1_RX), LN2_PIN(DSP_UART1_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) LN2_PIN(DSP_UART2_RX), LN2_PIN(DSP_UART2_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) LN2_PIN(GF_UART2_RX), LN2_PIN(GF_UART2_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) LN2_PIN(USB_UART_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) LN2_PIN(CDC_PDMCLK1), LN2_PIN(CDC_PDMDAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) LN2_PIN(CDC_PDMCLK2), LN2_PIN(CDC_PDMDAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) LN2_PIN(CDC_DMICCLK1), LN2_PIN(CDC_DMICDAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) LN2_PIN(CDC_DMICCLK2), LN2_PIN(CDC_DMICDAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) LN2_PIN(CDC_DMICCLK3), LN2_PIN(CDC_DMICDAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) LN2_PIN(CDC_DMICCLK4), LN2_PIN(CDC_DMICDAT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) LN2_PIN(DSP_DMICCLK1), LN2_PIN(DSP_DMICDAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) LN2_PIN(DSP_DMICCLK2), LN2_PIN(DSP_DMICDAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) LN2_PIN(I2C2_SCL), LN2_PIN(I2C2_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) LN2_PIN(I2C3_SCL), LN2_PIN(I2C3_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) LN2_PIN(I2C4_SCL), LN2_PIN(I2C4_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) LN2_PIN(DSP_STANDBY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) LN2_PIN(CDC_MCLK1), LN2_PIN(CDC_MCLK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) LN2_PIN(DSP_CLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) LN2_PIN(PSIA1_MCLK), LN2_PIN(PSIA2_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) LN2_PINS(SPDIF_AIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) LN2_PINS(USB_AIF1), LN2_PINS(USB_AIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) LN2_PINS(ADAT_AIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) LN2_PINS(SOUNDCARD_AIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define LN_AIF_PINS(REV, ID) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) LOCHNAGAR##REV##_PIN_##ID##_BCLK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) LOCHNAGAR##REV##_PIN_##ID##_LRCLK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) LOCHNAGAR##REV##_PIN_##ID##_TXDAT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) LOCHNAGAR##REV##_PIN_##ID##_RXDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define LN1_AIF(ID, CTRL) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct lochnagar_aif lochnagar1_##ID##_aif = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .name = LN_##ID##_STR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .pins = { LN_AIF_PINS(1, ID) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .src_reg = LOCHNAGAR1_##ID##_SEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .src_mask = LOCHNAGAR1_SRC_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .ctrl_reg = LOCHNAGAR1_##CTRL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .ena_mask = LOCHNAGAR1_##ID##_ENA_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .master_mask = LOCHNAGAR1_##ID##_LRCLK_DIR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) LOCHNAGAR1_##ID##_BCLK_DIR_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define LN2_AIF(ID) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct lochnagar_aif lochnagar2_##ID##_aif = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .name = LN_##ID##_STR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .pins = { LN_AIF_PINS(2, ID) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .src_reg = LOCHNAGAR2_##ID##_CTRL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .src_mask = LOCHNAGAR2_AIF_SRC_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .ctrl_reg = LOCHNAGAR2_##ID##_CTRL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .ena_mask = LOCHNAGAR2_AIF_ENA_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .master_mask = LOCHNAGAR2_AIF_LRCLK_DIR_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) LOCHNAGAR2_AIF_BCLK_DIR_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct lochnagar_aif {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) const char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int pins[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u16 src_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u16 src_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u16 ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u16 ena_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u16 master_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) LN1_AIF(CDC_AIF1, CDC_AIF_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) LN1_AIF(CDC_AIF2, CDC_AIF_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) LN1_AIF(CDC_AIF3, CDC_AIF_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) LN1_AIF(DSP_AIF1, DSP_AIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) LN1_AIF(DSP_AIF2, DSP_AIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) LN1_AIF(PSIA1, PSIA_AIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) LN1_AIF(PSIA2, PSIA_AIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) LN1_AIF(GF_AIF1, GF_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) LN1_AIF(GF_AIF2, GF_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) LN1_AIF(GF_AIF3, GF_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) LN1_AIF(GF_AIF4, GF_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) LN1_AIF(SPDIF_AIF, EXT_AIF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) LN2_AIF(CDC_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) LN2_AIF(CDC_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) LN2_AIF(CDC_AIF3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) LN2_AIF(DSP_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) LN2_AIF(DSP_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) LN2_AIF(PSIA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) LN2_AIF(PSIA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) LN2_AIF(GF_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) LN2_AIF(GF_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) LN2_AIF(GF_AIF3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) LN2_AIF(GF_AIF4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) LN2_AIF(SPDIF_AIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) LN2_AIF(USB_AIF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) LN2_AIF(USB_AIF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) LN2_AIF(ADAT_AIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) LN2_AIF(SOUNDCARD_AIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define LN2_OP_AIF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define LN2_OP_GPIO 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define LN_FUNC(NAME, TYPE, OP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { .name = NAME, .type = LN_FTYPE_##TYPE, .op = OP }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define LN_FUNC_PIN(REV, ID, OP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) LN_FUNC(lochnagar##REV##_##ID##_pin.name, PIN, OP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define LN1_FUNC_PIN(ID, OP) LN_FUNC_PIN(1, ID, OP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define LN2_FUNC_PIN(ID, OP) LN_FUNC_PIN(2, ID, OP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define LN_FUNC_AIF(REV, ID, OP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) LN_FUNC(lochnagar##REV##_##ID##_aif.name, AIF, OP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define LN1_FUNC_AIF(ID, OP) LN_FUNC_AIF(1, ID, OP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define LN2_FUNC_AIF(ID, OP) LN_FUNC_AIF(2, ID, OP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define LN2_FUNC_GAI(ID, OP, BOP, LROP, RXOP, TXOP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) LN2_FUNC_AIF(ID, OP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) LN_FUNC(lochnagar2_##ID##_BCLK_pin.name, PIN, BOP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) LN_FUNC(lochnagar2_##ID##_LRCLK_pin.name, PIN, LROP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) LN_FUNC(lochnagar2_##ID##_RXDAT_pin.name, PIN, RXOP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) LN_FUNC(lochnagar2_##ID##_TXDAT_pin.name, PIN, TXOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) enum lochnagar_func_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) LN_FTYPE_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) LN_FTYPE_AIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) LN_FTYPE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct lochnagar_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) const char * const name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) enum lochnagar_func_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u8 op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct lochnagar_func lochnagar1_funcs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) LN_FUNC("dsp-gpio1", PIN, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) LN_FUNC("dsp-gpio2", PIN, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) LN_FUNC("dsp-gpio3", PIN, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) LN_FUNC("codec-gpio1", PIN, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) LN_FUNC("codec-gpio2", PIN, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) LN_FUNC("codec-gpio3", PIN, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) LN_FUNC("codec-gpio4", PIN, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) LN_FUNC("codec-gpio5", PIN, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) LN_FUNC("codec-gpio6", PIN, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) LN_FUNC("codec-gpio7", PIN, 0x0A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) LN_FUNC("codec-gpio8", PIN, 0x0B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) LN1_FUNC_PIN(GF_GPIO2, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) LN1_FUNC_PIN(GF_GPIO3, 0x0D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) LN1_FUNC_PIN(GF_GPIO7, 0x0E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) LN1_FUNC_AIF(SPDIF_AIF, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) LN1_FUNC_AIF(PSIA1, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) LN1_FUNC_AIF(PSIA2, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) LN1_FUNC_AIF(CDC_AIF1, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) LN1_FUNC_AIF(CDC_AIF2, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) LN1_FUNC_AIF(CDC_AIF3, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) LN1_FUNC_AIF(DSP_AIF1, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) LN1_FUNC_AIF(DSP_AIF2, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) LN1_FUNC_AIF(GF_AIF3, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) LN1_FUNC_AIF(GF_AIF4, 0x0A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) LN1_FUNC_AIF(GF_AIF1, 0x0B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) LN1_FUNC_AIF(GF_AIF2, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const struct lochnagar_func lochnagar2_funcs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) LN_FUNC("aif", PIN, LN2_OP_AIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) LN2_FUNC_PIN(FPGA_GPIO1, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) LN2_FUNC_PIN(FPGA_GPIO2, 0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) LN2_FUNC_PIN(FPGA_GPIO3, 0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) LN2_FUNC_PIN(FPGA_GPIO4, 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) LN2_FUNC_PIN(FPGA_GPIO5, 0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) LN2_FUNC_PIN(FPGA_GPIO6, 0x06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) LN2_FUNC_PIN(CDC_GPIO1, 0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) LN2_FUNC_PIN(CDC_GPIO2, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) LN2_FUNC_PIN(CDC_GPIO3, 0x09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) LN2_FUNC_PIN(CDC_GPIO4, 0x0A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) LN2_FUNC_PIN(CDC_GPIO5, 0x0B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) LN2_FUNC_PIN(CDC_GPIO6, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) LN2_FUNC_PIN(CDC_GPIO7, 0x0D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) LN2_FUNC_PIN(CDC_GPIO8, 0x0E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) LN2_FUNC_PIN(DSP_GPIO1, 0x0F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) LN2_FUNC_PIN(DSP_GPIO2, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) LN2_FUNC_PIN(DSP_GPIO3, 0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) LN2_FUNC_PIN(DSP_GPIO4, 0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) LN2_FUNC_PIN(DSP_GPIO5, 0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) LN2_FUNC_PIN(DSP_GPIO6, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) LN2_FUNC_PIN(GF_GPIO2, 0x15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) LN2_FUNC_PIN(GF_GPIO3, 0x16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) LN2_FUNC_PIN(GF_GPIO7, 0x17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) LN2_FUNC_PIN(GF_GPIO1, 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) LN2_FUNC_PIN(GF_GPIO5, 0x19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) LN2_FUNC_PIN(DSP_GPIO20, 0x1A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) LN_FUNC("codec-clkout", PIN, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) LN_FUNC("dsp-clkout", PIN, 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) LN_FUNC("pmic-32k", PIN, 0x22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) LN_FUNC("spdif-clkout", PIN, 0x23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) LN_FUNC("clk-12m288", PIN, 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) LN_FUNC("clk-11m2986", PIN, 0x25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) LN_FUNC("clk-24m576", PIN, 0x26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) LN_FUNC("clk-22m5792", PIN, 0x27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) LN_FUNC("xmos-mclk", PIN, 0x29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) LN_FUNC("gf-clkout1", PIN, 0x2A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) LN_FUNC("gf-mclk1", PIN, 0x2B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) LN_FUNC("gf-mclk3", PIN, 0x2C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) LN_FUNC("gf-mclk2", PIN, 0x2D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) LN_FUNC("gf-clkout2", PIN, 0x2E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) LN2_FUNC_PIN(CDC_MCLK1, 0x2F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) LN2_FUNC_PIN(CDC_MCLK2, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) LN2_FUNC_PIN(DSP_CLKIN, 0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) LN2_FUNC_PIN(PSIA1_MCLK, 0x32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) LN2_FUNC_PIN(PSIA2_MCLK, 0x33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) LN_FUNC("spdif-mclk", PIN, 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) LN_FUNC("codec-irq", PIN, 0x42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) LN2_FUNC_PIN(CDC_RESET, 0x43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) LN2_FUNC_PIN(DSP_RESET, 0x44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) LN_FUNC("dsp-irq", PIN, 0x45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) LN2_FUNC_PIN(DSP_STANDBY, 0x46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) LN2_FUNC_PIN(CDC_PDMCLK1, 0x90),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) LN2_FUNC_PIN(CDC_PDMDAT1, 0x91),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) LN2_FUNC_PIN(CDC_PDMCLK2, 0x92),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) LN2_FUNC_PIN(CDC_PDMDAT2, 0x93),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) LN2_FUNC_PIN(CDC_DMICCLK1, 0xA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) LN2_FUNC_PIN(CDC_DMICDAT1, 0xA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) LN2_FUNC_PIN(CDC_DMICCLK2, 0xA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) LN2_FUNC_PIN(CDC_DMICDAT2, 0xA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) LN2_FUNC_PIN(CDC_DMICCLK3, 0xA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) LN2_FUNC_PIN(CDC_DMICDAT3, 0xA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) LN2_FUNC_PIN(CDC_DMICCLK4, 0xA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) LN2_FUNC_PIN(CDC_DMICDAT4, 0xA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) LN2_FUNC_PIN(DSP_DMICCLK1, 0xA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) LN2_FUNC_PIN(DSP_DMICDAT1, 0xA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) LN2_FUNC_PIN(DSP_DMICCLK2, 0xAA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) LN2_FUNC_PIN(DSP_DMICDAT2, 0xAB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) LN2_FUNC_PIN(DSP_UART1_RX, 0xC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) LN2_FUNC_PIN(DSP_UART1_TX, 0xC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) LN2_FUNC_PIN(DSP_UART2_RX, 0xC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) LN2_FUNC_PIN(DSP_UART2_TX, 0xC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) LN2_FUNC_PIN(GF_UART2_RX, 0xC4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) LN2_FUNC_PIN(GF_UART2_TX, 0xC5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) LN2_FUNC_PIN(USB_UART_RX, 0xC6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) LN_FUNC("usb-uart-tx", PIN, 0xC7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) LN2_FUNC_PIN(I2C2_SCL, 0xE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) LN2_FUNC_PIN(I2C2_SDA, 0xE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) LN2_FUNC_PIN(I2C3_SCL, 0xE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) LN2_FUNC_PIN(I2C3_SDA, 0xE3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) LN2_FUNC_PIN(I2C4_SCL, 0xE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) LN2_FUNC_PIN(I2C4_SDA, 0xE5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) LN2_FUNC_AIF(SPDIF_AIF, 0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) LN2_FUNC_GAI(PSIA1, 0x02, 0x50, 0x51, 0x52, 0x53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) LN2_FUNC_GAI(PSIA2, 0x03, 0x54, 0x55, 0x56, 0x57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) LN2_FUNC_GAI(CDC_AIF1, 0x04, 0x59, 0x5B, 0x5A, 0x58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) LN2_FUNC_GAI(CDC_AIF2, 0x05, 0x5D, 0x5F, 0x5E, 0x5C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) LN2_FUNC_GAI(CDC_AIF3, 0x06, 0x61, 0x62, 0x63, 0x60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) LN2_FUNC_GAI(DSP_AIF1, 0x07, 0x65, 0x67, 0x66, 0x64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) LN2_FUNC_GAI(DSP_AIF2, 0x08, 0x69, 0x6B, 0x6A, 0x68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) LN2_FUNC_GAI(GF_AIF3, 0x09, 0x6D, 0x6F, 0x6C, 0x6E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) LN2_FUNC_GAI(GF_AIF4, 0x0A, 0x71, 0x73, 0x70, 0x72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) LN2_FUNC_GAI(GF_AIF1, 0x0B, 0x75, 0x77, 0x74, 0x76),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) LN2_FUNC_GAI(GF_AIF2, 0x0C, 0x79, 0x7B, 0x78, 0x7A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) LN2_FUNC_AIF(USB_AIF1, 0x0D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) LN2_FUNC_AIF(USB_AIF2, 0x0E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) LN2_FUNC_AIF(ADAT_AIF, 0x0F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) LN2_FUNC_AIF(SOUNDCARD_AIF, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define LN_GROUP_PIN(REV, ID) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .name = lochnagar##REV##_##ID##_pin.name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .type = LN_FTYPE_PIN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .pins = &lochnagar##REV##_pins[LOCHNAGAR##REV##_PIN_##ID].number, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .npins = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .priv = &lochnagar##REV##_pins[LOCHNAGAR##REV##_PIN_##ID], \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define LN_GROUP_AIF(REV, ID) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .name = lochnagar##REV##_##ID##_aif.name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .type = LN_FTYPE_AIF, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .pins = lochnagar##REV##_##ID##_aif.pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .npins = ARRAY_SIZE(lochnagar##REV##_##ID##_aif.pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .priv = &lochnagar##REV##_##ID##_aif, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define LN1_GROUP_PIN(ID) LN_GROUP_PIN(1, ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define LN2_GROUP_PIN(ID) LN_GROUP_PIN(2, ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define LN1_GROUP_AIF(ID) LN_GROUP_AIF(1, ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define LN2_GROUP_AIF(ID) LN_GROUP_AIF(2, ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define LN2_GROUP_GAI(ID) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) LN2_GROUP_AIF(ID), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) LN2_GROUP_PIN(ID##_BCLK), LN2_GROUP_PIN(ID##_LRCLK), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) LN2_GROUP_PIN(ID##_RXDAT), LN2_GROUP_PIN(ID##_TXDAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct lochnagar_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) const char * const name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) enum lochnagar_func_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) const void *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const struct lochnagar_group lochnagar1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) LN1_GROUP_PIN(GF_GPIO2), LN1_GROUP_PIN(GF_GPIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) LN1_GROUP_PIN(GF_GPIO7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) LN1_GROUP_PIN(LED1), LN1_GROUP_PIN(LED2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) LN1_GROUP_AIF(CDC_AIF1), LN1_GROUP_AIF(CDC_AIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) LN1_GROUP_AIF(CDC_AIF3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) LN1_GROUP_AIF(DSP_AIF1), LN1_GROUP_AIF(DSP_AIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) LN1_GROUP_AIF(PSIA1), LN1_GROUP_AIF(PSIA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) LN1_GROUP_AIF(GF_AIF1), LN1_GROUP_AIF(GF_AIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) LN1_GROUP_AIF(GF_AIF3), LN1_GROUP_AIF(GF_AIF4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) LN1_GROUP_AIF(SPDIF_AIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const struct lochnagar_group lochnagar2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) LN2_GROUP_PIN(FPGA_GPIO1), LN2_GROUP_PIN(FPGA_GPIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) LN2_GROUP_PIN(FPGA_GPIO3), LN2_GROUP_PIN(FPGA_GPIO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) LN2_GROUP_PIN(FPGA_GPIO5), LN2_GROUP_PIN(FPGA_GPIO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) LN2_GROUP_PIN(CDC_GPIO1), LN2_GROUP_PIN(CDC_GPIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) LN2_GROUP_PIN(CDC_GPIO3), LN2_GROUP_PIN(CDC_GPIO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) LN2_GROUP_PIN(CDC_GPIO5), LN2_GROUP_PIN(CDC_GPIO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) LN2_GROUP_PIN(CDC_GPIO7), LN2_GROUP_PIN(CDC_GPIO8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) LN2_GROUP_PIN(DSP_GPIO1), LN2_GROUP_PIN(DSP_GPIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) LN2_GROUP_PIN(DSP_GPIO3), LN2_GROUP_PIN(DSP_GPIO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) LN2_GROUP_PIN(DSP_GPIO5), LN2_GROUP_PIN(DSP_GPIO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) LN2_GROUP_PIN(DSP_GPIO20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) LN2_GROUP_PIN(GF_GPIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) LN2_GROUP_PIN(GF_GPIO2), LN2_GROUP_PIN(GF_GPIO5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) LN2_GROUP_PIN(GF_GPIO3), LN2_GROUP_PIN(GF_GPIO7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) LN2_GROUP_PIN(DSP_UART1_RX), LN2_GROUP_PIN(DSP_UART1_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) LN2_GROUP_PIN(DSP_UART2_RX), LN2_GROUP_PIN(DSP_UART2_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) LN2_GROUP_PIN(GF_UART2_RX), LN2_GROUP_PIN(GF_UART2_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) LN2_GROUP_PIN(USB_UART_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) LN2_GROUP_PIN(CDC_PDMCLK1), LN2_GROUP_PIN(CDC_PDMDAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) LN2_GROUP_PIN(CDC_PDMCLK2), LN2_GROUP_PIN(CDC_PDMDAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) LN2_GROUP_PIN(CDC_DMICCLK1), LN2_GROUP_PIN(CDC_DMICDAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) LN2_GROUP_PIN(CDC_DMICCLK2), LN2_GROUP_PIN(CDC_DMICDAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) LN2_GROUP_PIN(CDC_DMICCLK3), LN2_GROUP_PIN(CDC_DMICDAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) LN2_GROUP_PIN(CDC_DMICCLK4), LN2_GROUP_PIN(CDC_DMICDAT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) LN2_GROUP_PIN(DSP_DMICCLK1), LN2_GROUP_PIN(DSP_DMICDAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) LN2_GROUP_PIN(DSP_DMICCLK2), LN2_GROUP_PIN(DSP_DMICDAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) LN2_GROUP_PIN(I2C2_SCL), LN2_GROUP_PIN(I2C2_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) LN2_GROUP_PIN(I2C3_SCL), LN2_GROUP_PIN(I2C3_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) LN2_GROUP_PIN(I2C4_SCL), LN2_GROUP_PIN(I2C4_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) LN2_GROUP_PIN(DSP_STANDBY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) LN2_GROUP_PIN(CDC_MCLK1), LN2_GROUP_PIN(CDC_MCLK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) LN2_GROUP_PIN(DSP_CLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) LN2_GROUP_PIN(PSIA1_MCLK), LN2_GROUP_PIN(PSIA2_MCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) LN2_GROUP_GAI(CDC_AIF1), LN2_GROUP_GAI(CDC_AIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) LN2_GROUP_GAI(CDC_AIF3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) LN2_GROUP_GAI(DSP_AIF1), LN2_GROUP_GAI(DSP_AIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) LN2_GROUP_GAI(PSIA1), LN2_GROUP_GAI(PSIA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) LN2_GROUP_GAI(GF_AIF1), LN2_GROUP_GAI(GF_AIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) LN2_GROUP_GAI(GF_AIF3), LN2_GROUP_GAI(GF_AIF4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) LN2_GROUP_AIF(SPDIF_AIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) LN2_GROUP_AIF(USB_AIF1), LN2_GROUP_AIF(USB_AIF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) LN2_GROUP_AIF(ADAT_AIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) LN2_GROUP_AIF(SOUNDCARD_AIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct lochnagar_func_groups {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct lochnagar_pin_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct lochnagar *lochnagar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) const struct lochnagar_func *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) unsigned int nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) const struct lochnagar_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct lochnagar_func_groups func_groups[LN_FTYPE_COUNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static int lochnagar_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return priv->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const char *lochnagar_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned int group_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return priv->groups[group_idx].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int lochnagar_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) unsigned int group_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) *pins = priv->groups[group_idx].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) *num_pins = priv->groups[group_idx].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static const struct pinctrl_ops lochnagar_pin_group_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .get_groups_count = lochnagar_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .get_group_name = lochnagar_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .get_group_pins = lochnagar_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static int lochnagar_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return priv->nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const char *lochnagar_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) unsigned int func_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return priv->funcs[func_idx].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int lochnagar_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) unsigned int func_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) unsigned int * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int func_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) func_type = priv->funcs[func_idx].type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) *groups = priv->func_groups[func_type].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) *num_groups = priv->func_groups[func_type].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int lochnagar2_get_gpio_chan(struct lochnagar_pin_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) unsigned int op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct regmap *regmap = priv->lochnagar->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int free = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) for (i = 0; i < LN2_NUM_GPIO_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = regmap_read(regmap, LOCHNAGAR2_GPIO_CHANNEL1 + i, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) val &= LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (val == op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return i + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (free < 0 && !val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) free = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (free >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ret = regmap_update_bits(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) LOCHNAGAR2_GPIO_CHANNEL1 + free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) free++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) dev_dbg(priv->dev, "Set channel %d to 0x%x\n", free, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static int lochnagar_pin_set_mux(struct lochnagar_pin_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) const struct lochnagar_pin *pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) unsigned int op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) switch (priv->lochnagar->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) case LOCHNAGAR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = lochnagar2_get_gpio_chan(priv, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dev_err(priv->dev, "Failed to get channel for %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) pin->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) op = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_dbg(priv->dev, "Set pin %s to 0x%x\n", pin->name, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ret = regmap_write(priv->lochnagar->regmap, pin->reg, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dev_err(priv->dev, "Failed to set %s mux: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pin->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int lochnagar_aif_set_mux(struct lochnagar_pin_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) const struct lochnagar_group *group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) unsigned int op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct regmap *regmap = priv->lochnagar->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) const struct lochnagar_aif *aif = group->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) const struct lochnagar_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ret = regmap_update_bits(regmap, aif->src_reg, aif->src_mask, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dev_err(priv->dev, "Failed to set %s source: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) group->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret = regmap_update_bits(regmap, aif->ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) aif->ena_mask, aif->ena_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev_err(priv->dev, "Failed to set %s enable: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) group->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) for (i = 0; i < group->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) pin = priv->pins[group->pins[i]].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (pin->type != LN_PTYPE_MUX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_dbg(priv->dev, "Set pin %s to AIF\n", pin->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ret = regmap_update_bits(regmap, pin->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) LOCHNAGAR2_GPIO_SRC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) LN2_OP_AIF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dev_err(priv->dev, "Failed to set %s to AIF: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) pin->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static int lochnagar_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) unsigned int func_idx, unsigned int group_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) const struct lochnagar_func *func = &priv->funcs[func_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) const struct lochnagar_group *group = &priv->groups[group_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) const struct lochnagar_pin *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) switch (func->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) case LN_FTYPE_AIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev_dbg(priv->dev, "Set group %s to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) group->name, func->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return lochnagar_aif_set_mux(priv, group, func->op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) case LN_FTYPE_PIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) pin = priv->pins[*group->pins].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dev_dbg(priv->dev, "Set pin %s to %s\n", pin->name, func->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return lochnagar_pin_set_mux(priv, pin, func->op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static int lochnagar_gpio_request(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct lochnagar *lochnagar = priv->lochnagar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dev_dbg(priv->dev, "Requesting GPIO %s\n", pin->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (lochnagar->type == LOCHNAGAR1 || pin->type != LN_PTYPE_MUX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ret = lochnagar2_get_gpio_chan(priv, LN2_OP_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) dev_err(priv->dev, "Failed to get low channel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = lochnagar2_get_gpio_chan(priv, LN2_OP_GPIO | 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) dev_err(priv->dev, "Failed to get high channel: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int lochnagar_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* The GPIOs only support output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static const struct pinmux_ops lochnagar_pin_mux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .get_functions_count = lochnagar_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .get_function_name = lochnagar_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .get_function_groups = lochnagar_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .set_mux = lochnagar_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .gpio_request_enable = lochnagar_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .gpio_set_direction = lochnagar_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .strict = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int lochnagar_aif_set_master(struct lochnagar_pin_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) unsigned int group_idx, bool master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct regmap *regmap = priv->lochnagar->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) const struct lochnagar_group *group = &priv->groups[group_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) const struct lochnagar_aif *aif = group->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (group->type != LN_FTYPE_AIF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) val = aif->master_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev_dbg(priv->dev, "Set AIF %s to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) group->name, master ? "master" : "slave");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ret = regmap_update_bits(regmap, aif->ctrl_reg, aif->master_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) dev_err(priv->dev, "Failed to set %s mode: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) group->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static int lochnagar_conf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) unsigned int group_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) unsigned int param = pinconf_to_config_param(*configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case PIN_CONFIG_OUTPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ret = lochnagar_aif_set_master(priv, group_idx, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ret = lochnagar_aif_set_master(priv, group_idx, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) configs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static const struct pinconf_ops lochnagar_pin_conf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .pin_config_group_set = lochnagar_conf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static const struct pinctrl_desc lochnagar_pin_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .name = "lochnagar-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .pctlops = &lochnagar_pin_group_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .pmxops = &lochnagar_pin_mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .confops = &lochnagar_pin_conf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static void lochnagar_gpio_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct lochnagar_pin_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct lochnagar *lochnagar = priv->lochnagar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) value = !!value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dev_dbg(priv->dev, "Set GPIO %s to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) pin->name, value ? "high" : "low");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) switch (pin->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) case LN_PTYPE_MUX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) value |= LN2_OP_GPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ret = lochnagar_pin_set_mux(priv, pin, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) case LN_PTYPE_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (pin->invert)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) value = !value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ret = regmap_update_bits(lochnagar->regmap, pin->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) BIT(pin->shift), value << pin->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) dev_err(chip->parent, "Failed to set %s value: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) pin->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static int lochnagar_gpio_direction_out(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) lochnagar_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return pinctrl_gpio_direction_output(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static int lochnagar_fill_func_groups(struct lochnagar_pin_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct lochnagar_func_groups *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) for (i = 0; i < priv->ngroups; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) priv->func_groups[priv->groups[i].type].ngroups++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) for (i = 0; i < LN_FTYPE_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) funcs = &priv->func_groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (!funcs->ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) funcs->groups = devm_kcalloc(priv->dev, funcs->ngroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) sizeof(*funcs->groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (!funcs->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) funcs->ngroups = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) for (i = 0; i < priv->ngroups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) funcs = &priv->func_groups[priv->groups[i].type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) funcs->groups[funcs->ngroups++] = priv->groups[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static int lochnagar_pin_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct lochnagar *lochnagar = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct lochnagar_pin_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct pinctrl_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) priv->lochnagar = lochnagar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) *desc = lochnagar_pin_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) priv->gpio_chip.label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) priv->gpio_chip.request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) priv->gpio_chip.free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) priv->gpio_chip.direction_output = lochnagar_gpio_direction_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) priv->gpio_chip.set = lochnagar_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) priv->gpio_chip.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) priv->gpio_chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) priv->gpio_chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #ifdef CONFIG_OF_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) priv->gpio_chip.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) switch (lochnagar->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) case LOCHNAGAR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) priv->funcs = lochnagar1_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) priv->nfuncs = ARRAY_SIZE(lochnagar1_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) priv->pins = lochnagar1_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) priv->npins = ARRAY_SIZE(lochnagar1_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) priv->groups = lochnagar1_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) priv->ngroups = ARRAY_SIZE(lochnagar1_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) priv->gpio_chip.ngpio = LOCHNAGAR1_PIN_NUM_GPIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) case LOCHNAGAR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) priv->funcs = lochnagar2_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) priv->nfuncs = ARRAY_SIZE(lochnagar2_funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) priv->pins = lochnagar2_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) priv->npins = ARRAY_SIZE(lochnagar2_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) priv->groups = lochnagar2_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) priv->ngroups = ARRAY_SIZE(lochnagar2_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) priv->gpio_chip.ngpio = LOCHNAGAR2_PIN_NUM_GPIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dev_err(dev, "Unknown Lochnagar type: %d\n", lochnagar->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = lochnagar_fill_func_groups(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) desc->pins = priv->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) desc->npins = priv->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) pctl = devm_pinctrl_register(dev, desc, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (IS_ERR(pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ret = PTR_ERR(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) dev_err(priv->dev, "Failed to register pinctrl: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ret = devm_gpiochip_add_data(dev, &priv->gpio_chip, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) dev_err(&pdev->dev, "Failed to register gpiochip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static const struct of_device_id lochnagar_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) { .compatible = "cirrus,lochnagar-pinctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) MODULE_DEVICE_TABLE(of, lochnagar_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static struct platform_driver lochnagar_pin_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .name = "lochnagar-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .of_match_table = of_match_ptr(lochnagar_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .probe = lochnagar_pin_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) module_platform_driver(lochnagar_pin_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) MODULE_DESCRIPTION("Pinctrl driver for Cirrus Logic Lochnagar Board");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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