^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2014-2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * pull up/down, slew and drive strength are also supported in this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Pins from the chipCommonA GPIO can be individually muxed to GPIO function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * through the interaction with the NSP IOMUX controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NSP_CHIP_A_INT_STATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NSP_CHIP_A_INT_MASK 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NSP_GPIO_DATA_IN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NSP_GPIO_DATA_OUT 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NSP_GPIO_OUT_EN 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NSP_GPIO_INT_POLARITY 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NSP_GPIO_INT_MASK 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NSP_GPIO_EVENT 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define NSP_GPIO_EVENT_INT_MASK 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NSP_GPIO_EVENT_INT_POLARITY 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define NSP_CHIP_A_GPIO_INT_BIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* I/O parameters offset for chipcommon A GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define NSP_GPIO_DRV_CTRL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define NSP_GPIO_HYSTERESIS_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define NSP_GPIO_SLEW_RATE_EN 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define NSP_PULL_UP_EN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NSP_PULL_DOWN_EN 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GPIO_DRV_STRENGTH_BITS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * nsp GPIO core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @dev: pointer to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @base: I/O register base for nsp GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @io_ctrl: I/O register base for PINCONF support outside the GPIO block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @gc: GPIO chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @pctl: pointer to pinctrl_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @pctldesc: pinctrl descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @lock: lock to protect access to I/O registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct nsp_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __iomem *io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct irq_chip irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct pinctrl_desc pctldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) enum base_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) IO_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Mapping from PINCONF pins to GPIO pins is 1-to-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline unsigned nsp_pin_to_gpio(unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * nsp GPIO register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @nsp_gpio: nsp GPIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @base_type: reg base to modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @reg: register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @gpio: GPIO pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @set: set or clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int reg, unsigned gpio, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) void __iomem *base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (address == IO_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) base_address = chip->io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) base_address = chip->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val = readl(base_address + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val |= BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val &= ~BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel(val, base_address + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * nsp GPIO register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int reg, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (address == IO_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return !!(readl(chip->base + reg) & BIT(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct gpio_chip *gc = (struct gpio_chip *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct nsp_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long int_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 int_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* go through the entire GPIOs and handle all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (int_status & NSP_CHIP_A_GPIO_INT_BIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int event, level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Get level and edge interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) readl(chip->base + NSP_GPIO_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) level = readl(chip->base + NSP_GPIO_DATA_IN) ^
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) readl(chip->base + NSP_GPIO_INT_POLARITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) level &= readl(chip->base + NSP_GPIO_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int_bits = level | event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for_each_set_bit(bit, &int_bits, gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) generic_handle_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) irq_linear_revmap(gc->irq.domain, bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return int_bits ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void nsp_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct nsp_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 val = BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 trigger_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) trigger_type = irq_get_trigger_type(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) writel(val, chip->base + NSP_GPIO_EVENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @d: IRQ chip data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @unmask: mask/unmask GPIO interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct nsp_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 trigger_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) trigger_type = irq_get_trigger_type(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void nsp_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct nsp_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) nsp_gpio_irq_set_mask(d, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void nsp_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct nsp_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) nsp_gpio_irq_set_mask(d, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct nsp_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) bool level_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) bool falling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) falling = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) falling = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) level_low = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) level_low = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) level_low ? "true" : "false", falling ? "true" : "false");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct nsp_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct nsp_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct nsp_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) val = nsp_get_bit(chip, REG, NSP_GPIO_OUT_EN, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return !val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct nsp_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct nsp_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * Only one group: "gpio_grp", since this local pinctrl device only performs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * GPIO specific PINCONF configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const char *nsp_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return "gpio_grp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct pinctrl_ops nsp_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .get_groups_count = nsp_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .get_group_name = nsp_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (slew)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) bool pull_up, bool pull_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) gpio, pull_up, pull_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) bool *pull_up, bool *pull_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u32 strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 offset, shift, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* make sure drive strength is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (strength < 2 || strength > 16 || (strength % 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) shift = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) offset = NSP_GPIO_DRV_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) strength = (strength / 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) val = readl(chip->io_ctrl + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val &= ~BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) val |= ((strength >> (i-1)) & 0x1) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) writel(val, chip->io_ctrl + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int offset, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) offset = NSP_GPIO_DRV_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) shift = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) val = readl(chip->io_ctrl + offset) & BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) val >>= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *strength += (val << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* convert to mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) *strength = (*strength + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int nsp_pin_config_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int nsp_pin_config_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u16 arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) bool pull_up, pull_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) gpio = nsp_pin_to_gpio(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if ((pull_up == false) && (pull_down == false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (pull_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (pull_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ret = nsp_gpio_get_strength(chip, gpio, &arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned int i, gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) gpio = nsp_pin_to_gpio(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = nsp_gpio_set_pull(chip, gpio, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = nsp_gpio_set_pull(chip, gpio, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ret = nsp_gpio_set_pull(chip, gpio, false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ret = nsp_gpio_set_strength(chip, gpio, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ret = nsp_gpio_set_slew(chip, gpio, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_err(chip->dev, "invalid configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const struct pinconf_ops nsp_pconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .pin_config_get = nsp_pin_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .pin_config_set = nsp_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .pin_config_group_get = nsp_pin_config_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .pin_config_group_set = nsp_pin_config_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * NSP GPIO controller supports some PINCONF related configurations such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * pull up, pull down, slew and drive strength, when the pin is configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * to GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * local GPIO pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int nsp_gpio_register_pinconf(struct nsp_gpio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct pinctrl_desc *pctldesc = &chip->pctldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct gpio_chip *gc = &chip->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) for (i = 0; i < gc->ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pins[i].number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) "gpio-%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (!pins[i].name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pctldesc->name = dev_name(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pctldesc->pctlops = &nsp_pctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pctldesc->pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) pctldesc->npins = gc->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) pctldesc->confops = &nsp_pconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (IS_ERR(chip->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_err(chip->dev, "unable to register pinctrl device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return PTR_ERR(chip->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const struct of_device_id nsp_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {.compatible = "brcm,nsp-gpio-a",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static int nsp_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct nsp_gpio *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_err(&pdev->dev, "Missing ngpios OF property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) chip->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) chip->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (IS_ERR(chip->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_err(dev, "unable to map I/O memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return PTR_ERR(chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) chip->io_ctrl = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (IS_ERR(chip->io_ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_err(dev, "unable to map I/O memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return PTR_ERR(chip->io_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) raw_spin_lock_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) gc = &chip->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) gc->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) gc->can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) gc->ngpio = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) gc->label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) gc->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) gc->of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) gc->request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) gc->free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) gc->direction_input = nsp_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) gc->direction_output = nsp_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) gc->get_direction = nsp_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) gc->set = nsp_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) gc->get = nsp_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* optional GPIO interrupt support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct irq_chip *irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) irqc = &chip->irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) irqc->name = "gpio-a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) irqc->irq_ack = nsp_gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) irqc->irq_mask = nsp_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) irqc->irq_unmask = nsp_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) irqc->irq_set_type = nsp_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) val = readl(chip->base + NSP_CHIP_A_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) val = val | NSP_CHIP_A_GPIO_INT_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Install ISR for this GPIO controller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret = devm_request_irq(dev, irq, nsp_gpio_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) IRQF_SHARED, "gpio-a", &chip->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) girq = &chip->gc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) girq->chip = irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = devm_gpiochip_add_data(dev, gc, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) dev_err(dev, "unable to add GPIO chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = nsp_gpio_register_pinconf(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) dev_err(dev, "unable to register pinconf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static struct platform_driver nsp_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .name = "nsp-gpio-a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .of_match_table = nsp_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .probe = nsp_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int __init nsp_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return platform_driver_register(&nsp_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) arch_initcall_sync(nsp_gpio_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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