^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* Copyright (C) 2016 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This file contains the Northstar2 IOMUX driver that supports group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * based PINMUX configuration. The PWM is functional only when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * corresponding mfio pin group is selected as gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define NS2_NUM_IOMUX 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NS2_NUM_PWM_MUX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NS2_PIN_MUX_BASE0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NS2_PIN_MUX_BASE1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NS2_PIN_CONF_BASE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NS2_MUX_PAD_FUNC1_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define NS2_PIN_SRC_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NS2_PIN_PULL_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NS2_PIN_DRIVE_STRENGTH_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define NS2_PIN_PULL_UP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define NS2_PIN_PULL_DOWN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NS2_PIN_INPUT_EN_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Northstar2 IOMUX register description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @base: base address number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @offset: register offset for mux configuration of a group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @shift: bit shift for mux configuration of a group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @mask: mask bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @alt: alternate function to set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct ns2_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Keep track of Northstar2 IOMUX configuration and prevent double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @ns2_mux: Northstar2 IOMUX register description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @is_configured: flag to indicate whether a mux setting has already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * been configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct ns2_mux_log {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct ns2_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) bool is_configured;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Group based IOMUX configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @name: name of the group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @pins: array of pins used by this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @num_pins: total number of pins used by this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @mux: Northstar2 group based IOMUX configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct ns2_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const unsigned int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const struct ns2_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Northstar2 mux function and supported pin groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @name: name of the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @groups: array of groups that can be supported by this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @num_groups: total number of groups that can be supported by function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct ns2_pin_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const unsigned int num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Northstar2 IOMUX pinctrl core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @pctl: pointer to pinctrl_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @dev: pointer to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @base0: first IOMUX register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @base1: second IOMUX register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @pinconf_base: configuration register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @groups: pointer to array of groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @num_groups: total number of groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @functions: pointer to array of functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @num_functions: total number of functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @mux_log: pointer to the array of mux logs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @lock: lock to protect register access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct ns2_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void __iomem *base0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void __iomem *base1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void __iomem *pinconf_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const struct ns2_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const struct ns2_pin_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct ns2_mux_log *mux_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Pin configuration info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @base: base address number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @offset: register offset from base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @src_shift: slew rate control bit shift in the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @input_en: input enable control bit shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @pull_shift: pull-up/pull-down control bit shift in the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @drive_shift: drive strength control bit shift in the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct ns2_pinconf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int src_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int input_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int pull_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int drive_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Description of a pin in Northstar2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @pin: pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @name: pin name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @pin_conf: pin configuration structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct ns2_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct ns2_pinconf pin_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define NS2_PIN_DESC(p, n, b, o, s, i, pu, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .pin = p, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .pin_conf = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .base = b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .src_shift = s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .input_en = i, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .pull_shift = pu, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .drive_shift = d, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * List of pins in Northstar2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct ns2_pin ns2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) NS2_PIN_DESC(0, "mfio_0", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) NS2_PIN_DESC(1, "mfio_1", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) NS2_PIN_DESC(2, "mfio_2", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) NS2_PIN_DESC(3, "mfio_3", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) NS2_PIN_DESC(4, "mfio_4", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) NS2_PIN_DESC(5, "mfio_5", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) NS2_PIN_DESC(6, "mfio_6", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) NS2_PIN_DESC(7, "mfio_7", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) NS2_PIN_DESC(8, "mfio_8", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) NS2_PIN_DESC(9, "mfio_9", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) NS2_PIN_DESC(10, "mfio_10", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) NS2_PIN_DESC(11, "mfio_11", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) NS2_PIN_DESC(12, "mfio_12", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) NS2_PIN_DESC(13, "mfio_13", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) NS2_PIN_DESC(14, "mfio_14", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) NS2_PIN_DESC(15, "mfio_15", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) NS2_PIN_DESC(16, "mfio_16", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) NS2_PIN_DESC(17, "mfio_17", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) NS2_PIN_DESC(18, "mfio_18", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) NS2_PIN_DESC(19, "mfio_19", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) NS2_PIN_DESC(20, "mfio_20", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) NS2_PIN_DESC(21, "mfio_21", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) NS2_PIN_DESC(22, "mfio_22", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) NS2_PIN_DESC(23, "mfio_23", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) NS2_PIN_DESC(24, "mfio_24", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) NS2_PIN_DESC(25, "mfio_25", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) NS2_PIN_DESC(26, "mfio_26", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) NS2_PIN_DESC(27, "mfio_27", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) NS2_PIN_DESC(28, "mfio_28", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) NS2_PIN_DESC(29, "mfio_29", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) NS2_PIN_DESC(30, "mfio_30", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) NS2_PIN_DESC(31, "mfio_31", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) NS2_PIN_DESC(32, "mfio_32", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) NS2_PIN_DESC(33, "mfio_33", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) NS2_PIN_DESC(34, "mfio_34", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) NS2_PIN_DESC(35, "mfio_35", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) NS2_PIN_DESC(36, "mfio_36", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) NS2_PIN_DESC(37, "mfio_37", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) NS2_PIN_DESC(38, "mfio_38", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) NS2_PIN_DESC(39, "mfio_39", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) NS2_PIN_DESC(40, "mfio_40", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) NS2_PIN_DESC(41, "mfio_41", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) NS2_PIN_DESC(42, "mfio_42", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) NS2_PIN_DESC(43, "mfio_43", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) NS2_PIN_DESC(44, "mfio_44", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) NS2_PIN_DESC(45, "mfio_45", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) NS2_PIN_DESC(46, "mfio_46", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) NS2_PIN_DESC(47, "mfio_47", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) NS2_PIN_DESC(48, "mfio_48", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) NS2_PIN_DESC(49, "mfio_49", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) NS2_PIN_DESC(50, "mfio_50", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) NS2_PIN_DESC(51, "mfio_51", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) NS2_PIN_DESC(52, "mfio_52", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) NS2_PIN_DESC(53, "mfio_53", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) NS2_PIN_DESC(54, "mfio_54", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) NS2_PIN_DESC(55, "mfio_55", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) NS2_PIN_DESC(56, "mfio_56", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) NS2_PIN_DESC(57, "mfio_57", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) NS2_PIN_DESC(58, "mfio_58", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) NS2_PIN_DESC(59, "mfio_59", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) NS2_PIN_DESC(60, "mfio_60", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) NS2_PIN_DESC(61, "mfio_61", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) NS2_PIN_DESC(62, "mfio_62", -1, 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) NS2_PIN_DESC(63, "qspi_wp", 2, 0x0, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) NS2_PIN_DESC(64, "qspi_hold", 2, 0x0, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) NS2_PIN_DESC(65, "qspi_cs", 2, 0x0, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) NS2_PIN_DESC(66, "qspi_sck", 2, 0x0, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) NS2_PIN_DESC(67, "uart3_sin", 2, 0x04, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) NS2_PIN_DESC(68, "uart3_sout", 2, 0x04, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) NS2_PIN_DESC(69, "qspi_mosi", 2, 0x04, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) NS2_PIN_DESC(70, "qspi_miso", 2, 0x04, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) NS2_PIN_DESC(71, "spi0_fss", 2, 0x08, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) NS2_PIN_DESC(72, "spi0_rxd", 2, 0x08, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) NS2_PIN_DESC(73, "spi0_txd", 2, 0x08, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) NS2_PIN_DESC(74, "spi0_sck", 2, 0x08, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) NS2_PIN_DESC(75, "spi1_fss", 2, 0x0c, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) NS2_PIN_DESC(76, "spi1_rxd", 2, 0x0c, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) NS2_PIN_DESC(77, "spi1_txd", 2, 0x0c, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) NS2_PIN_DESC(78, "spi1_sck", 2, 0x0c, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) NS2_PIN_DESC(79, "sdio0_data7", 2, 0x10, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) NS2_PIN_DESC(80, "sdio0_emmc_rst", 2, 0x10, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) NS2_PIN_DESC(81, "sdio0_led_on", 2, 0x10, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) NS2_PIN_DESC(82, "sdio0_wp", 2, 0x10, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) NS2_PIN_DESC(83, "sdio0_data3", 2, 0x14, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) NS2_PIN_DESC(84, "sdio0_data4", 2, 0x14, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) NS2_PIN_DESC(85, "sdio0_data5", 2, 0x14, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) NS2_PIN_DESC(86, "sdio0_data6", 2, 0x14, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) NS2_PIN_DESC(87, "sdio0_cmd", 2, 0x18, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) NS2_PIN_DESC(88, "sdio0_data0", 2, 0x18, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) NS2_PIN_DESC(89, "sdio0_data1", 2, 0x18, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) NS2_PIN_DESC(90, "sdio0_data2", 2, 0x18, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) NS2_PIN_DESC(91, "sdio1_led_on", 2, 0x1c, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) NS2_PIN_DESC(92, "sdio1_wp", 2, 0x1c, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) NS2_PIN_DESC(93, "sdio0_cd_l", 2, 0x1c, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) NS2_PIN_DESC(94, "sdio0_clk", 2, 0x1c, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) NS2_PIN_DESC(95, "sdio1_data5", 2, 0x20, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) NS2_PIN_DESC(96, "sdio1_data6", 2, 0x20, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) NS2_PIN_DESC(97, "sdio1_data7", 2, 0x20, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) NS2_PIN_DESC(98, "sdio1_emmc_rst", 2, 0x20, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) NS2_PIN_DESC(99, "sdio1_data1", 2, 0x24, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) NS2_PIN_DESC(100, "sdio1_data2", 2, 0x24, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) NS2_PIN_DESC(101, "sdio1_data3", 2, 0x24, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) NS2_PIN_DESC(102, "sdio1_data4", 2, 0x24, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) NS2_PIN_DESC(103, "sdio1_cd_l", 2, 0x28, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) NS2_PIN_DESC(104, "sdio1_clk", 2, 0x28, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) NS2_PIN_DESC(105, "sdio1_cmd", 2, 0x28, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) NS2_PIN_DESC(106, "sdio1_data0", 2, 0x28, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) NS2_PIN_DESC(107, "ext_mdio_0", 2, 0x2c, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) NS2_PIN_DESC(108, "ext_mdc_0", 2, 0x2c, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) NS2_PIN_DESC(109, "usb3_p1_vbus_ppc", 2, 0x34, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) NS2_PIN_DESC(110, "usb3_p1_overcurrent", 2, 0x34, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) NS2_PIN_DESC(111, "usb3_p0_vbus_ppc", 2, 0x34, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) NS2_PIN_DESC(112, "usb3_p0_overcurrent", 2, 0x34, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) NS2_PIN_DESC(113, "usb2_presence_indication", 2, 0x38, 31, 30, 27, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) NS2_PIN_DESC(114, "usb2_vbus_present", 2, 0x38, 23, 22, 19, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) NS2_PIN_DESC(115, "usb2_vbus_ppc", 2, 0x38, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) NS2_PIN_DESC(116, "usb2_overcurrent", 2, 0x38, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) NS2_PIN_DESC(117, "sata_led1", 2, 0x3c, 15, 14, 11, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) NS2_PIN_DESC(118, "sata_led0", 2, 0x3c, 7, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * List of groups of pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const unsigned int nand_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const unsigned int nor_data_pins[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const unsigned int gpio_0_1_pins[] = {24, 25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const unsigned int pwm_0_pins[] = {24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const unsigned int pwm_1_pins[] = {25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const unsigned int uart1_ext_clk_pins[] = {26};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const unsigned int nor_adv_pins[] = {26};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const unsigned int gpio_2_5_pins[] = {27, 28, 29, 30};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const unsigned int pcie_ab1_clk_wak_pins[] = {27, 28, 29, 30};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const unsigned int nor_addr_0_3_pins[] = {27, 28, 29, 30};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const unsigned int pwm_2_pins[] = {27};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const unsigned int pwm_3_pins[] = {28};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const unsigned int gpio_6_7_pins[] = {31, 32};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const unsigned int pcie_a3_clk_wak_pins[] = {31, 32};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const unsigned int nor_addr_4_5_pins[] = {31, 32};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const unsigned int gpio_8_9_pins[] = {33, 34};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const unsigned int pcie_b3_clk_wak_pins[] = {33, 34};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const unsigned int nor_addr_6_7_pins[] = {33, 34};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const unsigned int gpio_10_11_pins[] = {35, 36};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const unsigned int pcie_b2_clk_wak_pins[] = {35, 36};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const unsigned int nor_addr_8_9_pins[] = {35, 36};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const unsigned int gpio_12_13_pins[] = {37, 38};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const unsigned int pcie_a2_clk_wak_pins[] = {37, 38};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const unsigned int nor_addr_10_11_pins[] = {37, 38};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const unsigned int gpio_14_17_pins[] = {39, 40, 41, 42};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const unsigned int uart0_modem_pins[] = {39, 40, 41, 42};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const unsigned int nor_addr_12_15_pins[] = {39, 40, 41, 42};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const unsigned int gpio_18_19_pins[] = {43, 44};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const unsigned int uart0_rts_cts_pins[] = {43, 44};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const unsigned int gpio_20_21_pins[] = {45, 46};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const unsigned int uart0_in_out_pins[] = {45, 46};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const unsigned int gpio_22_23_pins[] = {47, 48};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const unsigned int uart1_dcd_dsr_pins[] = {47, 48};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const unsigned int gpio_24_25_pins[] = {49, 50};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const unsigned int uart1_ri_dtr_pins[] = {49, 50};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const unsigned int gpio_26_27_pins[] = {51, 52};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const unsigned int uart1_rts_cts_pins[] = {51, 52};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const unsigned int gpio_28_29_pins[] = {53, 54};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const unsigned int uart1_in_out_pins[] = {53, 54};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const unsigned int gpio_30_31_pins[] = {55, 56};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const unsigned int uart2_rts_cts_pins[] = {55, 56};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define NS2_PIN_GROUP(group_name, ba, off, sh, ma, al) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .name = __stringify(group_name) "_grp", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .pins = group_name ## _pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .num_pins = ARRAY_SIZE(group_name ## _pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .mux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .base = ba, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .offset = off, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .shift = sh, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .mask = ma, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .alt = al, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * List of Northstar2 pin groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const struct ns2_pin_group ns2_pin_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) NS2_PIN_GROUP(nand, 0, 0, 31, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) NS2_PIN_GROUP(nor_data, 0, 0, 31, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) NS2_PIN_GROUP(gpio_0_1, 0, 0, 31, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) NS2_PIN_GROUP(uart1_ext_clk, 0, 4, 30, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) NS2_PIN_GROUP(nor_adv, 0, 4, 30, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) NS2_PIN_GROUP(gpio_2_5, 0, 4, 28, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) NS2_PIN_GROUP(pcie_ab1_clk_wak, 0, 4, 28, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) NS2_PIN_GROUP(nor_addr_0_3, 0, 4, 28, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) NS2_PIN_GROUP(gpio_6_7, 0, 4, 26, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) NS2_PIN_GROUP(pcie_a3_clk_wak, 0, 4, 26, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) NS2_PIN_GROUP(nor_addr_4_5, 0, 4, 26, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) NS2_PIN_GROUP(gpio_8_9, 0, 4, 24, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) NS2_PIN_GROUP(pcie_b3_clk_wak, 0, 4, 24, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) NS2_PIN_GROUP(nor_addr_6_7, 0, 4, 24, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) NS2_PIN_GROUP(gpio_10_11, 0, 4, 22, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) NS2_PIN_GROUP(pcie_b2_clk_wak, 0, 4, 22, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) NS2_PIN_GROUP(nor_addr_8_9, 0, 4, 22, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) NS2_PIN_GROUP(gpio_12_13, 0, 4, 20, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) NS2_PIN_GROUP(pcie_a2_clk_wak, 0, 4, 20, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) NS2_PIN_GROUP(nor_addr_10_11, 0, 4, 20, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) NS2_PIN_GROUP(gpio_14_17, 0, 4, 18, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) NS2_PIN_GROUP(uart0_modem, 0, 4, 18, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) NS2_PIN_GROUP(nor_addr_12_15, 0, 4, 18, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) NS2_PIN_GROUP(gpio_18_19, 0, 4, 16, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) NS2_PIN_GROUP(uart0_rts_cts, 0, 4, 16, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) NS2_PIN_GROUP(gpio_20_21, 0, 4, 14, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) NS2_PIN_GROUP(uart0_in_out, 0, 4, 14, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) NS2_PIN_GROUP(gpio_22_23, 0, 4, 12, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) NS2_PIN_GROUP(uart1_dcd_dsr, 0, 4, 12, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) NS2_PIN_GROUP(gpio_24_25, 0, 4, 10, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) NS2_PIN_GROUP(uart1_ri_dtr, 0, 4, 10, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) NS2_PIN_GROUP(gpio_26_27, 0, 4, 8, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) NS2_PIN_GROUP(uart1_rts_cts, 0, 4, 8, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) NS2_PIN_GROUP(gpio_28_29, 0, 4, 6, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) NS2_PIN_GROUP(uart1_in_out, 0, 4, 6, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) NS2_PIN_GROUP(gpio_30_31, 0, 4, 4, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) NS2_PIN_GROUP(uart2_rts_cts, 0, 4, 4, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) NS2_PIN_GROUP(pwm_0, 1, 0, 0, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) NS2_PIN_GROUP(pwm_1, 1, 0, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) NS2_PIN_GROUP(pwm_2, 1, 0, 2, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) NS2_PIN_GROUP(pwm_3, 1, 0, 3, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * List of groups supported by functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const char * const nand_grps[] = {"nand_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const char * const nor_grps[] = {"nor_data_grp", "nor_adv_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) "nor_addr_0_3_grp", "nor_addr_4_5_grp", "nor_addr_6_7_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) "nor_addr_8_9_grp", "nor_addr_10_11_grp", "nor_addr_12_15_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const char * const gpio_grps[] = {"gpio_0_1_grp", "gpio_2_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "gpio_6_7_grp", "gpio_8_9_grp", "gpio_10_11_grp", "gpio_12_13_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "gpio_14_17_grp", "gpio_18_19_grp", "gpio_20_21_grp", "gpio_22_23_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) "gpio_24_25_grp", "gpio_26_27_grp", "gpio_28_29_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "gpio_30_31_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const char * const pcie_grps[] = {"pcie_ab1_clk_wak_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp", "pcie_b2_clk_wak_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "pcie_a2_clk_wak_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const char * const uart0_grps[] = {"uart0_modem_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "uart0_rts_cts_grp", "uart0_in_out_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const char * const uart1_grps[] = {"uart1_ext_clk_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp", "uart1_rts_cts_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "uart1_in_out_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const char * const uart2_grps[] = {"uart2_rts_cts_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const char * const pwm_grps[] = {"pwm_0_grp", "pwm_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "pwm_2_grp", "pwm_3_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define NS2_PIN_FUNCTION(func) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .name = #func, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .groups = func ## _grps, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .num_groups = ARRAY_SIZE(func ## _grps), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * List of supported functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct ns2_pin_function ns2_pin_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) NS2_PIN_FUNCTION(nand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) NS2_PIN_FUNCTION(nor),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) NS2_PIN_FUNCTION(gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) NS2_PIN_FUNCTION(pcie),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) NS2_PIN_FUNCTION(uart0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) NS2_PIN_FUNCTION(uart1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) NS2_PIN_FUNCTION(uart2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) NS2_PIN_FUNCTION(pwm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int ns2_get_groups_count(struct pinctrl_dev *pctrl_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return pinctrl->num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const char *ns2_get_group_name(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return pinctrl->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int ns2_get_group_pins(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned int selector, const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) *pins = pinctrl->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) *num_pins = pinctrl->groups[selector].num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static void ns2_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct seq_file *s, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) seq_printf(s, " %s", dev_name(pctrl_dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const struct pinctrl_ops ns2_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .get_groups_count = ns2_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .get_group_name = ns2_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .get_group_pins = ns2_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .pin_dbg_show = ns2_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int ns2_get_functions_count(struct pinctrl_dev *pctrl_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return pinctrl->num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static const char *ns2_get_function_name(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return pinctrl->functions[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int ns2_get_function_groups(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned int * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) *groups = pinctrl->functions[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) *num_groups = pinctrl->functions[selector].num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static int ns2_pinmux_set(struct ns2_pinctrl *pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) const struct ns2_pin_function *func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) const struct ns2_pin_group *grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct ns2_mux_log *mux_log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) const struct ns2_mux *mux = &grp->mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u32 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) void __iomem *base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) for (i = 0; i < NS2_NUM_IOMUX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if ((mux->shift != mux_log[i].mux.shift) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) (mux->base != mux_log[i].mux.base) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) (mux->offset != mux_log[i].mux.offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* if this is a new configuration, just do it! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!mux_log[i].is_configured)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * IOMUX has been configured previously and one is trying to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * configure it to a different function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (mux_log[i].mux.alt != mux->alt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dev_err(pinctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) "double configuration error detected!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_err(pinctrl->dev, "func:%s grp:%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) func->name, grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (i == NS2_NUM_IOMUX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) mask = mux->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mux_log[i].mux.alt = mux->alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) mux_log[i].is_configured = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) switch (mux->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case NS2_PIN_MUX_BASE0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) base_address = pinctrl->base0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case NS2_PIN_MUX_BASE1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) base_address = pinctrl->base1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) spin_lock_irqsave(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) val = readl(base_address + grp->mux.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) val &= ~(mask << grp->mux.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) val |= grp->mux.alt << grp->mux.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) writel(val, (base_address + grp->mux.offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) spin_unlock_irqrestore(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int ns2_pinmux_enable(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) unsigned int func_select, unsigned int grp_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) const struct ns2_pin_function *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) const struct ns2_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (grp_select >= pinctrl->num_groups ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) func_select >= pinctrl->num_functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) func = &pinctrl->functions[func_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) grp = &pinctrl->groups[grp_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) func_select, func->name, grp_select, grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) grp->mux.offset, grp->mux.shift, grp->mux.alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return ns2_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static int ns2_pin_set_enable(struct pinctrl_dev *pctrldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u16 enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) void __iomem *base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) base_address = pinctrl->pinconf_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) spin_lock_irqsave(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) val = readl(base_address + pin_data->pin_conf.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.input_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) val |= NS2_PIN_INPUT_EN_MASK << pin_data->pin_conf.input_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) writel(val, (base_address + pin_data->pin_conf.offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) spin_unlock_irqrestore(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_dbg(pctrldev->dev, "pin:%u set enable:%d\n", pin, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static int ns2_pin_get_enable(struct pinctrl_dev *pctrldev, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) spin_lock_irqsave(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) enable = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) enable = (enable >> pin_data->pin_conf.input_en) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) NS2_PIN_INPUT_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) spin_unlock_irqrestore(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) enable = NS2_PIN_INPUT_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev_dbg(pctrldev->dev, "pin:%u get disable:%d\n", pin, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int ns2_pin_set_slew(struct pinctrl_dev *pctrldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u32 slew)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) void __iomem *base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) base_address = pinctrl->pinconf_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) spin_lock_irqsave(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) val = readl(base_address + pin_data->pin_conf.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) val &= ~(NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (slew)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) val |= NS2_PIN_SRC_MASK << pin_data->pin_conf.src_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) writel(val, (base_address + pin_data->pin_conf.offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) spin_unlock_irqrestore(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev_dbg(pctrldev->dev, "pin:%u set slew:%d\n", pin, slew);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static int ns2_pin_get_slew(struct pinctrl_dev *pctrldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) u16 *slew)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) spin_lock_irqsave(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) *slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) spin_unlock_irqrestore(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dev_dbg(pctrldev->dev, "pin:%u get slew:%d\n", pin, *slew);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int ns2_pin_set_pull(struct pinctrl_dev *pctrldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) bool pull_up, bool pull_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) void __iomem *base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) base_address = pinctrl->pinconf_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) spin_lock_irqsave(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) val = readl(base_address + pin_data->pin_conf.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) val &= ~(NS2_PIN_PULL_MASK << pin_data->pin_conf.pull_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (pull_up == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) val |= NS2_PIN_PULL_UP << pin_data->pin_conf.pull_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (pull_down == true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) val |= NS2_PIN_PULL_DOWN << pin_data->pin_conf.pull_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) writel(val, (base_address + pin_data->pin_conf.offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) spin_unlock_irqrestore(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev_dbg(pctrldev->dev, "pin:%u set pullup:%d pulldown: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pin, pull_up, pull_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static void ns2_pin_get_pull(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) unsigned int pin, bool *pull_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) bool *pull_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) spin_lock_irqsave(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) val = (val >> pin_data->pin_conf.pull_shift) & NS2_PIN_PULL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) *pull_up = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) *pull_down = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (val == NS2_PIN_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) *pull_up = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (val == NS2_PIN_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) *pull_down = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) spin_unlock_irqrestore(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static int ns2_pin_set_strength(struct pinctrl_dev *pctrldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) void __iomem *base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* make sure drive strength is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (strength < 2 || strength > 16 || (strength % 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) base_address = pinctrl->pinconf_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) spin_lock_irqsave(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) val = readl(base_address + pin_data->pin_conf.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) val &= ~(NS2_PIN_DRIVE_STRENGTH_MASK << pin_data->pin_conf.drive_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) val |= ((strength / 2) - 1) << pin_data->pin_conf.drive_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) writel(val, (base_address + pin_data->pin_conf.offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) spin_unlock_irqrestore(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dev_dbg(pctrldev->dev, "pin:%u set drive strength:%d mA\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pin, strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int ns2_pin_get_strength(struct pinctrl_dev *pctrldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) spin_lock_irqsave(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) *strength = (val >> pin_data->pin_conf.drive_shift) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) NS2_PIN_DRIVE_STRENGTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) *strength = (*strength + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) spin_unlock_irqrestore(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev_dbg(pctrldev->dev, "pin:%u get drive strength:%d mA\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) pin, *strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static int ns2_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct ns2_pin *pin_data = pctldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) bool pull_up, pull_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u16 arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (pin_data->pin_conf.base == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if ((pull_up == false) && (pull_down == false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (pull_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ns2_pin_get_pull(pctldev, pin, &pull_up, &pull_down);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (pull_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ret = ns2_pin_get_strength(pctldev, pin, &arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ret = ns2_pin_get_slew(pctldev, pin, &arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ret = ns2_pin_get_enable(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int ns2_pin_config_set(struct pinctrl_dev *pctrldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct ns2_pin *pin_data = pctrldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) int ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (pin_data->pin_conf.base == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret = ns2_pin_set_pull(pctrldev, pin, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = ns2_pin_set_pull(pctrldev, pin, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ret = ns2_pin_set_pull(pctrldev, pin, false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ret = ns2_pin_set_strength(pctrldev, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ret = ns2_pin_set_slew(pctrldev, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = ns2_pin_set_enable(pctrldev, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) dev_err(pctrldev->dev, "invalid configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const struct pinmux_ops ns2_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .get_functions_count = ns2_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .get_function_name = ns2_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .get_function_groups = ns2_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .set_mux = ns2_pinmux_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static const struct pinconf_ops ns2_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .pin_config_get = ns2_pin_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .pin_config_set = ns2_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static struct pinctrl_desc ns2_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .name = "ns2-pinmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .pctlops = &ns2_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .pmxops = &ns2_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .confops = &ns2_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct ns2_mux_log *log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) pinctrl->mux_log = devm_kcalloc(pinctrl->dev, NS2_NUM_IOMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) sizeof(struct ns2_mux_log),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (!pinctrl->mux_log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) for (i = 0; i < NS2_NUM_IOMUX; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) pinctrl->mux_log[i].is_configured = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* Group 0 uses bit 31 in the IOMUX_PAD_FUNCTION_0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) log = &pinctrl->mux_log[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) log->mux.base = NS2_PIN_MUX_BASE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) log->mux.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) log->mux.shift = 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) log->mux.alt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * Groups 1 through 14 use two bits each in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * IOMUX_PAD_FUNCTION_1 register starting with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * bit position 30.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) for (i = 1; i < (NS2_NUM_IOMUX - NS2_NUM_PWM_MUX); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) log = &pinctrl->mux_log[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) log->mux.base = NS2_PIN_MUX_BASE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) log->mux.offset = NS2_MUX_PAD_FUNC1_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) log->mux.shift = 32 - (i * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) log->mux.alt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * Groups 15 through 18 use one bit each in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * AUX_SEL register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) for (i = 0; i < NS2_NUM_PWM_MUX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) log = &pinctrl->mux_log[(NS2_NUM_IOMUX - NS2_NUM_PWM_MUX) + i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) log->mux.base = NS2_PIN_MUX_BASE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) log->mux.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) log->mux.shift = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) log->mux.alt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int ns2_pinmux_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct ns2_pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) unsigned int num_pins = ARRAY_SIZE(ns2_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (!pinctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) pinctrl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) platform_set_drvdata(pdev, pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) spin_lock_init(&pinctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (IS_ERR(pinctrl->base0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return PTR_ERR(pinctrl->base0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (!pinctrl->base1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev_err(&pdev->dev, "unable to map I/O space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (IS_ERR(pinctrl->pinconf_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return PTR_ERR(pinctrl->pinconf_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret = ns2_mux_log_init(pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) for (i = 0; i < num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) pins[i].number = ns2_pins[i].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) pins[i].name = ns2_pins[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) pins[i].drv_data = &ns2_pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) pinctrl->groups = ns2_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) pinctrl->num_groups = ARRAY_SIZE(ns2_pin_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) pinctrl->functions = ns2_pin_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ns2_pinctrl_desc.pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ns2_pinctrl_desc.npins = num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (IS_ERR(pinctrl->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return PTR_ERR(pinctrl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static const struct of_device_id ns2_pinmux_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {.compatible = "brcm,ns2-pinmux"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static struct platform_driver ns2_pinmux_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) .name = "ns2-pinmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) .of_match_table = ns2_pinmux_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .probe = ns2_pinmux_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static int __init ns2_pinmux_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return platform_driver_register(&ns2_pinmux_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) arch_initcall(ns2_pinmux_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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