^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014-2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file contains the Broadcom Iproc GPIO driver that supports 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * GPIO controllers on Iproc including the ASIU GPIO controller, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * PINCONF such as bias pull up/down, and drive strength are also supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * in this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * It provides the functionality where pins from the GPIO can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * individually muxed to GPIO function, if individual pad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * configuration is supported, through the interaction with respective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * SoCs IOMUX controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IPROC_GPIO_DATA_IN_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IPROC_GPIO_DATA_OUT_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IPROC_GPIO_OUT_EN_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IPROC_GPIO_INT_TYPE_OFFSET 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IPROC_GPIO_INT_DE_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IPROC_GPIO_INT_EDGE_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IPROC_GPIO_INT_MSK_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IPROC_GPIO_INT_STAT_OFFSET 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IPROC_GPIO_INT_CLR_OFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IPROC_GPIO_PAD_RES_OFFSET 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IPROC_GPIO_RES_EN_OFFSET 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* drive strength control for ASIU GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* pinconf for CCM GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IPROC_GPIO_PULL_DN_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IPROC_GPIO_PULL_UP_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* pinconf for CRMU(aon) GPIO and CCM GPIO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IPROC_GPIO_DRV_CTRL_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GPIO_BANK_SIZE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define NGPIOS_PER_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPIO_DRV_STRENGTH_BIT_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPIO_DRV_STRENGTH_BITS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) enum iproc_pinconf_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) IPROC_PINCONF_DRIVE_STRENGTH = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) IPROC_PINCONF_BIAS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) IPROC_PINCONF_BIAS_PULL_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) IPROC_PINCONF_BIAS_PULL_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) IPROC_PINCON_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) enum iproc_pinconf_ctrl_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) IOCTRL_TYPE_AON = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) IOCTRL_TYPE_CDRU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) IOCTRL_TYPE_INVALID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Iproc GPIO core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @dev: pointer to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @base: I/O register base for Iproc GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @io_ctrl: I/O register base for certain type of Iproc GPIO controller that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * has the PINCONF support implemented outside of the GPIO block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @lock: lock to protect access to I/O registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @gc: GPIO chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @pinmux_is_supported: flag to indicate this GPIO controller contains pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * that can be individually muxed to GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @pinconf_disable: contains a list of PINCONF parameters that need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @nr_pinconf_disable: total number of PINCONF parameters that need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @pctl: pointer to pinctrl_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @pctldesc: pinctrl descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct iproc_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void __iomem *io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) enum iproc_pinconf_ctrl_type io_ctrl_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct irq_chip irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned num_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bool pinmux_is_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum pin_config_param *pinconf_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int nr_pinconf_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct pinctrl_desc pctldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Mapping from PINCONF pins to GPIO pins is 1-to-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline unsigned iproc_pin_to_gpio(unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * iproc_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Iproc GPIO register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @chip: Iproc GPIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @reg: register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @gpio: GPIO pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @set: set or clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned gpio, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int offset = IPROC_GPIO_REG(gpio, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int shift = IPROC_GPIO_SHIFT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) val = readl(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val |= BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) val &= ~BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) writel(val, chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int offset = IPROC_GPIO_REG(gpio, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int shift = IPROC_GPIO_SHIFT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return !!(readl(chip->base + offset) & BIT(shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void iproc_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct irq_chip *irq_chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int i, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) chained_irq_enter(irq_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* go through the entire GPIO banks and handle all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) for (i = 0; i < chip->num_banks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) IPROC_GPIO_INT_MSTAT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned pin = NGPIOS_PER_BANK * i + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int child_irq = irq_find_mapping(gc->irq.domain, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Clear the interrupt before invoking the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * handler, so we do not leave any window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) IPROC_GPIO_INT_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) generic_handle_irq(child_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) chained_irq_exit(irq_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void iproc_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned int offset = IPROC_GPIO_REG(gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) IPROC_GPIO_INT_CLR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned int shift = IPROC_GPIO_SHIFT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 val = BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) writel(val, chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * iproc_gpio_irq_set_mask - mask/unmask a GPIO interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @d: IRQ chip data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @unmask: mask/unmask GPIO interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void iproc_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) iproc_gpio_irq_set_mask(d, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void iproc_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) iproc_gpio_irq_set_mask(d, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) bool level_triggered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bool dual_edge = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) bool rising_or_high = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) rising_or_high = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dual_edge = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) level_triggered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) rising_or_high = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) level_triggered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) level_triggered);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) rising_or_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_dbg(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) gpio, level_triggered, dual_edge, rising_or_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) unsigned gpio = gc->base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* not all Iproc GPIO pins can be muxed individually */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!chip->pinmux_is_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return pinctrl_gpio_request(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned gpio = gc->base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!chip->pinmux_is_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) pinctrl_gpio_free(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned int shift = IPROC_GPIO_SHIFT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (readl(chip->base + offset) & BIT(shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct iproc_gpio *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int offset = IPROC_GPIO_REG(gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) IPROC_GPIO_DATA_IN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned int shift = IPROC_GPIO_SHIFT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return !!(readl(chip->base + offset) & BIT(shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * Mapping of the iProc PINCONF parameters to the generic pin configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const enum pin_config_param iproc_pinconf_disable_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) [IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) [IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) [IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) enum pin_config_param param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!chip->nr_pinconf_disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) for (i = 0; i < chip->nr_pinconf_disable; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (chip->pinconf_disable[i] == param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned long disable_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int bit, nbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* figure out total number of PINCONF parameters to disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) for_each_set_bit(bit, &disable_mask, map_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) nbits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!nbits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * Allocate an array to store PINCONF parameters that need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) sizeof(*chip->pinconf_disable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!chip->pinconf_disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) chip->nr_pinconf_disable = nbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* now store these parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) nbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) for_each_set_bit(bit, &disable_mask, map_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * Only one group: "gpio_grp", since this local pinctrl device only performs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * GPIO specific PINCONF configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return "gpio_grp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct pinctrl_ops iproc_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .get_groups_count = iproc_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .get_group_name = iproc_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) bool disable, bool pull_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 val_1, val_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) base = chip->io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) shift = IPROC_GPIO_SHIFT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* no pull-up or pull-down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) val_1 &= ~BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) val_2 &= ~BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) } else if (pull_up) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) val_1 |= BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) val_2 &= ~BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) val_1 &= ~BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) val_2 |= BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pull_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) bool *disable, bool *pull_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 val_1, val_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) base = chip->io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) shift = IPROC_GPIO_SHIFT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *pull_up = val_1 ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) *disable = (val_1 | val_2) ? false : true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ((type) == IOCTRL_TYPE_CDRU) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned int i, offset, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* make sure drive strength is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (strength < 2 || strength > 16 || (strength % 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (chip->io_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) base = chip->io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) base = chip->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) shift = IPROC_GPIO_SHIFT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) strength = (strength / 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) val = readl(base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) val &= ~BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) val |= ((strength >> i) & 0x1) << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) writel(val, base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u16 *strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned int i, offset, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (chip->io_ctrl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) base = chip->io_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) base = chip->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) shift = IPROC_GPIO_SHIFT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) raw_spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) *strength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) val = readl(base + offset) & BIT(shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) val >>= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) *strength += (val << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* convert to mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) *strength = (*strength + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) raw_spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned gpio = iproc_pin_to_gpio(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u16 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) bool disable, pull_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (iproc_pinconf_param_is_disabled(chip, param))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (!disable && pull_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!disable && !pull_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = iproc_gpio_get_strength(chip, gpio, &arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned i, gpio = iproc_pin_to_gpio(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int ret = -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (iproc_pinconf_param_is_disabled(chip, param))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = iproc_gpio_set_pull(chip, gpio, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = iproc_gpio_set_pull(chip, gpio, false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = iproc_gpio_set_pull(chip, gpio, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = iproc_gpio_set_strength(chip, gpio, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_err(chip->dev, "invalid configuration\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const struct pinconf_ops iproc_pconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .pin_config_get = iproc_pin_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .pin_config_set = iproc_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * Iproc GPIO controller supports some PINCONF related configurations such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * pull up, pull down, and drive strength, when the pin is configured to GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * local GPIO pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct pinctrl_desc *pctldesc = &chip->pctldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct gpio_chip *gc = &chip->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) for (i = 0; i < gc->ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) pins[i].number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "gpio-%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (!pins[i].name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pctldesc->name = dev_name(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pctldesc->pctlops = &iproc_pctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pctldesc->pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) pctldesc->npins = gc->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) pctldesc->confops = &iproc_pconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (IS_ERR(chip->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dev_err(chip->dev, "unable to register pinctrl device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return PTR_ERR(chip->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static const struct of_device_id iproc_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) { .compatible = "brcm,iproc-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) { .compatible = "brcm,cygnus-ccm-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) { .compatible = "brcm,cygnus-asiu-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) { .compatible = "brcm,cygnus-crmu-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) { .compatible = "brcm,iproc-nsp-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) { .compatible = "brcm,iproc-stingray-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int iproc_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct iproc_gpio *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) u32 ngpios, pinconf_disable_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) bool no_pinconf = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* NSP does not support drive strength config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* Stingray does not support pinconf in this controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) else if (of_device_is_compatible(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "brcm,iproc-stingray-gpio"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) no_pinconf = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) chip->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) chip->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (IS_ERR(chip->base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev_err(dev, "unable to map I/O memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return PTR_ERR(chip->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) chip->io_ctrl = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (IS_ERR(chip->io_ctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_err(dev, "unable to map I/O memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return PTR_ERR(chip->io_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (of_device_is_compatible(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) "brcm,cygnus-ccm-gpio"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) io_ctrl_type = IOCTRL_TYPE_CDRU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) io_ctrl_type = IOCTRL_TYPE_AON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) chip->io_ctrl_type = io_ctrl_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dev_err(&pdev->dev, "missing ngpios DT property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) raw_spin_lock_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) gc = &chip->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) gc->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) gc->ngpio = ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) gc->label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) gc->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) gc->of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) gc->request = iproc_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) gc->free = iproc_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) gc->direction_input = iproc_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) gc->direction_output = iproc_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) gc->get_direction = iproc_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) gc->set = iproc_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) gc->get = iproc_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) "gpio-ranges");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* optional GPIO interrupt support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) irq = platform_get_irq_optional(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct irq_chip *irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) irqc = &chip->irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) irqc->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) irqc->irq_ack = iproc_gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) irqc->irq_mask = iproc_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) irqc->irq_unmask = iproc_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) irqc->irq_set_type = iproc_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) irqc->irq_enable = iproc_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) irqc->irq_disable = iproc_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) girq = &gc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) girq->chip = irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) girq->parent_handler = iproc_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) girq->parents = devm_kcalloc(dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) girq->parents[0] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ret = gpiochip_add_data(gc, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dev_err(dev, "unable to add GPIO chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (!no_pinconf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ret = iproc_gpio_register_pinconf(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_err(dev, "unable to register pinconf\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) goto err_rm_gpiochip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (pinconf_disable_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ret = iproc_pinconf_disable_map_create(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) pinconf_disable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "unable to create pinconf disable map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) goto err_rm_gpiochip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) err_rm_gpiochip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) gpiochip_remove(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static struct platform_driver iproc_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .name = "iproc-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .of_match_table = iproc_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .probe = iproc_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static int __init iproc_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return platform_driver_register(&iproc_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) arch_initcall_sync(iproc_gpio_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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