^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2014-2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Broadcom Cygnus IOMUX driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * This file contains the Cygnus IOMUX driver that supports group based PINMUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * configuration. Although PINMUX configuration is mainly group based, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Cygnus IOMUX controller allows certain pins to be individually muxed to GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * function, and therefore be controlled by the Cygnus ASIU GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CYGNUS_NUM_IOMUX_REGS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CYGNUS_NUM_MUX_PER_REG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CYGNUS_NUM_IOMUX (CYGNUS_NUM_IOMUX_REGS * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) CYGNUS_NUM_MUX_PER_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Cygnus IOMUX register description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @offset: register offset for mux configuration of a group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @shift: bit shift for mux configuration of a group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @alt: alternate function to set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct cygnus_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Keep track of Cygnus IOMUX configuration and prevent double configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @cygnus_mux: Cygnus IOMUX register description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @is_configured: flag to indicate whether a mux setting has already been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct cygnus_mux_log {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct cygnus_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bool is_configured;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Group based IOMUX configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @name: name of the group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @pins: array of pins used by this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @num_pins: total number of pins used by this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @mux: Cygnus group based IOMUX configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct cygnus_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct cygnus_mux mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Cygnus mux function and supported pin groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @name: name of the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @groups: array of groups that can be supported by this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @num_groups: total number of groups that can be supported by this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct cygnus_pin_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Cygnus IOMUX pinctrl core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @pctl: pointer to pinctrl_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @dev: pointer to device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @base0: first I/O register base of the Cygnus IOMUX controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @base1: second I/O register base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @groups: pointer to array of groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @num_groups: total number of groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @functions: pointer to array of functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @num_functions: total number of functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @mux_log: pointer to the array of mux logs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @lock: lock to protect register access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct cygnus_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void __iomem *base0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void __iomem *base1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const struct cygnus_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) const struct cygnus_pin_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct cygnus_mux_log *mux_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Certain pins can be individually muxed to GPIO function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @is_supported: flag to indicate GPIO mux is supported for this pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @offset: register offset for GPIO mux override of a pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @shift: bit shift for GPIO mux override of a pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct cygnus_gpio_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int is_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Description of a pin in Cygnus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @pin: pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @name: pin name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @gpio_mux: GPIO override related information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct cygnus_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct cygnus_gpio_mux gpio_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CYGNUS_PIN_DESC(p, n, i, o, s) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .pin = p, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .gpio_mux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .is_supported = i, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .shift = s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * List of pins in Cygnus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static struct cygnus_pin cygnus_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CYGNUS_PIN_DESC(0, "ext_device_reset_n", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) CYGNUS_PIN_DESC(1, "chip_mode0", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CYGNUS_PIN_DESC(2, "chip_mode1", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) CYGNUS_PIN_DESC(3, "chip_mode2", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) CYGNUS_PIN_DESC(4, "chip_mode3", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) CYGNUS_PIN_DESC(5, "chip_mode4", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CYGNUS_PIN_DESC(6, "bsc0_scl", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) CYGNUS_PIN_DESC(7, "bsc0_sda", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CYGNUS_PIN_DESC(8, "bsc1_scl", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CYGNUS_PIN_DESC(9, "bsc1_sda", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CYGNUS_PIN_DESC(10, "d1w_dq", 1, 0x28, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CYGNUS_PIN_DESC(11, "d1wowstz_l", 1, 0x4, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CYGNUS_PIN_DESC(12, "gpio0", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) CYGNUS_PIN_DESC(13, "gpio1", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CYGNUS_PIN_DESC(14, "gpio2", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) CYGNUS_PIN_DESC(15, "gpio3", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CYGNUS_PIN_DESC(16, "gpio4", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) CYGNUS_PIN_DESC(17, "gpio5", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CYGNUS_PIN_DESC(18, "gpio6", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) CYGNUS_PIN_DESC(19, "gpio7", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) CYGNUS_PIN_DESC(20, "gpio8", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CYGNUS_PIN_DESC(21, "gpio9", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) CYGNUS_PIN_DESC(22, "gpio10", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) CYGNUS_PIN_DESC(23, "gpio11", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) CYGNUS_PIN_DESC(24, "gpio12", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) CYGNUS_PIN_DESC(25, "gpio13", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CYGNUS_PIN_DESC(26, "gpio14", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) CYGNUS_PIN_DESC(27, "gpio15", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CYGNUS_PIN_DESC(28, "gpio16", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CYGNUS_PIN_DESC(29, "gpio17", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CYGNUS_PIN_DESC(30, "gpio18", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CYGNUS_PIN_DESC(31, "gpio19", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) CYGNUS_PIN_DESC(32, "gpio20", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CYGNUS_PIN_DESC(33, "gpio21", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CYGNUS_PIN_DESC(34, "gpio22", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CYGNUS_PIN_DESC(35, "gpio23", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) CYGNUS_PIN_DESC(36, "mdc", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CYGNUS_PIN_DESC(37, "mdio", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) CYGNUS_PIN_DESC(38, "pwm0", 1, 0x10, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) CYGNUS_PIN_DESC(39, "pwm1", 1, 0x10, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) CYGNUS_PIN_DESC(40, "pwm2", 1, 0x10, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) CYGNUS_PIN_DESC(41, "pwm3", 1, 0x10, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) CYGNUS_PIN_DESC(42, "sc0_clk", 1, 0x10, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) CYGNUS_PIN_DESC(43, "sc0_cmdvcc_l", 1, 0x10, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) CYGNUS_PIN_DESC(44, "sc0_detect", 1, 0x10, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) CYGNUS_PIN_DESC(45, "sc0_fcb", 1, 0x10, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) CYGNUS_PIN_DESC(46, "sc0_io", 1, 0x10, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) CYGNUS_PIN_DESC(47, "sc0_rst_l", 1, 0x10, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) CYGNUS_PIN_DESC(48, "sc1_clk", 1, 0x10, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) CYGNUS_PIN_DESC(49, "sc1_cmdvcc_l", 1, 0x10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CYGNUS_PIN_DESC(50, "sc1_detect", 1, 0x10, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) CYGNUS_PIN_DESC(51, "sc1_fcb", 1, 0x10, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) CYGNUS_PIN_DESC(52, "sc1_io", 1, 0x10, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) CYGNUS_PIN_DESC(53, "sc1_rst_l", 1, 0x10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) CYGNUS_PIN_DESC(54, "spi0_clk", 1, 0x18, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) CYGNUS_PIN_DESC(55, "spi0_mosi", 1, 0x18, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) CYGNUS_PIN_DESC(56, "spi0_miso", 1, 0x18, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) CYGNUS_PIN_DESC(57, "spi0_ss", 1, 0x18, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) CYGNUS_PIN_DESC(58, "spi1_clk", 1, 0x18, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CYGNUS_PIN_DESC(59, "spi1_mosi", 1, 0x1c, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CYGNUS_PIN_DESC(60, "spi1_miso", 1, 0x18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) CYGNUS_PIN_DESC(61, "spi1_ss", 1, 0x1c, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) CYGNUS_PIN_DESC(62, "spi2_clk", 1, 0x1c, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) CYGNUS_PIN_DESC(63, "spi2_mosi", 1, 0x1c, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CYGNUS_PIN_DESC(64, "spi2_miso", 1, 0x1c, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CYGNUS_PIN_DESC(65, "spi2_ss", 1, 0x1c, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CYGNUS_PIN_DESC(66, "spi3_clk", 1, 0x1c, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) CYGNUS_PIN_DESC(67, "spi3_mosi", 1, 0x1c, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CYGNUS_PIN_DESC(68, "spi3_miso", 1, 0x1c, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CYGNUS_PIN_DESC(69, "spi3_ss", 1, 0x1c, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CYGNUS_PIN_DESC(70, "uart0_cts", 1, 0x1c, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CYGNUS_PIN_DESC(71, "uart0_rts", 1, 0x1c, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CYGNUS_PIN_DESC(72, "uart0_rx", 1, 0x1c, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) CYGNUS_PIN_DESC(73, "uart0_tx", 1, 0x1c, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) CYGNUS_PIN_DESC(74, "uart1_cts", 1, 0x1c, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) CYGNUS_PIN_DESC(75, "uart1_dcd", 1, 0x1c, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CYGNUS_PIN_DESC(76, "uart1_dsr", 1, 0x20, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) CYGNUS_PIN_DESC(77, "uart1_dtr", 1, 0x20, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) CYGNUS_PIN_DESC(78, "uart1_ri", 1, 0x20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) CYGNUS_PIN_DESC(79, "uart1_rts", 1, 0x20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) CYGNUS_PIN_DESC(80, "uart1_rx", 1, 0x20, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) CYGNUS_PIN_DESC(81, "uart1_tx", 1, 0x20, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) CYGNUS_PIN_DESC(82, "uart3_rx", 1, 0x20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) CYGNUS_PIN_DESC(83, "uart3_tx", 1, 0x20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) CYGNUS_PIN_DESC(84, "sdio1_clk_sdcard", 1, 0x14, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) CYGNUS_PIN_DESC(85, "sdio1_cmd", 1, 0x14, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) CYGNUS_PIN_DESC(86, "sdio1_data0", 1, 0x14, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) CYGNUS_PIN_DESC(87, "sdio1_data1", 1, 0x14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) CYGNUS_PIN_DESC(88, "sdio1_data2", 1, 0x18, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) CYGNUS_PIN_DESC(89, "sdio1_data3", 1, 0x18, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) CYGNUS_PIN_DESC(90, "sdio1_wp_n", 1, 0x18, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) CYGNUS_PIN_DESC(91, "sdio1_card_rst", 1, 0x14, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CYGNUS_PIN_DESC(92, "sdio1_led_on", 1, 0x18, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) CYGNUS_PIN_DESC(93, "sdio1_cd", 1, 0x14, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) CYGNUS_PIN_DESC(94, "sdio0_clk_sdcard", 1, 0x14, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) CYGNUS_PIN_DESC(95, "sdio0_cmd", 1, 0x14, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) CYGNUS_PIN_DESC(96, "sdio0_data0", 1, 0x14, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) CYGNUS_PIN_DESC(97, "sdio0_data1", 1, 0x14, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) CYGNUS_PIN_DESC(98, "sdio0_data2", 1, 0x14, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) CYGNUS_PIN_DESC(99, "sdio0_data3", 1, 0x14, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) CYGNUS_PIN_DESC(100, "sdio0_wp_n", 1, 0x14, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) CYGNUS_PIN_DESC(101, "sdio0_card_rst", 1, 0x14, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) CYGNUS_PIN_DESC(102, "sdio0_led_on", 1, 0x14, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) CYGNUS_PIN_DESC(103, "sdio0_cd", 1, 0x14, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) CYGNUS_PIN_DESC(104, "sflash_clk", 1, 0x18, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) CYGNUS_PIN_DESC(105, "sflash_cs_l", 1, 0x18, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) CYGNUS_PIN_DESC(106, "sflash_mosi", 1, 0x18, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) CYGNUS_PIN_DESC(107, "sflash_miso", 1, 0x18, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) CYGNUS_PIN_DESC(108, "sflash_wp_n", 1, 0x18, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) CYGNUS_PIN_DESC(109, "sflash_hold_n", 1, 0x18, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) CYGNUS_PIN_DESC(110, "nand_ale", 1, 0xc, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) CYGNUS_PIN_DESC(111, "nand_ce0_l", 1, 0xc, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) CYGNUS_PIN_DESC(112, "nand_ce1_l", 1, 0xc, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) CYGNUS_PIN_DESC(113, "nand_cle", 1, 0xc, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) CYGNUS_PIN_DESC(114, "nand_dq0", 1, 0xc, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) CYGNUS_PIN_DESC(115, "nand_dq1", 1, 0xc, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) CYGNUS_PIN_DESC(116, "nand_dq2", 1, 0xc, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) CYGNUS_PIN_DESC(117, "nand_dq3", 1, 0xc, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) CYGNUS_PIN_DESC(118, "nand_dq4", 1, 0xc, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) CYGNUS_PIN_DESC(119, "nand_dq5", 1, 0xc, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) CYGNUS_PIN_DESC(120, "nand_dq6", 1, 0xc, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) CYGNUS_PIN_DESC(121, "nand_dq7", 1, 0xc, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) CYGNUS_PIN_DESC(122, "nand_rb_l", 1, 0xc, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) CYGNUS_PIN_DESC(123, "nand_re_l", 1, 0xc, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) CYGNUS_PIN_DESC(124, "nand_we_l", 1, 0xc, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) CYGNUS_PIN_DESC(125, "nand_wp_l", 1, 0xc, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) CYGNUS_PIN_DESC(126, "lcd_clac", 1, 0x4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) CYGNUS_PIN_DESC(127, "lcd_clcp", 1, 0x4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) CYGNUS_PIN_DESC(128, "lcd_cld0", 1, 0x4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) CYGNUS_PIN_DESC(129, "lcd_cld1", 1, 0x4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) CYGNUS_PIN_DESC(130, "lcd_cld10", 1, 0x4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) CYGNUS_PIN_DESC(131, "lcd_cld11", 1, 0x4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) CYGNUS_PIN_DESC(132, "lcd_cld12", 1, 0x4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) CYGNUS_PIN_DESC(133, "lcd_cld13", 1, 0x4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) CYGNUS_PIN_DESC(134, "lcd_cld14", 1, 0x4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) CYGNUS_PIN_DESC(135, "lcd_cld15", 1, 0x4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) CYGNUS_PIN_DESC(136, "lcd_cld16", 1, 0x4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CYGNUS_PIN_DESC(137, "lcd_cld17", 1, 0x4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) CYGNUS_PIN_DESC(138, "lcd_cld18", 1, 0x4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) CYGNUS_PIN_DESC(139, "lcd_cld19", 1, 0x4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) CYGNUS_PIN_DESC(140, "lcd_cld2", 1, 0x8, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) CYGNUS_PIN_DESC(141, "lcd_cld20", 1, 0x8, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CYGNUS_PIN_DESC(142, "lcd_cld21", 1, 0x8, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) CYGNUS_PIN_DESC(143, "lcd_cld22", 1, 0x8, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) CYGNUS_PIN_DESC(144, "lcd_cld23", 1, 0x8, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) CYGNUS_PIN_DESC(145, "lcd_cld3", 1, 0x8, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) CYGNUS_PIN_DESC(146, "lcd_cld4", 1, 0x8, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) CYGNUS_PIN_DESC(147, "lcd_cld5", 1, 0x8, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) CYGNUS_PIN_DESC(148, "lcd_cld6", 1, 0x8, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) CYGNUS_PIN_DESC(149, "lcd_cld7", 1, 0x8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) CYGNUS_PIN_DESC(150, "lcd_cld8", 1, 0x8, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) CYGNUS_PIN_DESC(151, "lcd_cld9", 1, 0x8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) CYGNUS_PIN_DESC(152, "lcd_clfp", 1, 0x8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) CYGNUS_PIN_DESC(153, "lcd_clle", 1, 0x8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) CYGNUS_PIN_DESC(154, "lcd_cllp", 1, 0x8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) CYGNUS_PIN_DESC(155, "lcd_clpower", 1, 0x8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) CYGNUS_PIN_DESC(156, "camera_vsync", 1, 0x4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) CYGNUS_PIN_DESC(157, "camera_trigger", 1, 0x0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) CYGNUS_PIN_DESC(158, "camera_strobe", 1, 0x0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) CYGNUS_PIN_DESC(159, "camera_standby", 1, 0x0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) CYGNUS_PIN_DESC(160, "camera_reset_n", 1, 0x0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) CYGNUS_PIN_DESC(161, "camera_pixdata9", 1, 0x0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) CYGNUS_PIN_DESC(162, "camera_pixdata8", 1, 0x0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) CYGNUS_PIN_DESC(163, "camera_pixdata7", 1, 0x0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) CYGNUS_PIN_DESC(164, "camera_pixdata6", 1, 0x0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) CYGNUS_PIN_DESC(165, "camera_pixdata5", 1, 0x0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) CYGNUS_PIN_DESC(166, "camera_pixdata4", 1, 0x0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) CYGNUS_PIN_DESC(167, "camera_pixdata3", 1, 0x0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) CYGNUS_PIN_DESC(168, "camera_pixdata2", 1, 0x0, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) CYGNUS_PIN_DESC(169, "camera_pixdata1", 1, 0x0, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) CYGNUS_PIN_DESC(170, "camera_pixdata0", 1, 0x0, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) CYGNUS_PIN_DESC(171, "camera_pixclk", 1, 0x0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) CYGNUS_PIN_DESC(172, "camera_hsync", 1, 0x0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) CYGNUS_PIN_DESC(173, "camera_pll_ref_clk", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) CYGNUS_PIN_DESC(174, "usb_id_indication", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) CYGNUS_PIN_DESC(175, "usb_vbus_indication", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) CYGNUS_PIN_DESC(176, "gpio0_3p3", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CYGNUS_PIN_DESC(177, "gpio1_3p3", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) CYGNUS_PIN_DESC(178, "gpio2_3p3", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) CYGNUS_PIN_DESC(179, "gpio3_3p3", 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * List of groups of pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const unsigned bsc1_pins[] = { 8, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const unsigned pcie_clkreq_pins[] = { 8, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const unsigned i2s2_0_pins[] = { 12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const unsigned i2s2_1_pins[] = { 13 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const unsigned i2s2_2_pins[] = { 14 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const unsigned i2s2_3_pins[] = { 15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const unsigned i2s2_4_pins[] = { 16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const unsigned pwm4_pins[] = { 17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const unsigned pwm5_pins[] = { 18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const unsigned key0_pins[] = { 20 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const unsigned key1_pins[] = { 21 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const unsigned key2_pins[] = { 22 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const unsigned key3_pins[] = { 23 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const unsigned key4_pins[] = { 24 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const unsigned key5_pins[] = { 25 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const unsigned key6_pins[] = { 26 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const unsigned audio_dte0_pins[] = { 26 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const unsigned key7_pins[] = { 27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const unsigned audio_dte1_pins[] = { 27 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const unsigned key8_pins[] = { 28 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const unsigned key9_pins[] = { 29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const unsigned key10_pins[] = { 30 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const unsigned key11_pins[] = { 31 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const unsigned key12_pins[] = { 32 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const unsigned key13_pins[] = { 33 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const unsigned key14_pins[] = { 34 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const unsigned audio_dte2_pins[] = { 34 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const unsigned key15_pins[] = { 35 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const unsigned audio_dte3_pins[] = { 35 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const unsigned pwm0_pins[] = { 38 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const unsigned pwm1_pins[] = { 39 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const unsigned pwm2_pins[] = { 40 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const unsigned pwm3_pins[] = { 41 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const unsigned sdio0_pins[] = { 94, 95, 96, 97, 98, 99 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const unsigned smart_card0_pins[] = { 42, 43, 44, 46, 47 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const unsigned i2s0_0_pins[] = { 42, 43, 44, 46 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const unsigned spdif_pins[] = { 47 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const unsigned smart_card1_pins[] = { 48, 49, 50, 52, 53 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const unsigned i2s1_0_pins[] = { 48, 49, 50, 52 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const unsigned spi0_pins[] = { 54, 55, 56, 57 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const unsigned spi1_pins[] = { 58, 59, 60, 61 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const unsigned spi2_pins[] = { 62, 63, 64, 65 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const unsigned spi3_pins[] = { 66, 67, 68, 69 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const unsigned sw_led0_0_pins[] = { 66, 67, 68, 69 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const unsigned d1w_pins[] = { 10, 11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const unsigned uart4_pins[] = { 10, 11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static const unsigned sw_led2_0_pins[] = { 10, 11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const unsigned lcd_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 148, 149, 150, 151, 152, 153, 154, 155 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const unsigned sram_0_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 148, 149, 150, 151, 152, 153, 154, 155 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static const unsigned spi5_pins[] = { 141, 142, 143, 144 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const unsigned uart0_pins[] = { 70, 71, 72, 73 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const unsigned sw_led0_1_pins[] = { 70, 71, 72, 73 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const unsigned uart1_dte_pins[] = { 75, 76, 77, 78 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const unsigned uart2_pins[] = { 75, 76, 77, 78 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const unsigned uart1_pins[] = { 74, 79, 80, 81 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const unsigned uart3_pins[] = { 82, 83 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const unsigned qspi_0_pins[] = { 104, 105, 106, 107 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const unsigned nand_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 118, 119, 120, 121, 122, 123, 124, 125 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const unsigned sdio0_cd_pins[] = { 103 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const unsigned sdio0_mmc_pins[] = { 100, 101, 102 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const unsigned sdio1_data_0_pins[] = { 86, 87 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const unsigned can0_pins[] = { 86, 87 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const unsigned spi4_0_pins[] = { 86, 87 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const unsigned sdio1_data_1_pins[] = { 88, 89 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const unsigned can1_pins[] = { 88, 89 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const unsigned spi4_1_pins[] = { 88, 89 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const unsigned sdio1_cd_pins[] = { 93 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const unsigned sdio1_led_pins[] = { 84, 85 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static const unsigned sw_led2_1_pins[] = { 84, 85 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const unsigned sdio1_mmc_pins[] = { 90, 91, 92 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const unsigned cam_led_pins[] = { 156, 157, 158, 159, 160 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const unsigned sw_led1_pins[] = { 156, 157, 158, 159 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const unsigned cam_0_pins[] = { 169, 170, 171, 169, 170 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const unsigned cam_1_pins[] = { 161, 162, 163, 164, 165, 166, 167,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 168 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const unsigned sram_1_pins[] = { 161, 162, 163, 164, 165, 166, 167,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 168 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const unsigned qspi_1_pins[] = { 108, 109 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const unsigned smart_card0_fcb_pins[] = { 45 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const unsigned i2s0_1_pins[] = { 45 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static const unsigned smart_card1_fcb_pins[] = { 51 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const unsigned i2s1_1_pins[] = { 51 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const unsigned gpio0_3p3_pins[] = { 176 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const unsigned usb0_oc_pins[] = { 176 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const unsigned gpio1_3p3_pins[] = { 177 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static const unsigned usb1_oc_pins[] = { 177 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static const unsigned gpio2_3p3_pins[] = { 178 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const unsigned usb2_oc_pins[] = { 178 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define CYGNUS_PIN_GROUP(group_name, off, sh, al) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .name = __stringify(group_name) "_grp", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .pins = group_name ## _pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .num_pins = ARRAY_SIZE(group_name ## _pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .mux = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .offset = off, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .shift = sh, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .alt = al, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * List of Cygnus pin groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static const struct cygnus_pin_group cygnus_pin_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) CYGNUS_PIN_GROUP(i2s2_0, 0x0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) CYGNUS_PIN_GROUP(i2s2_1, 0x0, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) CYGNUS_PIN_GROUP(i2s2_2, 0x0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) CYGNUS_PIN_GROUP(i2s2_3, 0x0, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) CYGNUS_PIN_GROUP(i2s2_4, 0x0, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) CYGNUS_PIN_GROUP(pwm4, 0x0, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) CYGNUS_PIN_GROUP(pwm5, 0x0, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) CYGNUS_PIN_GROUP(key0, 0x4, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) CYGNUS_PIN_GROUP(key1, 0x4, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) CYGNUS_PIN_GROUP(key2, 0x4, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) CYGNUS_PIN_GROUP(key3, 0x4, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) CYGNUS_PIN_GROUP(key4, 0x4, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) CYGNUS_PIN_GROUP(key5, 0x4, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) CYGNUS_PIN_GROUP(key6, 0x4, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) CYGNUS_PIN_GROUP(audio_dte0, 0x4, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) CYGNUS_PIN_GROUP(key7, 0x4, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) CYGNUS_PIN_GROUP(audio_dte1, 0x4, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) CYGNUS_PIN_GROUP(key8, 0x8, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) CYGNUS_PIN_GROUP(key9, 0x8, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) CYGNUS_PIN_GROUP(key10, 0x8, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) CYGNUS_PIN_GROUP(key11, 0x8, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) CYGNUS_PIN_GROUP(key12, 0x8, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) CYGNUS_PIN_GROUP(key13, 0x8, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) CYGNUS_PIN_GROUP(key14, 0x8, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) CYGNUS_PIN_GROUP(audio_dte2, 0x8, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) CYGNUS_PIN_GROUP(key15, 0x8, 28, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) CYGNUS_PIN_GROUP(audio_dte3, 0x8, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) CYGNUS_PIN_GROUP(pwm0, 0xc, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) CYGNUS_PIN_GROUP(pwm1, 0xc, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) CYGNUS_PIN_GROUP(pwm2, 0xc, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) CYGNUS_PIN_GROUP(pwm3, 0xc, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) CYGNUS_PIN_GROUP(sdio0, 0xc, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) CYGNUS_PIN_GROUP(smart_card0, 0xc, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) CYGNUS_PIN_GROUP(i2s0_0, 0xc, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) CYGNUS_PIN_GROUP(spdif, 0xc, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) CYGNUS_PIN_GROUP(smart_card1, 0xc, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) CYGNUS_PIN_GROUP(i2s1_0, 0xc, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) CYGNUS_PIN_GROUP(spi0, 0x10, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) CYGNUS_PIN_GROUP(spi1, 0x10, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) CYGNUS_PIN_GROUP(spi2, 0x10, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) CYGNUS_PIN_GROUP(spi3, 0x10, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) CYGNUS_PIN_GROUP(sw_led0_0, 0x10, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) CYGNUS_PIN_GROUP(d1w, 0x10, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) CYGNUS_PIN_GROUP(uart4, 0x10, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) CYGNUS_PIN_GROUP(sw_led2_0, 0x10, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) CYGNUS_PIN_GROUP(lcd, 0x10, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) CYGNUS_PIN_GROUP(sram_0, 0x10, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) CYGNUS_PIN_GROUP(spi5, 0x10, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) CYGNUS_PIN_GROUP(uart0, 0x14, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) CYGNUS_PIN_GROUP(sw_led0_1, 0x14, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) CYGNUS_PIN_GROUP(uart1_dte, 0x14, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) CYGNUS_PIN_GROUP(uart2, 0x14, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) CYGNUS_PIN_GROUP(uart1, 0x14, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) CYGNUS_PIN_GROUP(uart3, 0x14, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) CYGNUS_PIN_GROUP(qspi_0, 0x14, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) CYGNUS_PIN_GROUP(nand, 0x14, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) CYGNUS_PIN_GROUP(sdio0_cd, 0x18, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) CYGNUS_PIN_GROUP(sdio0_mmc, 0x18, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) CYGNUS_PIN_GROUP(sdio1_data_0, 0x18, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) CYGNUS_PIN_GROUP(can0, 0x18, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) CYGNUS_PIN_GROUP(spi4_0, 0x18, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) CYGNUS_PIN_GROUP(sdio1_data_1, 0x18, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) CYGNUS_PIN_GROUP(can1, 0x18, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) CYGNUS_PIN_GROUP(spi4_1, 0x18, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) CYGNUS_PIN_GROUP(sdio1_cd, 0x18, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) CYGNUS_PIN_GROUP(sdio1_led, 0x18, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) CYGNUS_PIN_GROUP(sw_led2_1, 0x18, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) CYGNUS_PIN_GROUP(sdio1_mmc, 0x18, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) CYGNUS_PIN_GROUP(cam_led, 0x1c, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) CYGNUS_PIN_GROUP(sw_led1, 0x1c, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) CYGNUS_PIN_GROUP(cam_0, 0x1c, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) CYGNUS_PIN_GROUP(cam_1, 0x1c, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) CYGNUS_PIN_GROUP(sram_1, 0x1c, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) CYGNUS_PIN_GROUP(qspi_1, 0x1c, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) CYGNUS_PIN_GROUP(bsc1, 0x1c, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) CYGNUS_PIN_GROUP(pcie_clkreq, 0x1c, 16, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) CYGNUS_PIN_GROUP(smart_card0_fcb, 0x20, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) CYGNUS_PIN_GROUP(i2s0_1, 0x20, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) CYGNUS_PIN_GROUP(smart_card1_fcb, 0x20, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) CYGNUS_PIN_GROUP(i2s1_1, 0x20, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) CYGNUS_PIN_GROUP(gpio0_3p3, 0x28, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) CYGNUS_PIN_GROUP(usb0_oc, 0x28, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) CYGNUS_PIN_GROUP(gpio1_3p3, 0x28, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) CYGNUS_PIN_GROUP(usb1_oc, 0x28, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) CYGNUS_PIN_GROUP(gpio2_3p3, 0x28, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) CYGNUS_PIN_GROUP(usb2_oc, 0x28, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * List of groups supported by functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const char * const i2s0_grps[] = { "i2s0_0_grp", "i2s0_1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static const char * const i2s1_grps[] = { "i2s1_0_grp", "i2s1_1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const char * const i2s2_grps[] = { "i2s2_0_grp", "i2s2_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) "i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const char * const spdif_grps[] = { "spdif_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const char * const pwm0_grps[] = { "pwm0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const char * const pwm1_grps[] = { "pwm1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const char * const pwm2_grps[] = { "pwm2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const char * const pwm3_grps[] = { "pwm3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const char * const pwm4_grps[] = { "pwm4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const char * const pwm5_grps[] = { "pwm5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const char * const key_grps[] = { "key0_grp", "key1_grp", "key2_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) "key3_grp", "key4_grp", "key5_grp", "key6_grp", "key7_grp", "key8_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) "key9_grp", "key10_grp", "key11_grp", "key12_grp", "key13_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) "key14_grp", "key15_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const char * const audio_dte_grps[] = { "audio_dte0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const char * const smart_card0_grps[] = { "smart_card0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) "smart_card0_fcb_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const char * const smart_card1_grps[] = { "smart_card1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) "smart_card1_fcb_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const char * const spi0_grps[] = { "spi0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static const char * const spi1_grps[] = { "spi1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static const char * const spi2_grps[] = { "spi2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static const char * const spi3_grps[] = { "spi3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const char * const spi4_grps[] = { "spi4_0_grp", "spi4_1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const char * const spi5_grps[] = { "spi5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const char * const sw_led0_grps[] = { "sw_led0_0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) "sw_led0_1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const char * const sw_led1_grps[] = { "sw_led1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const char * const sw_led2_grps[] = { "sw_led2_0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "sw_led2_1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const char * const d1w_grps[] = { "d1w_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static const char * const lcd_grps[] = { "lcd_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const char * const sram_grps[] = { "sram_0_grp", "sram_1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const char * const uart0_grps[] = { "uart0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const char * const uart1_grps[] = { "uart1_grp", "uart1_dte_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const char * const uart2_grps[] = { "uart2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const char * const uart3_grps[] = { "uart3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const char * const uart4_grps[] = { "uart4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const char * const qspi_grps[] = { "qspi_0_grp", "qspi_1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const char * const nand_grps[] = { "nand_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static const char * const sdio0_grps[] = { "sdio0_grp", "sdio0_cd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "sdio0_mmc_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const char * const sdio1_grps[] = { "sdio1_data_0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) "sdio1_data_1_grp", "sdio1_cd_grp", "sdio1_led_grp", "sdio1_mmc_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const char * const can0_grps[] = { "can0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const char * const can1_grps[] = { "can1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const char * const cam_grps[] = { "cam_led_grp", "cam_0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) "cam_1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const char * const bsc1_grps[] = { "bsc1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const char * const pcie_clkreq_grps[] = { "pcie_clkreq_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const char * const usb0_oc_grps[] = { "usb0_oc_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const char * const usb1_oc_grps[] = { "usb1_oc_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const char * const usb2_oc_grps[] = { "usb2_oc_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define CYGNUS_PIN_FUNCTION(func) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .name = #func, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .groups = func ## _grps, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .num_groups = ARRAY_SIZE(func ## _grps), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * List of supported functions in Cygnus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static const struct cygnus_pin_function cygnus_pin_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) CYGNUS_PIN_FUNCTION(i2s0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) CYGNUS_PIN_FUNCTION(i2s1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) CYGNUS_PIN_FUNCTION(i2s2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) CYGNUS_PIN_FUNCTION(spdif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) CYGNUS_PIN_FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) CYGNUS_PIN_FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) CYGNUS_PIN_FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) CYGNUS_PIN_FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) CYGNUS_PIN_FUNCTION(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) CYGNUS_PIN_FUNCTION(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) CYGNUS_PIN_FUNCTION(key),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) CYGNUS_PIN_FUNCTION(audio_dte),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) CYGNUS_PIN_FUNCTION(smart_card0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) CYGNUS_PIN_FUNCTION(smart_card1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) CYGNUS_PIN_FUNCTION(spi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) CYGNUS_PIN_FUNCTION(spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) CYGNUS_PIN_FUNCTION(spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) CYGNUS_PIN_FUNCTION(spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) CYGNUS_PIN_FUNCTION(spi4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) CYGNUS_PIN_FUNCTION(spi5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) CYGNUS_PIN_FUNCTION(sw_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) CYGNUS_PIN_FUNCTION(sw_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) CYGNUS_PIN_FUNCTION(sw_led2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) CYGNUS_PIN_FUNCTION(d1w),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) CYGNUS_PIN_FUNCTION(lcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) CYGNUS_PIN_FUNCTION(sram),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) CYGNUS_PIN_FUNCTION(uart0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) CYGNUS_PIN_FUNCTION(uart1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) CYGNUS_PIN_FUNCTION(uart2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) CYGNUS_PIN_FUNCTION(uart3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) CYGNUS_PIN_FUNCTION(uart4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) CYGNUS_PIN_FUNCTION(qspi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) CYGNUS_PIN_FUNCTION(nand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) CYGNUS_PIN_FUNCTION(sdio0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) CYGNUS_PIN_FUNCTION(sdio1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) CYGNUS_PIN_FUNCTION(can0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) CYGNUS_PIN_FUNCTION(can1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) CYGNUS_PIN_FUNCTION(cam),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) CYGNUS_PIN_FUNCTION(bsc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) CYGNUS_PIN_FUNCTION(pcie_clkreq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) CYGNUS_PIN_FUNCTION(usb0_oc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) CYGNUS_PIN_FUNCTION(usb1_oc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) CYGNUS_PIN_FUNCTION(usb2_oc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int cygnus_get_groups_count(struct pinctrl_dev *pctrl_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return pinctrl->num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const char *cygnus_get_group_name(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return pinctrl->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int cygnus_get_group_pins(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) unsigned selector, const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) *pins = pinctrl->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) *num_pins = pinctrl->groups[selector].num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static void cygnus_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct seq_file *s, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) seq_printf(s, " %s", dev_name(pctrl_dev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const struct pinctrl_ops cygnus_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .get_groups_count = cygnus_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .get_group_name = cygnus_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .get_group_pins = cygnus_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .pin_dbg_show = cygnus_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int cygnus_get_functions_count(struct pinctrl_dev *pctrl_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return pinctrl->num_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const char *cygnus_get_function_name(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return pinctrl->functions[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int cygnus_get_function_groups(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) *groups = pinctrl->functions[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) *num_groups = pinctrl->functions[selector].num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static int cygnus_pinmux_set(struct cygnus_pinctrl *pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) const struct cygnus_pin_function *func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) const struct cygnus_pin_group *grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct cygnus_mux_log *mux_log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) const struct cygnus_mux *mux = &grp->mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u32 val, mask = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) for (i = 0; i < CYGNUS_NUM_IOMUX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (mux->offset != mux_log[i].mux.offset ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mux->shift != mux_log[i].mux.shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* match found if we reach here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* if this is a new configuration, just do it! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (!mux_log[i].is_configured)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * IOMUX has been configured previously and one is trying to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * configure it to a different function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (mux_log[i].mux.alt != mux->alt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) dev_err(pinctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "double configuration error detected!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) dev_err(pinctrl->dev, "func:%s grp:%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) func->name, grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * One tries to configure it to the same function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * Just quit and don't bother
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) mux_log[i].mux.alt = mux->alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) mux_log[i].is_configured = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) spin_lock_irqsave(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) val = readl(pinctrl->base0 + grp->mux.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) val &= ~(mask << grp->mux.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) val |= grp->mux.alt << grp->mux.shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) writel(val, pinctrl->base0 + grp->mux.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) spin_unlock_irqrestore(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int cygnus_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) unsigned func_select, unsigned grp_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) const struct cygnus_pin_function *func =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) &pinctrl->functions[func_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) const struct cygnus_pin_group *grp = &pinctrl->groups[grp_select];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) func_select, func->name, grp_select, grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) grp->mux.offset, grp->mux.shift, grp->mux.alt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return cygnus_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static int cygnus_gpio_request_enable(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) const struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* not all pins support GPIO pinmux override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (!mux->is_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) spin_lock_irqsave(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) val = readl(pinctrl->base1 + mux->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) val |= 0x3 << mux->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) writel(val, pinctrl->base1 + mux->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) spin_unlock_irqrestore(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_dbg(pctrl_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) "gpio request enable pin=%u offset=0x%x shift=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) pin, mux->offset, mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static void cygnus_gpio_disable_free(struct pinctrl_dev *pctrl_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (!mux->is_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) spin_lock_irqsave(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) val = readl(pinctrl->base1 + mux->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) val &= ~(0x3 << mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) writel(val, pinctrl->base1 + mux->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) spin_unlock_irqrestore(&pinctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dev_err(pctrl_dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) "gpio disable free pin=%u offset=0x%x shift=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) pin, mux->offset, mux->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static const struct pinmux_ops cygnus_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .get_functions_count = cygnus_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .get_function_name = cygnus_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .get_function_groups = cygnus_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .set_mux = cygnus_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .gpio_request_enable = cygnus_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .gpio_disable_free = cygnus_gpio_disable_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static struct pinctrl_desc cygnus_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .name = "cygnus-pinmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .pctlops = &cygnus_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .pmxops = &cygnus_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct cygnus_mux_log *log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) pinctrl->mux_log = devm_kcalloc(pinctrl->dev, CYGNUS_NUM_IOMUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) sizeof(struct cygnus_mux_log),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (!pinctrl->mux_log)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) for (i = 0; i < CYGNUS_NUM_IOMUX_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) for (j = 0; j < CYGNUS_NUM_MUX_PER_REG; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) log = &pinctrl->mux_log[i * CYGNUS_NUM_MUX_PER_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) + j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) log->mux.offset = i * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) log->mux.shift = j * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) log->mux.alt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) log->is_configured = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int cygnus_pinmux_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct cygnus_pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) unsigned num_pins = ARRAY_SIZE(cygnus_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (!pinctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) pinctrl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) platform_set_drvdata(pdev, pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) spin_lock_init(&pinctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (IS_ERR(pinctrl->base0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev_err(&pdev->dev, "unable to map I/O space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return PTR_ERR(pinctrl->base0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) pinctrl->base1 = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (IS_ERR(pinctrl->base1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dev_err(&pdev->dev, "unable to map I/O space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return PTR_ERR(pinctrl->base1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ret = cygnus_mux_log_init(pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) for (i = 0; i < num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) pins[i].number = cygnus_pins[i].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) pins[i].name = cygnus_pins[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) pins[i].drv_data = &cygnus_pins[i].gpio_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) pinctrl->groups = cygnus_pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) pinctrl->num_groups = ARRAY_SIZE(cygnus_pin_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) pinctrl->functions = cygnus_pin_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) pinctrl->num_functions = ARRAY_SIZE(cygnus_pin_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) cygnus_pinctrl_desc.pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) cygnus_pinctrl_desc.npins = num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) pinctrl->pctl = devm_pinctrl_register(&pdev->dev, &cygnus_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (IS_ERR(pinctrl->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) dev_err(&pdev->dev, "unable to register Cygnus IOMUX pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return PTR_ERR(pinctrl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static const struct of_device_id cygnus_pinmux_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) { .compatible = "brcm,cygnus-pinmux" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static struct platform_driver cygnus_pinmux_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .name = "cygnus-pinmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .of_match_table = cygnus_pinmux_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .probe = cygnus_pinmux_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static int __init cygnus_pinmux_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return platform_driver_register(&cygnus_pinmux_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) arch_initcall(cygnus_pinmux_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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