^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This driver is inspired by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * pinctrl-nomadik.c, please see original file for copyright information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * pinctrl-tegra.c, please see original file for copyright information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irqdesc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <dt-bindings/pinctrl/bcm2835.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MODULE_NAME "pinctrl-bcm2835"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BCM2835_NUM_GPIOS 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BCM2711_NUM_GPIOS 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BCM2835_NUM_BANKS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BCM2835_NUM_IRQS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* GPIO register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPFSEL0 0x0 /* Function Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPSET0 0x1c /* Pin Output Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPCLR0 0x28 /* Pin Output Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GPLEV0 0x34 /* Pin Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GPEDS0 0x40 /* Pin Event Detect Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPHEN0 0x64 /* Pin High Detect Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GPLEN0 0x70 /* Pin Low Detect Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GPPUD 0x94 /* Pin Pull-up/down Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FSEL_SHIFT(p) (((p) % 10) * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPIO_REG_OFFSET(p) ((p) / 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPIO_REG_SHIFT(p) ((p) % 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PUD_2711_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PUD_2711_REG_OFFSET(p) ((p) / 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* argument: bcm2835_pinconf_pull */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BCM2711_PULL_NONE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BCM2711_PULL_UP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BCM2711_PULL_DOWN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct bcm2835_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int *wake_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* note: locking assumes each bank will have its own unsigned long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int irq_type[BCM2711_NUM_GPIOS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct pinctrl_dev *pctl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct pinctrl_desc pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct pinctrl_gpio_range gpio_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* pins are just named GPIO0..GPIO53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) BCM2835_GPIO_PIN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) BCM2835_GPIO_PIN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) BCM2835_GPIO_PIN(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) BCM2835_GPIO_PIN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) BCM2835_GPIO_PIN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) BCM2835_GPIO_PIN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) BCM2835_GPIO_PIN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) BCM2835_GPIO_PIN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) BCM2835_GPIO_PIN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) BCM2835_GPIO_PIN(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) BCM2835_GPIO_PIN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) BCM2835_GPIO_PIN(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) BCM2835_GPIO_PIN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) BCM2835_GPIO_PIN(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) BCM2835_GPIO_PIN(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) BCM2835_GPIO_PIN(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) BCM2835_GPIO_PIN(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) BCM2835_GPIO_PIN(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) BCM2835_GPIO_PIN(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) BCM2835_GPIO_PIN(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) BCM2835_GPIO_PIN(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) BCM2835_GPIO_PIN(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) BCM2835_GPIO_PIN(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) BCM2835_GPIO_PIN(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) BCM2835_GPIO_PIN(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) BCM2835_GPIO_PIN(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) BCM2835_GPIO_PIN(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) BCM2835_GPIO_PIN(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) BCM2835_GPIO_PIN(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) BCM2835_GPIO_PIN(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) BCM2835_GPIO_PIN(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) BCM2835_GPIO_PIN(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) BCM2835_GPIO_PIN(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) BCM2835_GPIO_PIN(33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) BCM2835_GPIO_PIN(34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) BCM2835_GPIO_PIN(35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) BCM2835_GPIO_PIN(36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) BCM2835_GPIO_PIN(37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) BCM2835_GPIO_PIN(38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) BCM2835_GPIO_PIN(39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) BCM2835_GPIO_PIN(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) BCM2835_GPIO_PIN(41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) BCM2835_GPIO_PIN(42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) BCM2835_GPIO_PIN(43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) BCM2835_GPIO_PIN(44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) BCM2835_GPIO_PIN(45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) BCM2835_GPIO_PIN(46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) BCM2835_GPIO_PIN(47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) BCM2835_GPIO_PIN(48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) BCM2835_GPIO_PIN(49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) BCM2835_GPIO_PIN(50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) BCM2835_GPIO_PIN(51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) BCM2835_GPIO_PIN(52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) BCM2835_GPIO_PIN(53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) BCM2835_GPIO_PIN(54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) BCM2835_GPIO_PIN(55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) BCM2835_GPIO_PIN(56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) BCM2835_GPIO_PIN(57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* one pin per group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const char * const bcm2835_gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "gpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "gpio16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "gpio17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "gpio18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "gpio20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "gpio22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "gpio24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "gpio25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "gpio29",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "gpio30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "gpio32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "gpio33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "gpio34",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "gpio37",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "gpio38",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "gpio39",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "gpio40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "gpio41",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "gpio43",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "gpio44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "gpio45",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "gpio46",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "gpio47",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "gpio48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "gpio49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "gpio50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "gpio51",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "gpio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "gpio53",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "gpio54",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "gpio55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "gpio57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) enum bcm2835_fsel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) BCM2835_FSEL_COUNT = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) BCM2835_FSEL_MASK = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) [BCM2835_FSEL_GPIO_IN] = "gpio_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) [BCM2835_FSEL_ALT0] = "alt0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [BCM2835_FSEL_ALT1] = "alt1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [BCM2835_FSEL_ALT2] = "alt2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [BCM2835_FSEL_ALT3] = "alt3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) [BCM2835_FSEL_ALT4] = "alt4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [BCM2835_FSEL_ALT5] = "alt5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const char * const irq_type_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [IRQ_TYPE_NONE] = "none",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [IRQ_TYPE_EDGE_RISING] = "edge-rising",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) [IRQ_TYPE_EDGE_BOTH] = "edge-both",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [IRQ_TYPE_LEVEL_HIGH] = "level-high",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [IRQ_TYPE_LEVEL_LOW] = "level-low",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return readl(pc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(val, pc->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) reg += GPIO_REG_OFFSET(bit) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* note NOT a read/modify/write cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned reg, unsigned bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) reg += GPIO_REG_OFFSET(bit) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct bcm2835_pinctrl *pc, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bcm2835_functions[status]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static inline void bcm2835_pinctrl_fsel_set(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct bcm2835_pinctrl *pc, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) enum bcm2835_fsel fsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) bcm2835_functions[cur]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (cur == fsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* always transition through GPIO_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) val |= fsel << FSEL_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) bcm2835_functions[fsel]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return pinctrl_gpio_direction_input(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Alternative function doesn't clearly provide a direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (fsel > BCM2835_FSEL_GPIO_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (fsel == BCM2835_FSEL_GPIO_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) bcm2835_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return pinctrl_gpio_direction_output(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct gpio_chip bcm2835_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .label = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .direction_input = bcm2835_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .direction_output = bcm2835_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .get_direction = bcm2835_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .get = bcm2835_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .set = bcm2835_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .set_config = gpiochip_generic_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .ngpio = BCM2835_NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .can_sleep = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const struct gpio_chip bcm2711_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .label = "pinctrl-bcm2711",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .direction_input = bcm2835_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .direction_output = bcm2835_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .get_direction = bcm2835_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .get = bcm2835_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .set = bcm2835_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .set_config = gpiochip_generic_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .ngpio = BCM2711_NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .can_sleep = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int bank, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned long events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) events &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) events &= pc->enabled_irq_map[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) for_each_set_bit(offset, &events, 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) gpio = (32 * bank) + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct gpio_chip *chip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct irq_chip *host_chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int irq = irq_desc_get_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for (i = 0; i < BCM2835_NUM_IRQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (chip->irq.parents[i] == irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) group = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* This should not happen, every IRQ has a bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (i == BCM2835_NUM_IRQS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) chained_irq_enter(host_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) switch (group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case 0: /* IRQ0 covers GPIOs 0-27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case 1: /* IRQ1 covers GPIOs 28-45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case 2: /* IRQ2 covers GPIOs 46-57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) chained_irq_exit(host_chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned reg, unsigned offset, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) reg += GPIO_REG_OFFSET(offset) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) value = bcm2835_gpio_rd(pc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) value |= BIT(GPIO_REG_SHIFT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) value &= ~(BIT(GPIO_REG_SHIFT(offset)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) bcm2835_gpio_wr(pc, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* fast path for IRQ handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned offset, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) switch (pc->irq_type[offset]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static void bcm2835_gpio_irq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) unsigned gpio = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned offset = GPIO_REG_SHIFT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned bank = GPIO_REG_OFFSET(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) set_bit(offset, &pc->enabled_irq_map[bank]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) bcm2835_gpio_irq_config(pc, gpio, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static void bcm2835_gpio_irq_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) unsigned gpio = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned offset = GPIO_REG_SHIFT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned bank = GPIO_REG_OFFSET(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) bcm2835_gpio_irq_config(pc, gpio, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Clear events that were latched prior to clearing event sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) clear_bit(offset, &pc->enabled_irq_map[bank]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) unsigned offset, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case IRQ_TYPE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pc->irq_type[offset] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* slower path for reconfiguring IRQ type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned offset, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) case IRQ_TYPE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (pc->irq_type[offset] != type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) bcm2835_gpio_irq_config(pc, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pc->irq_type[offset] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* RISING already enabled, disable FALLING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) bcm2835_gpio_irq_config(pc, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pc->irq_type[offset] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) } else if (pc->irq_type[offset] != type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) bcm2835_gpio_irq_config(pc, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pc->irq_type[offset] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bcm2835_gpio_irq_config(pc, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* FALLING already enabled, disable RISING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) bcm2835_gpio_irq_config(pc, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) pc->irq_type[offset] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) } else if (pc->irq_type[offset] != type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) bcm2835_gpio_irq_config(pc, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pc->irq_type[offset] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) bcm2835_gpio_irq_config(pc, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* RISING already enabled, enable FALLING too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) bcm2835_gpio_irq_config(pc, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pc->irq_type[offset] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* FALLING already enabled, enable RISING too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) bcm2835_gpio_irq_config(pc, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pc->irq_type[offset] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) } else if (pc->irq_type[offset] != type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) bcm2835_gpio_irq_config(pc, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pc->irq_type[offset] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) bcm2835_gpio_irq_config(pc, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (pc->irq_type[offset] != type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) bcm2835_gpio_irq_config(pc, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) pc->irq_type[offset] = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) bcm2835_gpio_irq_config(pc, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned gpio = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned offset = GPIO_REG_SHIFT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) unsigned bank = GPIO_REG_OFFSET(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (test_bit(offset, &pc->enabled_irq_map[bank]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static void bcm2835_gpio_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned gpio = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) unsigned gpio = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) unsigned int irqgroup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (!pc->wake_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (gpio <= 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) irqgroup = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) else if (gpio >= 28 && gpio <= 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) irqgroup = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) else if (gpio >= 46 && gpio <= 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) irqgroup = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ret = enable_irq_wake(pc->wake_irq[irqgroup]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ret = disable_irq_wake(pc->wake_irq[irqgroup]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static struct irq_chip bcm2835_gpio_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .irq_enable = bcm2835_gpio_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .irq_disable = bcm2835_gpio_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .irq_set_type = bcm2835_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .irq_ack = bcm2835_gpio_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .irq_mask = bcm2835_gpio_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .irq_unmask = bcm2835_gpio_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .irq_set_wake = bcm2835_gpio_irq_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .flags = IRQCHIP_MASK_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return BCM2835_NUM_GPIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return bcm2835_gpio_groups[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *pins = &bcm2835_gpio_pins[selector].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) *num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct gpio_chip *chip = &pc->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) const char *fname = bcm2835_functions[fsel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) int irq = irq_find_mapping(chip->irq.domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) seq_printf(s, "function %s in %s; irq %d (%s)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) fname, value ? "hi" : "lo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) irq, irq_type_names[pc->irq_type[offset]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct pinctrl_map *maps, unsigned num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) for (i = 0; i < num_maps; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) kfree(maps[i].data.configs.configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) kfree(maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct device_node *np, u32 pin, u32 fnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct pinctrl_map **maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct pinctrl_map *map = *maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) map->type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) map->data.mux.group = bcm2835_gpio_groups[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) map->data.mux.function = bcm2835_functions[fnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) (*maps)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct device_node *np, u32 pin, u32 pull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct pinctrl_map **maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct pinctrl_map *map = *maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) unsigned long *configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (pull > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) configs = kzalloc(sizeof(*configs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (!configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) map->type = PIN_MAP_TYPE_CONFIGS_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) map->data.configs.configs = configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) map->data.configs.num_configs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) (*maps)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct pinctrl_map **map, unsigned int *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct property *pins, *funcs, *pulls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int num_pins, num_funcs, num_pulls, maps_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct pinctrl_map *maps, *cur_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) u32 pin, func, pull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* Check for generic binding in this node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (err || *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* Generic binding did not find anything continue with legacy parse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pins = of_find_property(np, "brcm,pins", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (!pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) funcs = of_find_property(np, "brcm,function", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) pulls = of_find_property(np, "brcm,pull", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (!funcs && !pulls) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dev_err(pc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) "%pOF: neither brcm,function nor brcm,pull specified\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) num_pins = pins->length / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) num_funcs = funcs ? (funcs->length / 4) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) num_pulls = pulls ? (pulls->length / 4) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (num_funcs > 1 && num_funcs != num_pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_err(pc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) "%pOF: brcm,function must have 1 or %d entries\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) np, num_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (num_pulls > 1 && num_pulls != num_pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) dev_err(pc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) "%pOF: brcm,pull must have 1 or %d entries\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) np, num_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) maps_per_pin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (num_funcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) maps_per_pin++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (num_pulls)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) maps_per_pin++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (!maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) for (i = 0; i < num_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (pin >= pc->pctl_desc.npins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) np, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (num_funcs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) err = of_property_read_u32_index(np, "brcm,function",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) (num_funcs > 1) ? i : 0, &func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) func, &cur_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (num_pulls) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) err = of_property_read_u32_index(np, "brcm,pull",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) (num_pulls > 1) ? i : 0, &pull);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) pull, &cur_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) *map = maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) *num_maps = num_pins * maps_per_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static const struct pinctrl_ops bcm2835_pctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .get_groups_count = bcm2835_pctl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .get_group_name = bcm2835_pctl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .get_group_pins = bcm2835_pctl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .dt_free_map = bcm2835_pctl_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* disable by setting to GPIO_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return BCM2835_FSEL_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return bcm2835_functions[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* every pin can do every function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) *groups = bcm2835_gpio_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) *num_groups = BCM2835_NUM_GPIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) unsigned func_selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) unsigned group_selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* disable by setting to GPIO_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) enum bcm2835_fsel fsel = input ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) bcm2835_pinctrl_fsel_set(pc, offset, fsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static const struct pinmux_ops bcm2835_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .free = bcm2835_pmx_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .get_functions_count = bcm2835_pmx_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .get_function_name = bcm2835_pmx_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .get_function_groups = bcm2835_pmx_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .set_mux = bcm2835_pmx_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) unsigned pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* No way to read back config in HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) unsigned int pin, unsigned int arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u32 off, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) off = GPIO_REG_OFFSET(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) bit = GPIO_REG_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) bcm2835_gpio_wr(pc, GPPUD, arg & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * BCM2835 datasheet say to wait 150 cycles, but not of what.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * But the VideoCore firmware delay for this operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * based nearly on the same amount of VPU cycles and this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * runs at 250 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unsigned int pin, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) u32 param, arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* Set legacy brcm,pull */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) case BCM2835_PINCONF_PARAM_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) bcm2835_pull_config_set(pc, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* Set pull generic bindings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* Set output-high or output-low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) } /* switch param type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static const struct pinconf_ops bcm2835_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .pin_config_get = bcm2835_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .pin_config_set = bcm2835_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) unsigned int pin, unsigned int arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) u32 shifter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) u32 off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) off = PUD_2711_REG_OFFSET(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) shifter = PUD_2711_REG_SHIFT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) value &= ~(PUD_2711_MASK << shifter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) value |= (arg << shifter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) unsigned int pin, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u32 param, arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* convert legacy brcm,pull */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) case BCM2835_PINCONF_PARAM_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (arg == BCM2835_PUD_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) arg = BCM2711_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) else if (arg == BCM2835_PUD_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) arg = BCM2711_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) arg = BCM2711_PULL_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) bcm2711_pull_config_set(pc, pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* Set pull generic bindings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Set output-high or output-low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static const struct pinconf_ops bcm2711_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .pin_config_get = bcm2835_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .pin_config_set = bcm2711_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static const struct pinctrl_desc bcm2835_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .pins = bcm2835_gpio_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .npins = BCM2835_NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .pctlops = &bcm2835_pctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .pmxops = &bcm2835_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .confops = &bcm2835_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static const struct pinctrl_desc bcm2711_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .name = "pinctrl-bcm2711",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .pins = bcm2835_gpio_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .npins = BCM2711_NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .pctlops = &bcm2835_pctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .pmxops = &bcm2835_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .confops = &bcm2711_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .npins = BCM2835_NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .name = "pinctrl-bcm2711",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .npins = BCM2711_NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct bcm_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) const struct gpio_chip *gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) const struct pinctrl_desc *pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) const struct pinctrl_gpio_range *gpio_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static const struct bcm_plat_data bcm2835_plat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .gpio_chip = &bcm2835_gpio_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .pctl_desc = &bcm2835_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .gpio_range = &bcm2835_pinctrl_gpio_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static const struct bcm_plat_data bcm2711_plat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .gpio_chip = &bcm2711_gpio_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .pctl_desc = &bcm2711_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .gpio_range = &bcm2711_pinctrl_gpio_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static const struct of_device_id bcm2835_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .compatible = "brcm,bcm2835-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .data = &bcm2835_plat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .compatible = "brcm,bcm2711-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .data = &bcm2711_plat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .compatible = "brcm,bcm7211-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .data = &bcm2711_plat_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) static int bcm2835_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) const struct bcm_plat_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct bcm2835_pinctrl *pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct resource iomem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) int is_7211 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (!pc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) platform_set_drvdata(pdev, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) pc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) err = of_address_to_resource(np, 0, &iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) dev_err(dev, "could not get IO memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) pc->base = devm_ioremap_resource(dev, &iomem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (IS_ERR(pc->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return PTR_ERR(pc->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) pdata = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) pc->gpio_chip = *pdata->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) pc->gpio_chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) pc->gpio_chip.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) for (i = 0; i < BCM2835_NUM_BANKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) unsigned long events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) unsigned offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* clear event detection flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* clear all the events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) for_each_set_bit(offset, &events, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) raw_spin_lock_init(&pc->irq_lock[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) pc->pctl_desc = *pdata->pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (IS_ERR(pc->pctl_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) gpiochip_remove(&pc->gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return PTR_ERR(pc->pctl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) pc->gpio_range = *pdata->gpio_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) pc->gpio_range.base = pc->gpio_chip.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) pc->gpio_range.gc = &pc->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) girq = &pc->gpio_chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) girq->chip = &bcm2835_gpio_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) girq->parent_handler = bcm2835_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) girq->num_parents = BCM2835_NUM_IRQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (!girq->parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) goto out_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (is_7211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) sizeof(*pc->wake_irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (!pc->wake_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) goto out_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * Use the same handler for all groups: this is necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * since we use one gpiochip to cover all lines - the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * irq handler then needs to figure out which group and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * bank that was firing the IRQ and look up the per-group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * and bank data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) for (i = 0; i < BCM2835_NUM_IRQS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) girq->parents[i] = irq_of_parse_and_map(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (!is_7211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /* Skip over the all banks interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) pc->wake_irq[i] = irq_of_parse_and_map(np, i +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) BCM2835_NUM_IRQS + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) len = strlen(dev_name(pc->dev)) + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (!name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) goto out_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* These are optional interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) err = devm_request_irq(dev, pc->wake_irq[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) bcm2835_gpio_wake_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) IRQF_SHARED, name, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) dev_warn(dev, "unable to request wake IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) pc->wake_irq[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) err = gpiochip_add_data(&pc->gpio_chip, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dev_err(dev, "could not add GPIO chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) goto out_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) out_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static struct platform_driver bcm2835_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .probe = bcm2835_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .name = MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .of_match_table = bcm2835_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) builtin_platform_driver(bcm2835_pinctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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