^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2013-2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* BCM281XX Pin Control Registers Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Function Select bits are the same for all pin control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BCM281XX_PIN_REG_F_SEL_MASK 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BCM281XX_PIN_REG_F_SEL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Standard pin register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BCM281XX_STD_PIN_REG_DRV_STR_MASK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BCM281XX_STD_PIN_REG_DRV_STR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BCM281XX_STD_PIN_REG_INPUT_DIS_MASK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BCM281XX_STD_PIN_REG_INPUT_DIS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BCM281XX_STD_PIN_REG_SLEW_MASK 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BCM281XX_STD_PIN_REG_SLEW_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BCM281XX_STD_PIN_REG_PULL_UP_MASK 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BCM281XX_STD_PIN_REG_PULL_UP_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BCM281XX_STD_PIN_REG_PULL_DN_MASK 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BCM281XX_STD_PIN_REG_PULL_DN_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BCM281XX_STD_PIN_REG_HYST_MASK 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BCM281XX_STD_PIN_REG_HYST_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* I2C pin register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BCM281XX_I2C_PIN_REG_INPUT_DIS_MASK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BCM281XX_I2C_PIN_REG_INPUT_DIS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BCM281XX_I2C_PIN_REG_SLEW_MASK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BCM281XX_I2C_PIN_REG_SLEW_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BCM281XX_I2C_PIN_REG_PULL_UP_STR_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* HDMI pin register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BCM281XX_HDMI_PIN_REG_INPUT_DIS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BCM281XX_HDMI_PIN_REG_MODE_MASK 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BCM281XX_HDMI_PIN_REG_MODE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * bcm281xx_pin_type - types of pin register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) enum bcm281xx_pin_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) BCM281XX_PIN_TYPE_UNKNOWN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) BCM281XX_PIN_TYPE_STD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) BCM281XX_PIN_TYPE_I2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) BCM281XX_PIN_TYPE_HDMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static enum bcm281xx_pin_type std_pin = BCM281XX_PIN_TYPE_STD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static enum bcm281xx_pin_type i2c_pin = BCM281XX_PIN_TYPE_I2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static enum bcm281xx_pin_type hdmi_pin = BCM281XX_PIN_TYPE_HDMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * bcm281xx_pin_function- define pin function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct bcm281xx_pin_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * bcm281xx_pinctrl_data - Broadcom-specific pinctrl data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @reg_base - base of pinctrl registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct bcm281xx_pinctrl_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* List of all pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const struct bcm281xx_pin_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) const unsigned nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Pin number definition. The order here must be the same as defined in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * PADCTRLREG block in the RDB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BCM281XX_PIN_ADCSYNC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BCM281XX_PIN_BAT_RM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BCM281XX_PIN_BSC1_SCL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BCM281XX_PIN_BSC1_SDA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BCM281XX_PIN_BSC2_SCL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BCM281XX_PIN_BSC2_SDA 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BCM281XX_PIN_CLASSGPWR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BCM281XX_PIN_CLK_CX8 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BCM281XX_PIN_CLKOUT_0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BCM281XX_PIN_CLKOUT_1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BCM281XX_PIN_CLKOUT_2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BCM281XX_PIN_CLKOUT_3 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BCM281XX_PIN_CLKREQ_IN_0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BCM281XX_PIN_CLKREQ_IN_1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BCM281XX_PIN_CWS_SYS_REQ1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BCM281XX_PIN_CWS_SYS_REQ2 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BCM281XX_PIN_CWS_SYS_REQ3 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BCM281XX_PIN_DIGMIC1_CLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BCM281XX_PIN_DIGMIC1_DQ 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BCM281XX_PIN_DIGMIC2_CLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BCM281XX_PIN_DIGMIC2_DQ 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BCM281XX_PIN_GPEN13 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BCM281XX_PIN_GPEN14 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BCM281XX_PIN_GPEN15 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BCM281XX_PIN_GPIO00 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BCM281XX_PIN_GPIO01 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BCM281XX_PIN_GPIO02 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BCM281XX_PIN_GPIO03 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BCM281XX_PIN_GPIO04 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BCM281XX_PIN_GPIO05 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define BCM281XX_PIN_GPIO06 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BCM281XX_PIN_GPIO07 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define BCM281XX_PIN_GPIO08 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BCM281XX_PIN_GPIO09 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BCM281XX_PIN_GPIO10 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define BCM281XX_PIN_GPIO11 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define BCM281XX_PIN_GPIO12 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define BCM281XX_PIN_GPIO13 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define BCM281XX_PIN_GPIO14 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define BCM281XX_PIN_GPS_PABLANK 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define BCM281XX_PIN_GPS_TMARK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BCM281XX_PIN_HDMI_SCL 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BCM281XX_PIN_HDMI_SDA 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BCM281XX_PIN_IC_DM 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BCM281XX_PIN_IC_DP 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define BCM281XX_PIN_KP_COL_IP_0 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define BCM281XX_PIN_KP_COL_IP_1 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BCM281XX_PIN_KP_COL_IP_2 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define BCM281XX_PIN_KP_COL_IP_3 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define BCM281XX_PIN_KP_ROW_OP_0 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define BCM281XX_PIN_KP_ROW_OP_1 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define BCM281XX_PIN_KP_ROW_OP_2 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define BCM281XX_PIN_KP_ROW_OP_3 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define BCM281XX_PIN_LCD_B_0 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define BCM281XX_PIN_LCD_B_1 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define BCM281XX_PIN_LCD_B_2 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define BCM281XX_PIN_LCD_B_3 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BCM281XX_PIN_LCD_B_4 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define BCM281XX_PIN_LCD_B_5 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BCM281XX_PIN_LCD_B_6 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define BCM281XX_PIN_LCD_B_7 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define BCM281XX_PIN_LCD_G_0 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define BCM281XX_PIN_LCD_G_1 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define BCM281XX_PIN_LCD_G_2 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define BCM281XX_PIN_LCD_G_3 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define BCM281XX_PIN_LCD_G_4 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define BCM281XX_PIN_LCD_G_5 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define BCM281XX_PIN_LCD_G_6 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define BCM281XX_PIN_LCD_G_7 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BCM281XX_PIN_LCD_HSYNC 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define BCM281XX_PIN_LCD_OE 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define BCM281XX_PIN_LCD_PCLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define BCM281XX_PIN_LCD_R_0 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define BCM281XX_PIN_LCD_R_1 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define BCM281XX_PIN_LCD_R_2 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define BCM281XX_PIN_LCD_R_3 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BCM281XX_PIN_LCD_R_4 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define BCM281XX_PIN_LCD_R_5 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define BCM281XX_PIN_LCD_R_6 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define BCM281XX_PIN_LCD_R_7 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define BCM281XX_PIN_LCD_VSYNC 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define BCM281XX_PIN_MDMGPIO0 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define BCM281XX_PIN_MDMGPIO1 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define BCM281XX_PIN_MDMGPIO2 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define BCM281XX_PIN_MDMGPIO3 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define BCM281XX_PIN_MDMGPIO4 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BCM281XX_PIN_MDMGPIO5 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define BCM281XX_PIN_MDMGPIO6 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define BCM281XX_PIN_MDMGPIO7 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define BCM281XX_PIN_MDMGPIO8 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define BCM281XX_PIN_MPHI_DATA_0 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define BCM281XX_PIN_MPHI_DATA_1 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define BCM281XX_PIN_MPHI_DATA_2 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define BCM281XX_PIN_MPHI_DATA_3 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define BCM281XX_PIN_MPHI_DATA_4 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define BCM281XX_PIN_MPHI_DATA_5 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define BCM281XX_PIN_MPHI_DATA_6 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define BCM281XX_PIN_MPHI_DATA_7 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define BCM281XX_PIN_MPHI_DATA_8 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define BCM281XX_PIN_MPHI_DATA_9 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define BCM281XX_PIN_MPHI_DATA_10 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define BCM281XX_PIN_MPHI_DATA_11 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define BCM281XX_PIN_MPHI_DATA_12 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define BCM281XX_PIN_MPHI_DATA_13 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define BCM281XX_PIN_MPHI_DATA_14 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define BCM281XX_PIN_MPHI_DATA_15 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define BCM281XX_PIN_MPHI_HA0 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define BCM281XX_PIN_MPHI_HAT0 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define BCM281XX_PIN_MPHI_HAT1 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define BCM281XX_PIN_MPHI_HCE0_N 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define BCM281XX_PIN_MPHI_HCE1_N 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define BCM281XX_PIN_MPHI_HRD_N 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define BCM281XX_PIN_MPHI_HWR_N 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define BCM281XX_PIN_MPHI_RUN0 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define BCM281XX_PIN_MPHI_RUN1 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define BCM281XX_PIN_MTX_SCAN_CLK 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define BCM281XX_PIN_MTX_SCAN_DATA 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define BCM281XX_PIN_NAND_AD_0 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define BCM281XX_PIN_NAND_AD_1 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define BCM281XX_PIN_NAND_AD_2 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define BCM281XX_PIN_NAND_AD_3 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define BCM281XX_PIN_NAND_AD_4 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define BCM281XX_PIN_NAND_AD_5 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define BCM281XX_PIN_NAND_AD_6 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define BCM281XX_PIN_NAND_AD_7 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define BCM281XX_PIN_NAND_ALE 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define BCM281XX_PIN_NAND_CEN_0 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define BCM281XX_PIN_NAND_CEN_1 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define BCM281XX_PIN_NAND_CLE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define BCM281XX_PIN_NAND_OEN 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define BCM281XX_PIN_NAND_RDY_0 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define BCM281XX_PIN_NAND_RDY_1 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define BCM281XX_PIN_NAND_WEN 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define BCM281XX_PIN_NAND_WP 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define BCM281XX_PIN_PC1 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define BCM281XX_PIN_PC2 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define BCM281XX_PIN_PMU_INT 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define BCM281XX_PIN_PMU_SCL 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define BCM281XX_PIN_PMU_SDA 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define BCM281XX_PIN_RFST2G_MTSLOTEN3G 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define BCM281XX_PIN_RGMII_0_RX_CTL 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define BCM281XX_PIN_RGMII_0_RXC 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define BCM281XX_PIN_RGMII_0_RXD_0 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define BCM281XX_PIN_RGMII_0_RXD_1 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define BCM281XX_PIN_RGMII_0_RXD_2 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define BCM281XX_PIN_RGMII_0_RXD_3 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define BCM281XX_PIN_RGMII_0_TX_CTL 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define BCM281XX_PIN_RGMII_0_TXC 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define BCM281XX_PIN_RGMII_0_TXD_0 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define BCM281XX_PIN_RGMII_0_TXD_1 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define BCM281XX_PIN_RGMII_0_TXD_2 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define BCM281XX_PIN_RGMII_0_TXD_3 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define BCM281XX_PIN_RGMII_1_RX_CTL 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define BCM281XX_PIN_RGMII_1_RXC 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define BCM281XX_PIN_RGMII_1_RXD_0 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define BCM281XX_PIN_RGMII_1_RXD_1 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define BCM281XX_PIN_RGMII_1_RXD_2 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define BCM281XX_PIN_RGMII_1_RXD_3 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define BCM281XX_PIN_RGMII_1_TX_CTL 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define BCM281XX_PIN_RGMII_1_TXC 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define BCM281XX_PIN_RGMII_1_TXD_0 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define BCM281XX_PIN_RGMII_1_TXD_1 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define BCM281XX_PIN_RGMII_1_TXD_2 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define BCM281XX_PIN_RGMII_1_TXD_3 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define BCM281XX_PIN_RGMII_GPIO_0 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define BCM281XX_PIN_RGMII_GPIO_1 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define BCM281XX_PIN_RGMII_GPIO_2 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define BCM281XX_PIN_RGMII_GPIO_3 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define BCM281XX_PIN_RTXDATA2G_TXDATA3G1 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define BCM281XX_PIN_RTXEN2G_TXDATA3G2 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define BCM281XX_PIN_RXDATA3G0 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define BCM281XX_PIN_RXDATA3G1 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define BCM281XX_PIN_RXDATA3G2 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define BCM281XX_PIN_SDIO1_CLK 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define BCM281XX_PIN_SDIO1_CMD 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define BCM281XX_PIN_SDIO1_DATA_0 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define BCM281XX_PIN_SDIO1_DATA_1 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define BCM281XX_PIN_SDIO1_DATA_2 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define BCM281XX_PIN_SDIO1_DATA_3 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define BCM281XX_PIN_SDIO4_CLK 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define BCM281XX_PIN_SDIO4_CMD 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define BCM281XX_PIN_SDIO4_DATA_0 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define BCM281XX_PIN_SDIO4_DATA_1 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define BCM281XX_PIN_SDIO4_DATA_2 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define BCM281XX_PIN_SDIO4_DATA_3 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define BCM281XX_PIN_SIM_CLK 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define BCM281XX_PIN_SIM_DATA 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define BCM281XX_PIN_SIM_DET 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define BCM281XX_PIN_SIM_RESETN 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define BCM281XX_PIN_SIM2_CLK 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define BCM281XX_PIN_SIM2_DATA 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define BCM281XX_PIN_SIM2_DET 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define BCM281XX_PIN_SIM2_RESETN 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define BCM281XX_PIN_SRI_C 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define BCM281XX_PIN_SRI_D 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define BCM281XX_PIN_SRI_E 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define BCM281XX_PIN_SSP_EXTCLK 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define BCM281XX_PIN_SSP0_CLK 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define BCM281XX_PIN_SSP0_FS 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define BCM281XX_PIN_SSP0_RXD 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define BCM281XX_PIN_SSP0_TXD 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define BCM281XX_PIN_SSP2_CLK 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define BCM281XX_PIN_SSP2_FS_0 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define BCM281XX_PIN_SSP2_FS_1 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define BCM281XX_PIN_SSP2_FS_2 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define BCM281XX_PIN_SSP2_FS_3 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define BCM281XX_PIN_SSP2_RXD_0 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define BCM281XX_PIN_SSP2_RXD_1 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define BCM281XX_PIN_SSP2_TXD_0 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define BCM281XX_PIN_SSP2_TXD_1 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define BCM281XX_PIN_SSP3_CLK 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define BCM281XX_PIN_SSP3_FS 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define BCM281XX_PIN_SSP3_RXD 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define BCM281XX_PIN_SSP3_TXD 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define BCM281XX_PIN_SSP4_CLK 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define BCM281XX_PIN_SSP4_FS 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define BCM281XX_PIN_SSP4_RXD 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define BCM281XX_PIN_SSP4_TXD 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define BCM281XX_PIN_SSP5_CLK 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define BCM281XX_PIN_SSP5_FS 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define BCM281XX_PIN_SSP5_RXD 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define BCM281XX_PIN_SSP5_TXD 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define BCM281XX_PIN_SSP6_CLK 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define BCM281XX_PIN_SSP6_FS 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define BCM281XX_PIN_SSP6_RXD 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define BCM281XX_PIN_SSP6_TXD 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define BCM281XX_PIN_STAT_1 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define BCM281XX_PIN_STAT_2 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define BCM281XX_PIN_SYSCLKEN 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define BCM281XX_PIN_TRACECLK 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define BCM281XX_PIN_TRACEDT00 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define BCM281XX_PIN_TRACEDT01 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define BCM281XX_PIN_TRACEDT02 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define BCM281XX_PIN_TRACEDT03 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define BCM281XX_PIN_TRACEDT04 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define BCM281XX_PIN_TRACEDT05 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define BCM281XX_PIN_TRACEDT06 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define BCM281XX_PIN_TRACEDT07 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define BCM281XX_PIN_TRACEDT08 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define BCM281XX_PIN_TRACEDT09 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define BCM281XX_PIN_TRACEDT10 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define BCM281XX_PIN_TRACEDT11 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define BCM281XX_PIN_TRACEDT12 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define BCM281XX_PIN_TRACEDT13 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define BCM281XX_PIN_TRACEDT14 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define BCM281XX_PIN_TRACEDT15 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define BCM281XX_PIN_TXDATA3G0 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define BCM281XX_PIN_TXPWRIND 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define BCM281XX_PIN_UARTB1_UCTS 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define BCM281XX_PIN_UARTB1_URTS 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define BCM281XX_PIN_UARTB1_URXD 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define BCM281XX_PIN_UARTB1_UTXD 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define BCM281XX_PIN_UARTB2_URXD 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define BCM281XX_PIN_UARTB2_UTXD 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define BCM281XX_PIN_UARTB3_UCTS 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define BCM281XX_PIN_UARTB3_URTS 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define BCM281XX_PIN_UARTB3_URXD 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define BCM281XX_PIN_UARTB3_UTXD 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define BCM281XX_PIN_UARTB4_UCTS 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define BCM281XX_PIN_UARTB4_URTS 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define BCM281XX_PIN_UARTB4_URXD 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define BCM281XX_PIN_UARTB4_UTXD 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define BCM281XX_PIN_VC_CAM1_SCL 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define BCM281XX_PIN_VC_CAM1_SDA 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define BCM281XX_PIN_VC_CAM2_SCL 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define BCM281XX_PIN_VC_CAM2_SDA 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define BCM281XX_PIN_VC_CAM3_SCL 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define BCM281XX_PIN_VC_CAM3_SDA 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define BCM281XX_PIN_DESC(a, b, c) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { .number = a, .name = b, .drv_data = &c##_pin }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * Pin description definition. The order here must be the same as defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * the PADCTRLREG block in the RDB, since the pin number is used as an index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * into this array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct pinctrl_pin_desc bcm281xx_pinctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) BCM281XX_PIN_DESC(BCM281XX_PIN_ADCSYNC, "adcsync", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) BCM281XX_PIN_DESC(BCM281XX_PIN_BAT_RM, "bat_rm", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SCL, "bsc1_scl", i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) BCM281XX_PIN_DESC(BCM281XX_PIN_BSC1_SDA, "bsc1_sda", i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SCL, "bsc2_scl", i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) BCM281XX_PIN_DESC(BCM281XX_PIN_BSC2_SDA, "bsc2_sda", i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) BCM281XX_PIN_DESC(BCM281XX_PIN_CLASSGPWR, "classgpwr", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) BCM281XX_PIN_DESC(BCM281XX_PIN_CLK_CX8, "clk_cx8", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_0, "clkout_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_1, "clkout_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_2, "clkout_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) BCM281XX_PIN_DESC(BCM281XX_PIN_CLKOUT_3, "clkout_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_0, "clkreq_in_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) BCM281XX_PIN_DESC(BCM281XX_PIN_CLKREQ_IN_1, "clkreq_in_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ1, "cws_sys_req1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ2, "cws_sys_req2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) BCM281XX_PIN_DESC(BCM281XX_PIN_CWS_SYS_REQ3, "cws_sys_req3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_CLK, "digmic1_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC1_DQ, "digmic1_dq", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_CLK, "digmic2_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) BCM281XX_PIN_DESC(BCM281XX_PIN_DIGMIC2_DQ, "digmic2_dq", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN13, "gpen13", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN14, "gpen14", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) BCM281XX_PIN_DESC(BCM281XX_PIN_GPEN15, "gpen15", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO00, "gpio00", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO01, "gpio01", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO02, "gpio02", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO03, "gpio03", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO04, "gpio04", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO05, "gpio05", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO06, "gpio06", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO07, "gpio07", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO08, "gpio08", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO09, "gpio09", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO10, "gpio10", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO11, "gpio11", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO12, "gpio12", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO13, "gpio13", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) BCM281XX_PIN_DESC(BCM281XX_PIN_GPIO14, "gpio14", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_PABLANK, "gps_pablank", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) BCM281XX_PIN_DESC(BCM281XX_PIN_GPS_TMARK, "gps_tmark", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SCL, "hdmi_scl", hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) BCM281XX_PIN_DESC(BCM281XX_PIN_HDMI_SDA, "hdmi_sda", hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DM, "ic_dm", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) BCM281XX_PIN_DESC(BCM281XX_PIN_IC_DP, "ic_dp", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_0, "kp_col_ip_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_1, "kp_col_ip_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_2, "kp_col_ip_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) BCM281XX_PIN_DESC(BCM281XX_PIN_KP_COL_IP_3, "kp_col_ip_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_0, "kp_row_op_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_1, "kp_row_op_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_2, "kp_row_op_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) BCM281XX_PIN_DESC(BCM281XX_PIN_KP_ROW_OP_3, "kp_row_op_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_0, "lcd_b_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_1, "lcd_b_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_2, "lcd_b_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_3, "lcd_b_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_4, "lcd_b_4", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_5, "lcd_b_5", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_6, "lcd_b_6", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_B_7, "lcd_b_7", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_0, "lcd_g_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_1, "lcd_g_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_2, "lcd_g_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_3, "lcd_g_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_4, "lcd_g_4", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_5, "lcd_g_5", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_6, "lcd_g_6", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_G_7, "lcd_g_7", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_HSYNC, "lcd_hsync", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_OE, "lcd_oe", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_PCLK, "lcd_pclk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_0, "lcd_r_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_1, "lcd_r_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_2, "lcd_r_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_3, "lcd_r_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_4, "lcd_r_4", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_5, "lcd_r_5", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_6, "lcd_r_6", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_R_7, "lcd_r_7", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) BCM281XX_PIN_DESC(BCM281XX_PIN_LCD_VSYNC, "lcd_vsync", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO0, "mdmgpio0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO1, "mdmgpio1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO2, "mdmgpio2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO3, "mdmgpio3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO4, "mdmgpio4", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO5, "mdmgpio5", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO6, "mdmgpio6", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO7, "mdmgpio7", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) BCM281XX_PIN_DESC(BCM281XX_PIN_MDMGPIO8, "mdmgpio8", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_0, "mphi_data_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_1, "mphi_data_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_2, "mphi_data_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_3, "mphi_data_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_4, "mphi_data_4", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_5, "mphi_data_5", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_6, "mphi_data_6", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_7, "mphi_data_7", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_8, "mphi_data_8", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_9, "mphi_data_9", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_10, "mphi_data_10", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_11, "mphi_data_11", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_12, "mphi_data_12", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_13, "mphi_data_13", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_14, "mphi_data_14", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_DATA_15, "mphi_data_15", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HA0, "mphi_ha0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT0, "mphi_hat0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HAT1, "mphi_hat1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE0_N, "mphi_hce0_n", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HCE1_N, "mphi_hce1_n", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HRD_N, "mphi_hrd_n", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_HWR_N, "mphi_hwr_n", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN0, "mphi_run0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) BCM281XX_PIN_DESC(BCM281XX_PIN_MPHI_RUN1, "mphi_run1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) BCM281XX_PIN_DESC(BCM281XX_PIN_MTX_SCAN_DATA, "mtx_scan_data", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_0, "nand_ad_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_1, "nand_ad_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_2, "nand_ad_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_3, "nand_ad_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_4, "nand_ad_4", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_5, "nand_ad_5", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_6, "nand_ad_6", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_AD_7, "nand_ad_7", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_ALE, "nand_ale", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_0, "nand_cen_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CEN_1, "nand_cen_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_CLE, "nand_cle", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_OEN, "nand_oen", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_0, "nand_rdy_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_RDY_1, "nand_rdy_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WEN, "nand_wen", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) BCM281XX_PIN_DESC(BCM281XX_PIN_NAND_WP, "nand_wp", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) BCM281XX_PIN_DESC(BCM281XX_PIN_PC1, "pc1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) BCM281XX_PIN_DESC(BCM281XX_PIN_PC2, "pc2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_INT, "pmu_int", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SCL, "pmu_scl", i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) BCM281XX_PIN_DESC(BCM281XX_PIN_PMU_SDA, "pmu_sda", i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) BCM281XX_PIN_DESC(BCM281XX_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXC, "rgmii_0_rxc", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXC, "rgmii_0_txc", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXC, "rgmii_1_rxc", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXC, "rgmii_1_txc", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) BCM281XX_PIN_DESC(BCM281XX_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) BCM281XX_PIN_DESC(BCM281XX_PIN_RTXDATA2G_TXDATA3G1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) "rtxdata2g_txdata3g1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) BCM281XX_PIN_DESC(BCM281XX_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G0, "rxdata3g0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G1, "rxdata3g1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) BCM281XX_PIN_DESC(BCM281XX_PIN_RXDATA3G2, "rxdata3g2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CLK, "sdio1_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_CMD, "sdio1_cmd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_0, "sdio1_data_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_1, "sdio1_data_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_2, "sdio1_data_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO1_DATA_3, "sdio1_data_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CLK, "sdio4_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_CMD, "sdio4_cmd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_0, "sdio4_data_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_1, "sdio4_data_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_2, "sdio4_data_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) BCM281XX_PIN_DESC(BCM281XX_PIN_SDIO4_DATA_3, "sdio4_data_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_CLK, "sim_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DATA, "sim_data", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_DET, "sim_det", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) BCM281XX_PIN_DESC(BCM281XX_PIN_SIM_RESETN, "sim_resetn", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_CLK, "sim2_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DATA, "sim2_data", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_DET, "sim2_det", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) BCM281XX_PIN_DESC(BCM281XX_PIN_SIM2_RESETN, "sim2_resetn", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_C, "sri_c", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_D, "sri_d", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) BCM281XX_PIN_DESC(BCM281XX_PIN_SRI_E, "sri_e", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP_EXTCLK, "ssp_extclk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_CLK, "ssp0_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_FS, "ssp0_fs", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_RXD, "ssp0_rxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP0_TXD, "ssp0_txd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_CLK, "ssp2_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_0, "ssp2_fs_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_1, "ssp2_fs_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_2, "ssp2_fs_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_FS_3, "ssp2_fs_3", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_0, "ssp2_rxd_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_RXD_1, "ssp2_rxd_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_0, "ssp2_txd_0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP2_TXD_1, "ssp2_txd_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_CLK, "ssp3_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_FS, "ssp3_fs", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_RXD, "ssp3_rxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP3_TXD, "ssp3_txd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_CLK, "ssp4_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_FS, "ssp4_fs", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_RXD, "ssp4_rxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP4_TXD, "ssp4_txd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_CLK, "ssp5_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_FS, "ssp5_fs", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_RXD, "ssp5_rxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP5_TXD, "ssp5_txd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_CLK, "ssp6_clk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_FS, "ssp6_fs", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_RXD, "ssp6_rxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) BCM281XX_PIN_DESC(BCM281XX_PIN_SSP6_TXD, "ssp6_txd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_1, "stat_1", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) BCM281XX_PIN_DESC(BCM281XX_PIN_STAT_2, "stat_2", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) BCM281XX_PIN_DESC(BCM281XX_PIN_SYSCLKEN, "sysclken", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACECLK, "traceclk", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT00, "tracedt00", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT01, "tracedt01", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT02, "tracedt02", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT03, "tracedt03", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT04, "tracedt04", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT05, "tracedt05", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT06, "tracedt06", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT07, "tracedt07", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT08, "tracedt08", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT09, "tracedt09", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT10, "tracedt10", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT11, "tracedt11", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT12, "tracedt12", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT13, "tracedt13", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT14, "tracedt14", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) BCM281XX_PIN_DESC(BCM281XX_PIN_TRACEDT15, "tracedt15", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) BCM281XX_PIN_DESC(BCM281XX_PIN_TXDATA3G0, "txdata3g0", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) BCM281XX_PIN_DESC(BCM281XX_PIN_TXPWRIND, "txpwrind", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UCTS, "uartb1_ucts", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URTS, "uartb1_urts", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_URXD, "uartb1_urxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB1_UTXD, "uartb1_utxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_URXD, "uartb2_urxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB2_UTXD, "uartb2_utxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UCTS, "uartb3_ucts", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URTS, "uartb3_urts", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_URXD, "uartb3_urxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB3_UTXD, "uartb3_utxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UCTS, "uartb4_ucts", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URTS, "uartb4_urts", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_URXD, "uartb4_urxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) BCM281XX_PIN_DESC(BCM281XX_PIN_UARTB4_UTXD, "uartb4_utxd", std),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) BCM281XX_PIN_DESC(BCM281XX_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static const char * const bcm281xx_alt_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) "adcsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) "bat_rm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) "bsc1_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "bsc1_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) "bsc2_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) "bsc2_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) "classgpwr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "clk_cx8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) "clkout_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "clkout_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "clkout_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "clkout_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "clkreq_in_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "clkreq_in_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) "cws_sys_req1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) "cws_sys_req2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) "cws_sys_req3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) "digmic1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) "digmic1_dq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "digmic2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) "digmic2_dq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) "gpen13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) "gpen14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) "gpen15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) "gpio00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) "gpio01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) "gpio02",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "gpio03",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) "gpio04",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) "gpio05",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "gpio06",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "gpio07",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) "gpio08",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) "gpio09",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "gps_pablank",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) "gps_tmark",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) "hdmi_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "hdmi_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) "ic_dm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) "ic_dp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) "kp_col_ip_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) "kp_col_ip_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) "kp_col_ip_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) "kp_col_ip_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) "kp_row_op_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) "kp_row_op_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) "kp_row_op_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "kp_row_op_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) "lcd_b_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) "lcd_b_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "lcd_b_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) "lcd_b_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "lcd_b_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "lcd_b_5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) "lcd_b_6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) "lcd_b_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) "lcd_g_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) "lcd_g_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) "lcd_g_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) "lcd_g_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "lcd_g_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "lcd_g_5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) "lcd_g_6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "lcd_g_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) "lcd_hsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "lcd_oe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) "lcd_pclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) "lcd_r_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "lcd_r_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) "lcd_r_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "lcd_r_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) "lcd_r_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) "lcd_r_5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "lcd_r_6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "lcd_r_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "lcd_vsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "mdmgpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "mdmgpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "mdmgpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "mdmgpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "mdmgpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) "mdmgpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "mdmgpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) "mdmgpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) "mdmgpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) "mphi_data_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) "mphi_data_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "mphi_data_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "mphi_data_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "mphi_data_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "mphi_data_5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "mphi_data_6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) "mphi_data_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) "mphi_data_8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) "mphi_data_9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "mphi_data_10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "mphi_data_11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "mphi_data_12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "mphi_data_13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) "mphi_data_14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "mphi_data_15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "mphi_ha0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) "mphi_hat0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "mphi_hat1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) "mphi_hce0_n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) "mphi_hce1_n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "mphi_hrd_n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) "mphi_hwr_n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "mphi_run0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "mphi_run1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) "mtx_scan_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) "mtx_scan_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) "nand_ad_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "nand_ad_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "nand_ad_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) "nand_ad_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "nand_ad_4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) "nand_ad_5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) "nand_ad_6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) "nand_ad_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) "nand_ale",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) "nand_cen_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "nand_cen_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) "nand_cle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) "nand_oen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "nand_rdy_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) "nand_rdy_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) "nand_wen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "nand_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) "pc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "pc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "pmu_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) "pmu_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) "pmu_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "rfst2g_mtsloten3g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) "rgmii_0_rx_ctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) "rgmii_0_rxc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) "rgmii_0_rxd_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "rgmii_0_rxd_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "rgmii_0_rxd_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "rgmii_0_rxd_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) "rgmii_0_tx_ctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) "rgmii_0_txc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "rgmii_0_txd_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) "rgmii_0_txd_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) "rgmii_0_txd_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "rgmii_0_txd_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) "rgmii_1_rx_ctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "rgmii_1_rxc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "rgmii_1_rxd_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "rgmii_1_rxd_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "rgmii_1_rxd_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "rgmii_1_rxd_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) "rgmii_1_tx_ctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) "rgmii_1_txc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) "rgmii_1_txd_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) "rgmii_1_txd_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) "rgmii_1_txd_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) "rgmii_1_txd_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) "rgmii_gpio_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) "rgmii_gpio_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) "rgmii_gpio_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) "rgmii_gpio_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) "rtxdata2g_txdata3g1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) "rtxen2g_txdata3g2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "rxdata3g0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "rxdata3g1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) "rxdata3g2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "sdio1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "sdio1_cmd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "sdio1_data_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "sdio1_data_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "sdio1_data_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) "sdio1_data_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) "sdio4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) "sdio4_cmd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "sdio4_data_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) "sdio4_data_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) "sdio4_data_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "sdio4_data_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "sim_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) "sim_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) "sim_det",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) "sim_resetn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) "sim2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) "sim2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "sim2_det",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "sim2_resetn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) "sri_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) "sri_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) "sri_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) "ssp_extclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) "ssp0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) "ssp0_fs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) "ssp0_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) "ssp0_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "ssp2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) "ssp2_fs_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) "ssp2_fs_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) "ssp2_fs_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) "ssp2_fs_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) "ssp2_rxd_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) "ssp2_rxd_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) "ssp2_txd_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) "ssp2_txd_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) "ssp3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) "ssp3_fs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) "ssp3_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) "ssp3_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) "ssp4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) "ssp4_fs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) "ssp4_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) "ssp4_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) "ssp5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) "ssp5_fs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) "ssp5_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) "ssp5_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "ssp6_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) "ssp6_fs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) "ssp6_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) "ssp6_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) "stat_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) "stat_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) "sysclken",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) "traceclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) "tracedt00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "tracedt01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) "tracedt02",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "tracedt03",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) "tracedt04",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "tracedt05",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) "tracedt06",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "tracedt07",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) "tracedt08",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) "tracedt09",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) "tracedt10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) "tracedt11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) "tracedt12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "tracedt13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) "tracedt14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) "tracedt15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) "txdata3g0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) "txpwrind",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) "uartb1_ucts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "uartb1_urts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) "uartb1_urxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) "uartb1_utxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) "uartb2_urxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) "uartb2_utxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) "uartb3_ucts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) "uartb3_urts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) "uartb3_urxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) "uartb3_utxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) "uartb4_ucts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) "uartb4_urts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) "uartb4_urxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) "uartb4_utxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) "vc_cam1_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) "vc_cam1_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) "vc_cam2_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) "vc_cam2_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) "vc_cam3_scl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) "vc_cam3_sda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* Every pin can implement all ALT1-ALT4 functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define BCM281XX_PIN_FUNCTION(fcn_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .name = #fcn_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .groups = bcm281xx_alt_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .ngroups = ARRAY_SIZE(bcm281xx_alt_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static const struct bcm281xx_pin_function bcm281xx_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) BCM281XX_PIN_FUNCTION(alt1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) BCM281XX_PIN_FUNCTION(alt2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) BCM281XX_PIN_FUNCTION(alt3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) BCM281XX_PIN_FUNCTION(alt4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static struct bcm281xx_pinctrl_data bcm281xx_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .pins = bcm281xx_pinctrl_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .npins = ARRAY_SIZE(bcm281xx_pinctrl_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .functions = bcm281xx_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .nfunctions = ARRAY_SIZE(bcm281xx_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static inline enum bcm281xx_pin_type pin_type_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (pin >= pdata->npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return BCM281XX_PIN_TYPE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return *(enum bcm281xx_pin_type *)(pdata->pins[pin].drv_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define BCM281XX_PIN_SHIFT(type, param) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) (BCM281XX_ ## type ## _PIN_REG_ ## param ## _SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define BCM281XX_PIN_MASK(type, param) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) (BCM281XX_ ## type ## _PIN_REG_ ## param ## _MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * This helper function is used to build up the value and mask used to write to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * a pin register, but does not actually write to the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static inline void bcm281xx_pin_update(u32 *reg_val, u32 *reg_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) u32 param_val, u32 param_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) u32 param_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) *reg_val &= ~param_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) *reg_val |= (param_val << param_shift) & param_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) *reg_mask |= param_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const struct regmap_config bcm281xx_pinctrl_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .max_register = BCM281XX_PIN_VC_CAM3_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static int bcm281xx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return pdata->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static const char *bcm281xx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return pdata->pins[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int bcm281xx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) *pins = &pdata->pins[group].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) *num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static void bcm281xx_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) seq_printf(s, " %s", dev_name(pctldev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static const struct pinctrl_ops bcm281xx_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .get_groups_count = bcm281xx_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .get_group_name = bcm281xx_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .get_group_pins = bcm281xx_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .pin_dbg_show = bcm281xx_pinctrl_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static int bcm281xx_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return pdata->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static const char *bcm281xx_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) unsigned function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return pdata->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static int bcm281xx_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) *groups = pdata->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) *num_groups = pdata->functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static int bcm281xx_pinmux_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) const struct bcm281xx_pin_function *f = &pdata->functions[function];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) u32 offset = 4 * pdata->pins[group].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dev_dbg(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) __func__, f->name, function, pdata->pins[group].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) pdata->pins[group].number, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) rc = regmap_update_bits(pdata->regmap, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) BCM281XX_PIN_REG_F_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) function << BCM281XX_PIN_REG_F_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) dev_err(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) "Error updating register for pin %s (%d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) pdata->pins[group].name, pdata->pins[group].number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static const struct pinmux_ops bcm281xx_pinctrl_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .get_functions_count = bcm281xx_pinctrl_get_fcns_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .get_function_name = bcm281xx_pinctrl_get_fcn_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .get_function_groups = bcm281xx_pinctrl_get_fcn_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .set_mux = bcm281xx_pinmux_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static int bcm281xx_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* Goes through the configs and update register val/mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static int bcm281xx_std_pin_update(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) unsigned num_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) u32 *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) u32 *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) arg = (arg >= 1 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) bcm281xx_pin_update(val, mask, arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) BCM281XX_PIN_SHIFT(STD, HYST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) BCM281XX_PIN_MASK(STD, HYST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * The pin bias can only be one of pull-up, pull-down, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * disable. The user does not need to specify a value for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * property, and the default value from pinconf-generic is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) bcm281xx_pin_update(val, mask, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) BCM281XX_PIN_SHIFT(STD, PULL_UP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) BCM281XX_PIN_MASK(STD, PULL_UP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) bcm281xx_pin_update(val, mask, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) BCM281XX_PIN_SHIFT(STD, PULL_DN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) BCM281XX_PIN_MASK(STD, PULL_DN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) bcm281xx_pin_update(val, mask, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) BCM281XX_PIN_SHIFT(STD, PULL_UP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) BCM281XX_PIN_MASK(STD, PULL_UP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) bcm281xx_pin_update(val, mask, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) BCM281XX_PIN_SHIFT(STD, PULL_DN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) BCM281XX_PIN_MASK(STD, PULL_DN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) bcm281xx_pin_update(val, mask, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) BCM281XX_PIN_SHIFT(STD, PULL_UP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) BCM281XX_PIN_MASK(STD, PULL_UP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) bcm281xx_pin_update(val, mask, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) BCM281XX_PIN_SHIFT(STD, PULL_DN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) BCM281XX_PIN_MASK(STD, PULL_DN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) arg = (arg >= 1 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) bcm281xx_pin_update(val, mask, arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) BCM281XX_PIN_SHIFT(STD, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) BCM281XX_PIN_MASK(STD, SLEW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /* inversed since register is for input _disable_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) arg = (arg >= 1 ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) bcm281xx_pin_update(val, mask, arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) BCM281XX_PIN_SHIFT(STD, INPUT_DIS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) BCM281XX_PIN_MASK(STD, INPUT_DIS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* Valid range is 2-16 mA, even numbers only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if ((arg < 2) || (arg > 16) || (arg % 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) dev_err(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) "Invalid Drive Strength value (%d) for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) "pin %s (%d). Valid values are "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) "(2..16) mA, even numbers only.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) arg, pdata->pins[pin].name, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) bcm281xx_pin_update(val, mask, (arg/2)-1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) BCM281XX_PIN_SHIFT(STD, DRV_STR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) BCM281XX_PIN_MASK(STD, DRV_STR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) dev_err(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) "Unrecognized pin config %d for pin %s (%d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) param, pdata->pins[pin].name, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) } /* switch config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) * The pull-up strength for an I2C pin is represented by bits 4-6 in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) * register with the following mapping:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * 0b000: No pull-up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * 0b001: 1200 Ohm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * 0b010: 1800 Ohm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * 0b011: 720 Ohm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * 0b100: 2700 Ohm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * 0b101: 831 Ohm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * 0b110: 1080 Ohm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * 0b111: 568 Ohm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) * This array maps pull-up strength in Ohms to register values (1+index).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static const u16 bcm281xx_pullup_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) 1200, 1800, 720, 2700, 831, 1080, 568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* Goes through the configs and update register val/mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static int bcm281xx_i2c_pin_update(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) unsigned num_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) u32 *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) u32 *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) for (j = 0; j < ARRAY_SIZE(bcm281xx_pullup_map); j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (bcm281xx_pullup_map[j] == arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (j == ARRAY_SIZE(bcm281xx_pullup_map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) dev_err(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) "Invalid pull-up value (%d) for pin %s "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) "(%d). Valid values are 568, 720, 831, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) "1080, 1200, 1800, 2700 Ohms.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) arg, pdata->pins[pin].name, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) bcm281xx_pin_update(val, mask, j+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) bcm281xx_pin_update(val, mask, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) BCM281XX_PIN_SHIFT(I2C, PULL_UP_STR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) BCM281XX_PIN_MASK(I2C, PULL_UP_STR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) arg = (arg >= 1 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) bcm281xx_pin_update(val, mask, arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) BCM281XX_PIN_SHIFT(I2C, SLEW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) BCM281XX_PIN_MASK(I2C, SLEW));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* inversed since register is for input _disable_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) arg = (arg >= 1 ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) bcm281xx_pin_update(val, mask, arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) BCM281XX_PIN_SHIFT(I2C, INPUT_DIS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) BCM281XX_PIN_MASK(I2C, INPUT_DIS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dev_err(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) "Unrecognized pin config %d for pin %s (%d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) param, pdata->pins[pin].name, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) } /* switch config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* Goes through the configs and update register val/mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static int bcm281xx_hdmi_pin_update(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) unsigned num_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u32 *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) u32 *mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) arg = (arg >= 1 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) bcm281xx_pin_update(val, mask, arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) BCM281XX_PIN_SHIFT(HDMI, MODE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) BCM281XX_PIN_MASK(HDMI, MODE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /* inversed since register is for input _disable_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) arg = (arg >= 1 ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) bcm281xx_pin_update(val, mask, arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) BCM281XX_PIN_SHIFT(HDMI, INPUT_DIS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) BCM281XX_PIN_MASK(HDMI, INPUT_DIS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dev_err(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) "Unrecognized pin config %d for pin %s (%d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) param, pdata->pins[pin].name, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) } /* switch config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct bcm281xx_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) enum bcm281xx_pin_type pin_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) u32 offset = 4 * pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) u32 cfg_val, cfg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) cfg_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) cfg_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) pin_type = pin_type_get(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /* Different pins have different configuration options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) switch (pin_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) case BCM281XX_PIN_TYPE_STD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) rc = bcm281xx_std_pin_update(pctldev, pin, configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) num_configs, &cfg_val, &cfg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) case BCM281XX_PIN_TYPE_I2C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) rc = bcm281xx_i2c_pin_update(pctldev, pin, configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) num_configs, &cfg_val, &cfg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) case BCM281XX_PIN_TYPE_HDMI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) rc = bcm281xx_hdmi_pin_update(pctldev, pin, configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) num_configs, &cfg_val, &cfg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) pdata->pins[pin].name, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) } /* switch pin type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_dbg(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dev_err(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) "Error updating register for pin %s (%d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) pdata->pins[pin].name, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static const struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .pin_config_get = bcm281xx_pinctrl_pin_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .pin_config_set = bcm281xx_pinctrl_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static struct pinctrl_desc bcm281xx_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* name, pins, npins members initialized in probe function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .pctlops = &bcm281xx_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .pmxops = &bcm281xx_pinctrl_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .confops = &bcm281xx_pinctrl_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) struct bcm281xx_pinctrl_data *pdata = &bcm281xx_pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* So far We can assume there is only 1 bank of registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) pdata->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (IS_ERR(pdata->reg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) return PTR_ERR(pdata->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) /* Initialize the dynamic part of pinctrl_desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) &bcm281xx_pinctrl_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (IS_ERR(pdata->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) dev_err(&pdev->dev, "Regmap MMIO init failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) bcm281xx_pinctrl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) bcm281xx_pinctrl_desc.pins = bcm281xx_pinctrl.pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) bcm281xx_pinctrl_desc.npins = bcm281xx_pinctrl.npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) pctl = devm_pinctrl_register(&pdev->dev, &bcm281xx_pinctrl_desc, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (IS_ERR(pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) dev_err(&pdev->dev, "Failed to register pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return PTR_ERR(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) platform_set_drvdata(pdev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static const struct of_device_id bcm281xx_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) { .compatible = "brcm,bcm11351-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static struct platform_driver bcm281xx_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .name = "bcm281xx-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .of_match_table = bcm281xx_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) builtin_platform_driver_probe(bcm281xx_pinctrl_driver, bcm281xx_pinctrl_probe);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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