^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2019 IBM Corp. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef ASPEED_PINMUX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define ASPEED_PINMUX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <stdbool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * The ASPEED SoCs provide typically more than 200 pins for GPIO and other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * functions. The SoC function enabled on a pin is determined on a priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * basis where a given pin can provide a number of different signal types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The signal active on a pin is described by both a priority level and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * compound logical expressions involving multiple operators, registers and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * bits. Some difficulty arises as the pin's function bit masks for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * priority level are frequently not the same (i.e. cannot just flip a bit to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * change from a high to low priority signal), or even in the same register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Further, not all signals can be unmuxed, as some expressions depend on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * values in the hardware strapping register (which may be treated as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * read-only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * SoC Multi-function Pin Expression Examples
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * ------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Here are some sample mux configurations from the AST2400 and AST2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * datasheets to illustrate the corner cases, roughly in order of least to most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * corner. The signal priorities are in decending order from P0 (highest).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * D6 is a pin with a single function (beside GPIO); a high priority signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * that participates in one function:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * -----+---------+-----------+-----------------------------+-----------+---------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * D6 GPIOA0 MAC1LINK SCU80[0]=1 GPIOA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * -----+---------+-----------+-----------------------------+-----------+---------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * C5 is a multi-signal pin (high and low priority signals). Here we touch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * different registers for the different functions that enable each signal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * -----+---------+-----------+-----------------------------+-----------+---------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * C5 GPIOA4 SCL9 SCU90[22]=1 TIMER5 SCU80[4]=1 GPIOA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * -----+---------+-----------+-----------------------------+-----------+---------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * E19 is a single-signal pin with two functions that influence the active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * signal. In this case both bits have the same meaning - enable a dedicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * LPC reset pin. However it's not always the case that the bits in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * OR-relationship have the same meaning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * -----+---------+-----------+-----------------------------+-----------+---------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * E19 GPIOB4 LPCRST# SCU80[12]=1 | Strap[14]=1 GPIOB4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * -----+---------+-----------+-----------------------------+-----------+---------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * For example, pin B19 has a low-priority signal that's enabled by two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * distinct SoC functions: A specific SIOPBI bit in register SCUA4, and an ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * bit in the STRAP register. The ACPI bit configures signals on pins in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * addition to B19. Both of the low priority functions as well as the high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * priority function must be disabled for GPIOF1 to be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * B19 GPIOF1 NDCD4 SCU80[25]=1 SIOPBI# SCUA4[12]=1 | Strap[19]=0 GPIOF1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * For pin E18, the SoC ANDs the expected state of three bits to determine the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * pin's active signal:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * * SCU3C[3]: Enable external SOC reset function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * * SCU80[15]: Enable SPICS1# or EXTRST# function pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * * SCU90[31]: Select SPI interface CS# output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * E18 GPIOB7 EXTRST# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=0 SPICS1# SCU3C[3]=1 & SCU80[15]=1 & SCU90[31]=1 GPIOB7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * -----+---------+-----------+-----------------------------------------+-----------+----------------------------------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * (Bits SCU3C[3] and SCU80[15] appear to only be used in the expressions for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * selecting the signals on pin E18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * Pin T5 is a multi-signal pin with a more complex configuration:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * -----+---------+-----------+------------------------------+-----------+---------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * T5 GPIOL1 VPIDE SCU90[5:4]!=0 & SCU84[17]=1 NDCD1 SCU84[17]=1 GPIOL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * -----+---------+-----------+------------------------------+-----------+---------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * The high priority signal configuration is best thought of in terms of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * exploded form, with reference to the SCU90[5:4] bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * * SCU90[5:4]=00: disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * * SCU90[5:4]=01: 18 bits (R6/G6/B6) video mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * * SCU90[5:4]=10: 24 bits (R8/G8/B8) video mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * * SCU90[5:4]=11: 30 bits (R10/G10/B10) video mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Re-writing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * -----+---------+-----------+------------------------------+-----------+---------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * T5 GPIOL1 VPIDE (SCU90[5:4]=1 & SCU84[17]=1) NDCD1 SCU84[17]=1 GPIOL1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * | (SCU90[5:4]=2 & SCU84[17]=1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * | (SCU90[5:4]=3 & SCU84[17]=1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * -----+---------+-----------+------------------------------+-----------+---------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * For reference the SCU84[17] bit configure the "UART1 NDCD1 or Video VPIDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * function pin", where the signal itself is determined by whether SCU94[5:4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * is disabled or in one of the 18, 24 or 30bit video modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Other video-input-related pins require an explicit state in SCU90[5:4], e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * W1 and U5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * -----+---------+-----------+------------------------------+-----------+---------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * W1 GPIOL6 VPIB0 SCU90[5:4]=3 & SCU84[22]=1 TXD1 SCU84[22]=1 GPIOL6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * U5 GPIOL7 VPIB1 SCU90[5:4]=3 & SCU84[23]=1 RXD1 SCU84[23]=1 GPIOL7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * -----+---------+-----------+------------------------------+-----------+---------------+----------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * The examples of T5 and W1 are particularly fertile, as they also demonstrate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * that despite operating as part of the video input bus each signal needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * be enabled individually via it's own SCU84 (in the cases of T5 and W1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * register bit. This is a little crazy if the bus doesn't have optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * signals, but is used to decent effect with some of the UARTs where not all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * signals are required. However, this isn't done consistently - UART1 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * enabled on a per-pin basis, and by contrast, all signals for UART6 are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * enabled by a single bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Further, the high and low priority signals listed in the table above share
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * a configuration bit. The VPI signals should operate in concert in a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * function, but the UART signals should retain the ability to be configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * independently. This pushes the implementation down the path of tagging a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * signal's expressions with the function they participate in, rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * defining masks affecting multiple signals per function. The latter approach
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * fails in this instance where applying the configuration for the UART pin of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * interest will stomp on the state of other UART signals when disabling the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * VPI functions on the current pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Ball | Default | P0 Signal | P0 Expression | P1 Signal | P1 Expression | Other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * -----+------------+-----------+---------------------------+-----------+---------------+------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * A12 RGMII1TXCK GPIOT0 SCUA0[0]=1 RMII1TXEN Strap[6]=0 RGMII1TXCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * B12 RGMII1TXCTL GPIOT1 SCUA0[1]=1 – Strap[6]=0 RGMII1TXCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * -----+------------+-----------+---------------------------+-----------+---------------+------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * A12 demonstrates that the "Other" signal isn't always GPIO - in this case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * GPIOT0 is a high-priority signal and RGMII1TXCK is Other. Thus, GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * should be treated like any other signal type with full function expression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * requirements, and not assumed to be the default case. Separately, GPIOT0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * GPIOT1's signal descriptor bits are distinct, therefore we must iterate all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * pins in the function's group to disable the higher-priority signals such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * that the signal for the function of interest is correctly enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Finally, three priority levels aren't always enough; the AST2500 brings with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * it 18 pins of five priority levels, however the 18 pins only use three of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * the five priority levels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Ultimately the requirement to control pins in the examples above drive the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * design:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * * Pins provide signals according to functions activated in the mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * * Pins provide up to five signal types in a priority order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * * For priorities levels defined on a pin, each priority provides one signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * * Enabling lower priority signals requires higher priority signals be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * * A function represents a set of signals; functions are distinct if they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * do not share a subset of signals (and may be distinct if they are a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * strict subset).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * * Signals participate in one or more functions or groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * * A function is described by an expression of one or more signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * descriptors, which compare bit values in a register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * * A signal expression is the smallest set of signal descriptors whose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * comparisons must evaluate 'true' for a signal to be enabled on a pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * * A signal participating in a function is active on a pin if evaluating all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * signal descriptors in the pin's signal expression for the function yields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * a 'true' result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * * A signal at a given priority on a given pin is active if any of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * functions in which the signal participates are active, and no higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * priority signal on the pin is active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * * GPIO is configured per-pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * And so:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * * To disable a signal, any function(s) activating the signal must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * * Each pin must know the signal expressions of functions in which it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * participates, for the purpose of enabling the Other function. This is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * by deactivating all functions that activate higher priority signals on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * As a concrete example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * * T5 provides three signals types: VPIDE, NDCD1 and GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * * The VPIDE signal participates in 3 functions: VPI18, VPI24 and VPI30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * * The NDCD1 signal participates in just its own NDCD1 function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * * VPIDE is high priority, NDCD1 is low priority, and GPIOL1 is the least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * prioritised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * * The prerequisit for activating the NDCD1 signal is that the VPI18, VPI24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * and VPI30 functions all be disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * * Similarly, all of VPI18, VPI24, VPI30 and NDCD1 functions must be disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * to provide GPIOL6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Considerations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * --------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * If pinctrl allows us to allocate a pin we can configure a function without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * concern for the function of already allocated pins, if pin groups are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * created with respect to the SoC functions in which they participate. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * intuitive, but it did not feel obvious from the bit/pin relationships.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Conversely, failing to allocate all pins in a group indicates some bits (as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * well as pins) required for the group's configuration will already be in use,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * likely in a way that's inconsistent with the requirements of the failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * --------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Beyond the documentation below the various structures and helper macros that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * allow the implementation to hang together are defined. The macros are fairly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * dense, so below we walk through some raw examples of the configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * tables in an effort to clarify the concepts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * The complexity of configuring the mux combined with the scale of the pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * and functions was a concern, so the table design along with the macro jungle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * is an attempt to address it. The rough principles of the approach are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * 1. Use a data-driven solution rather than embedding state into code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * 2. Minimise editing to the specifics of the given mux configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * 3. Detect as many errors as possible at compile time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * Addressing point 3 leads to naming of symbols in terms of the four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * properties associated with a given mux configuration: The pin, the signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * the group and the function. In this way copy/paste errors cause duplicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * symbols to be defined, which prevents successful compilation. Failing to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * properly parent the tables leads to unused symbol warnings, and use of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * designated initialisers and additional warnings ensures that there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * no override errors in the pin, group and function arrays.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * Addressing point 2 drives the development of the macro jungle, as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * centralises the definition noise at the cost of taking some time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * understand.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * Here's a complete, concrete "pre-processed" example of the table structures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * used to describe the D6 ball from the examples above:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * ```
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * static const struct aspeed_sig_desc sig_descs_MAC1LINK_MAC1LINK[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * .ip = ASPEED_IP_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * .reg = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * .mask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * .enable = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * .disable = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * static const struct aspeed_sig_expr sig_expr_MAC1LINK_MAC1LINK = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * .signal = "MAC1LINK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * .function = "MAC1LINK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * .ndescs = ARRAY_SIZE(sig_descs_MAC1LINK_MAC1LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * .descs = &(sig_descs_MAC1LINK_MAC1LINK)[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * static const struct aspeed_sig_expr *sig_exprs_MAC1LINK_MAC1LINK[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * &sig_expr_MAC1LINK_MAC1LINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * static const struct aspeed_sig_desc sig_descs_GPIOA0_GPIOA0[] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * static const struct aspeed_sig_expr sig_expr_GPIOA0_GPIOA0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * .signal = "GPIOA0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * .function = "GPIOA0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * .ndescs = ARRAY_SIZE(sig_descs_GPIOA0_GPIOA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * .descs = &(sig_descs_GPIOA0_GPIOA0)[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * static const struct aspeed_sig_expr *sig_exprs_GPIOA0_GPIOA0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * &sig_expr_GPIOA0_GPIOA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * static const struct aspeed_sig_expr **pin_exprs_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * sig_exprs_MAC1LINK_MAC1LINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * sig_exprs_GPIOA0_GPIOA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * static const struct aspeed_pin_desc pin_0 = { "0", (&pin_exprs_0[0]) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * static const int group_pins_MAC1LINK[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * static const char *func_groups_MAC1LINK[] = { "MAC1LINK" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * static struct pinctrl_pin_desc aspeed_g4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * [0] = { .number = 0, .name = "D6", .drv_data = &pin_0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * static const struct aspeed_pin_group aspeed_g4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * .name = "MAC1LINK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * .pins = &(group_pins_MAC1LINK)[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * .npins = ARRAY_SIZE(group_pins_MAC1LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * static const struct aspeed_pin_function aspeed_g4_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * .name = "MAC1LINK",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * .groups = &func_groups_MAC1LINK[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * .ngroups = ARRAY_SIZE(func_groups_MAC1LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * ```
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * At the end of the day much of the above code is compressed into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * following two lines:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * ```
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * #define D6 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * ```
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * The two examples below show just the differences from the example above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Ball E18 demonstrates a function, EXTRST, that requires multiple descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * be set for it to be muxed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * ```
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * static const struct aspeed_sig_desc sig_descs_EXTRST_EXTRST[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * .ip = ASPEED_IP_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * .reg = 0x3C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * .mask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * .enable = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * .disable = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * .ip = ASPEED_IP_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * .reg = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * .mask = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * .enable = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * .disable = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * .ip = ASPEED_IP_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * .reg = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * .mask = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * .enable = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * .disable = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * static const struct aspeed_sig_expr sig_expr_EXTRST_EXTRST = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * .signal = "EXTRST",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * .function = "EXTRST",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * .ndescs = ARRAY_SIZE(sig_descs_EXTRST_EXTRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * .descs = &(sig_descs_EXTRST_EXTRST)[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * ```
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * For ball E19, we have multiple functions enabling a single signal, LPCRST#.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * The data structures look like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRST[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * .ip = ASPEED_IP_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * .reg = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * .mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * .enable = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * .disable = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRST = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * .signal = "LPCRST",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * .function = "LPCRST",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * .descs = &(sig_descs_LPCRST_LPCRST)[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * static const struct aspeed_sig_desc sig_descs_LPCRST_LPCRSTS[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * .ip = ASPEED_IP_SCU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * .reg = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * .mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * .enable = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * .disable = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * static const struct aspeed_sig_expr sig_expr_LPCRST_LPCRSTS = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * .signal = "LPCRST",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * .function = "LPCRSTS",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * .ndescs = ARRAY_SIZE(sig_descs_LPCRST_LPCRSTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * .descs = &(sig_descs_LPCRST_LPCRSTS)[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * static const struct aspeed_sig_expr *sig_exprs_LPCRST_LPCRST[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * &sig_expr_LPCRST_LPCRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * &sig_expr_LPCRST_LPCRSTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * ```
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * Both expressions listed in the sig_exprs_LPCRST_LPCRST array need to be set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * to disabled for the associated GPIO to be muxed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define ASPEED_IP_SCU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define ASPEED_IP_GFX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define ASPEED_IP_LPC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define ASPEED_NR_PINMUX_IPS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * A signal descriptor, which describes the register, bits and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * enable/disable values that should be compared or written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * @ip: The IP block identifier, used as an index into the regmap array in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * struct aspeed_pinctrl_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * @reg: The register offset with respect to the base address of the IP block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * @mask: The mask to apply to the register. The lowest set bit of the mask is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * used to derive the shift value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @enable: The value that enables the function. Value should be in the LSBs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * not at the position of the mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * @disable: The value that disables the function. Value should be in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * LSBs, not at the position of the mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct aspeed_sig_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Describes a signal expression. The expression is evaluated by ANDing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * evaluation of the descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * @signal: The signal name for the priority level on the pin. If the signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * type is GPIO, then the signal name must begin with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * prefix "GPI", e.g. GPIOA0, GPIT0 etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * @function: The name of the function the signal participates in for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * associated expression. For pin-specific GPIO, the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * name must match the signal name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * @ndescs: The number of signal descriptors in the expression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * @descs: Pointer to an array of signal descriptors that comprise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * function expression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct aspeed_sig_expr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) const char *signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) const char *function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) int ndescs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) const struct aspeed_sig_desc *descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * A struct capturing the list of expressions enabling signals at each priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * for a given pin. The signal configuration for a priority level is evaluated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * by ORing the evaluation of the signal expressions in the respective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * priority's list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @name: A name for the pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * @prios: A pointer to an array of expression list pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct aspeed_pin_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) const struct aspeed_sig_expr ***prios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* Macro hell */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define SIG_DESC_IP_BIT(ip, reg, idx, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * Short-hand macro for describing an SCU descriptor enabled by the state of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * one bit. The disable value is derived.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * @reg: The signal's associated register, offset from base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * @idx: The signal's bit index in the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * @val: The value (0 or 1) that enables the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SIG_DESC_BIT(reg, idx, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * A further short-hand macro expanding to an SCU descriptor enabled by a set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * @reg: The register, offset from base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * @idx: The bit index in the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define SIG_DESC_CLEAR(reg, idx) { ASPEED_IP_SCU, reg, BIT_MASK(idx), 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define SIG_DESC_LIST_DECL(sig, group, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, group)[] = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) { __VA_ARGS__ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SIG_EXPR_SYM(sig, group) sig_expr_ ## sig ## _ ## group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SIG_EXPR_DECL_(sig, group, func) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, group) = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .signal = #sig, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .function = #func, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, group)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .descs = &(SIG_DESC_LIST_SYM(sig, group))[0], \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * Declare a signal expression.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * @sig: A macro symbol name for the signal (is subjected to stringification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * and token pasting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * @func: The function in which the signal is participating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * @...: Signal descriptors that define the signal expression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * For example, the following declares the ROMD8 signal for the ROM16 function:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * And with multiple signal descriptors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SIG_EXPR_DECL(sig, group, func, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) SIG_EXPR_DECL_(sig, group, func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * Declare a pointer to a signal expression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * @sig: The macro symbol name for the signal (subjected to token pasting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * @func: The macro symbol name for the function (subjected to token pasting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SIG_EXPR_PTR(sig, group) (&SIG_EXPR_SYM(sig, group))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define SIG_EXPR_LIST_SYM(sig, group) sig_exprs_ ## sig ## _ ## group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * Declare a signal expression list for reference in a struct aspeed_pin_prio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * @sig: A macro symbol name for the signal (is subjected to token pasting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * @...: Signal expression structure pointers (use SIG_EXPR_PTR())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * For example, the 16-bit ROM bus can be enabled by one of two possible signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * expressions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * SIG_EXPR_PTR(ROMD8, ROM16S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SIG_EXPR_LIST_DECL(sig, group, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig, group)[] =\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { __VA_ARGS__, NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define stringify(x) #x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define istringify(x) stringify(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * Create an expression symbol alias from (signal, group) to (pin, signal).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * @pin: The pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * @sig: The signal name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * @group: The name of the group of which the pin is a member that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * associated with the function's signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * Using an alias in this way enables detection of copy/paste errors (defining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * the signal for a group multiple times) whilst enabling multiple pin groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * to exist for a signal without intrusive side-effects on defining the list of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * signals available on a pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define SIG_EXPR_LIST_ALIAS(pin, sig, group) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const struct aspeed_sig_expr *\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) SIG_EXPR_LIST_SYM(pin, sig)[ARRAY_SIZE(SIG_EXPR_LIST_SYM(sig, group))] \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) __attribute__((alias(istringify(SIG_EXPR_LIST_SYM(sig, group)))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * A short-hand macro for declaring a function expression and an expression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * list with a single expression (SE) and a single group (SG) of pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * @pin: The pin the signal will be routed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * @sig: The signal that will be routed to the pin for the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * @func: A macro symbol name for the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * @...: Function descriptors that define the function expression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * For example, signal NCTS6 participates in its own function with one group:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define SIG_EXPR_LIST_DECL_SESG(pin, sig, func, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) SIG_EXPR_DECL_(sig, func, func); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) SIG_EXPR_LIST_DECL(sig, func, SIG_EXPR_PTR(sig, func)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) SIG_EXPR_LIST_ALIAS(pin, sig, func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * Similar to the above, but for pins with a single expression (SE) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * multiple groups (MG) of pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * @pin: The pin the signal will be routed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * @sig: The signal that will be routed to the pin for the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * @group: The name of the function's pin group in which the pin participates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * @func: A macro symbol name for the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * @...: Function descriptors that define the function expression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define SIG_EXPR_LIST_DECL_SEMG(pin, sig, group, func, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) SIG_EXPR_DECL_(sig, group, func); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) SIG_EXPR_LIST_DECL(sig, group, SIG_EXPR_PTR(sig, group)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) SIG_EXPR_LIST_ALIAS(pin, sig, group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * Similar to the above, but for pins with a dual expressions (DE) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * and a single group (SG) of pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * @pin: The pin the signal will be routed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * @sig: The signal that will be routed to the pin for the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * @group: The name of the function's pin group in which the pin participates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * @func: A macro symbol name for the function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * @...: Function descriptors that define the function expression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define SIG_EXPR_LIST_DECL_DESG(pin, sig, f0, f1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) SIG_EXPR_LIST_DECL(sig, f0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) SIG_EXPR_PTR(sig, f0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) SIG_EXPR_PTR(sig, f1)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) SIG_EXPR_LIST_ALIAS(pin, sig, f0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define SIG_EXPR_LIST_PTR(sig, group) SIG_EXPR_LIST_SYM(sig, group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define PIN_SYM(pin) pin_ ## pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define PIN_DECL_(pin, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) { __VA_ARGS__, NULL }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const struct aspeed_pin_desc PIN_SYM(pin) = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { #pin, PIN_EXPRS_PTR(pin) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * Declare a single signal pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * @pin: The pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * @other: Macro name for "other" functionality (subjected to stringification)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * @sig: Macro name for the signal (subjected to stringification)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * For example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * #define E3 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * PIN_DECL_1(E3, GPIOK0, SCL5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define PIN_DECL_1(pin, other, sig) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) SIG_EXPR_LIST_PTR(pin, other))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * Single signal, single function pin declaration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * @pin: The pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * @other: Macro name for "other" functionality (subjected to stringification)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * @sig: Macro name for the signal (subjected to stringification)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * @...: Signal descriptors that define the function expression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * For example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define SSSF_PIN_DECL(pin, other, sig, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) SIG_EXPR_LIST_DECL_SESG(pin, sig, sig, __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) SIG_EXPR_LIST_PTR(pin, other)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) FUNC_GROUP_DECL(sig, pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * Declare a two-signal pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * @pin: The pin number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * @other: Macro name for "other" functionality (subjected to stringification)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * @high: Macro name for the highest priority signal functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * @low: Macro name for the low signal functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * For example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * #define A8 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * { HW_STRAP1, GENMASK(1, 0), 0, 0 });
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * SIG_EXPR_PTR(ROMD8, ROM16S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define PIN_DECL_2(pin, other, high, low) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PIN_DECL_(pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) SIG_EXPR_LIST_PTR(pin, high), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) SIG_EXPR_LIST_PTR(pin, low), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) SIG_EXPR_LIST_PTR(pin, other))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define PIN_DECL_3(pin, other, high, medium, low) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) SIG_EXPR_LIST_DECL_SESG(pin, other, other); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PIN_DECL_(pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) SIG_EXPR_LIST_PTR(pin, high), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) SIG_EXPR_LIST_PTR(pin, medium), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) SIG_EXPR_LIST_PTR(pin, low), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) SIG_EXPR_LIST_PTR(pin, other))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define GROUP_SYM(group) group_pins_ ## group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define GROUP_DECL(group, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const int GROUP_SYM(group)[] = { __VA_ARGS__ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define FUNC_SYM(func) func_groups_ ## func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define FUNC_DECL_(func, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const char *FUNC_SYM(func)[] = { __VA_ARGS__ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define FUNC_DECL_1(func, group) FUNC_DECL_(func, #group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define FUNC_GROUP_DECL(func, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) GROUP_DECL(func, __VA_ARGS__); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) FUNC_DECL_(func, #func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define GPIO_PIN_DECL(pin, gpio) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) SIG_EXPR_LIST_DECL_SESG(pin, gpio, gpio); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct aspeed_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) const unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define ASPEED_PINCTRL_GROUP(name_) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .name = #name_, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .pins = &(GROUP_SYM(name_))[0], \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .npins = ARRAY_SIZE(GROUP_SYM(name_)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct aspeed_pin_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) const char *const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define ASPEED_PINCTRL_FUNC(name_, ...) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .name = #name_, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .groups = &FUNC_SYM(name_)[0], \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .ngroups = ARRAY_SIZE(FUNC_SYM(name_)), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct aspeed_pinmux_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct aspeed_pinmux_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int (*eval)(struct aspeed_pinmux_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) const struct aspeed_sig_expr *expr, bool enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int (*set)(struct aspeed_pinmux_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) const struct aspeed_sig_expr *expr, bool enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct aspeed_pinmux_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct regmap *maps[ASPEED_NR_PINMUX_IPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) const struct aspeed_pinmux_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) const struct aspeed_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) const unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) const struct aspeed_pin_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) const unsigned int nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc, bool enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct regmap *map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int aspeed_sig_expr_eval(struct aspeed_pinmux_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) const struct aspeed_sig_expr *expr, bool enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static inline int aspeed_sig_expr_set(struct aspeed_pinmux_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) const struct aspeed_sig_expr *expr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) bool enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return ctx->ops->set(ctx, expr, enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #endif /* ASPEED_PINMUX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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