^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef PINCTRL_ASPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define PINCTRL_ASPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pinmux-aspeed.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * @param The pinconf parameter type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * @pins The pin range this config struct covers, [low, high]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * @reg The register housing the configuration bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * @mask The mask to select the bits of interest in @reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct aspeed_pin_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) unsigned int pins[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ASPEED_PINCTRL_PIN(name_) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) [name_] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .number = name_, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .name = #name_, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .drv_data = (void *) &(PIN_SYM(name_)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ASPEED_SB_PINCONF(param_, pin0_, pin1_, reg_, bit_) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .param = param_, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .pins = {pin0_, pin1_}, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .reg = reg_, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .mask = BIT_MASK(bit_) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Aspeed pin configuration description.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @param: pinconf configuration parameter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @arg: The supported argument for @param, or -1 if any value is supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @val: The register value to write to configure @arg for @param
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @mask: The bitfield mask for @val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * The map is to be used in conjunction with the configuration array supplied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * by the driver implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct aspeed_pin_config_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) s32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct aspeed_pinctrl_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct regmap *scu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const struct aspeed_pin_config *configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const unsigned int nconfigs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct aspeed_pinmux_data pinmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const struct aspeed_pin_config_map *confmaps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const unsigned int nconfmaps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Aspeed pinctrl helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int group, const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int *npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct seq_file *s, unsigned int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int function, const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int * const num_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int aspeed_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct pinctrl_desc *pdesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct aspeed_pinctrl_data *pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long *configs, unsigned int num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long *config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif /* PINCTRL_ASPEED */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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