^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "pinctrl-aspeed.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) return pdata->pinmux.ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) return pdata->pinmux.groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int group, const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int *npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *pins = &pdata->pinmux.groups[group].pins[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *npins = pdata->pinmux.groups[group].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct seq_file *s, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) seq_printf(s, " %s", dev_name(pctldev->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return pdata->pinmux.nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned int function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return pdata->pinmux.functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *groups = pdata->pinmux.functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *num_groups = pdata->pinmux.functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int aspeed_sig_expr_enable(struct aspeed_pinmux_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const struct aspeed_sig_expr *expr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) pr_debug("Enabling signal %s for %s\n", expr->signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) expr->function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = aspeed_sig_expr_eval(ctx, expr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return aspeed_sig_expr_set(ctx, expr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int aspeed_sig_expr_disable(struct aspeed_pinmux_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const struct aspeed_sig_expr *expr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pr_debug("Disabling signal %s for %s\n", expr->signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) expr->function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = aspeed_sig_expr_eval(ctx, expr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return aspeed_sig_expr_set(ctx, expr, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Disable a signal on a pin by disabling all provided signal expressions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @ctx: The pinmux context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @exprs: The list of signal expressions (from a priority level on a pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Return: 0 if all expressions are disabled, otherwise a negative error code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int aspeed_disable_sig(struct aspeed_pinmux_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const struct aspeed_sig_expr **exprs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (!exprs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) while (*exprs && !ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = aspeed_sig_expr_disable(ctx, *exprs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) exprs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Search for the signal expression needed to enable the pin's signal for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * requested function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @exprs: List of signal expressions (haystack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @name: The name of the requested function (needle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Return: A pointer to the signal expression whose function tag matches the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * provided name, otherwise NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct aspeed_sig_expr *aspeed_find_expr_by_name(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) const struct aspeed_sig_expr **exprs, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) while (*exprs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (strcmp((*exprs)->function, name) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return *exprs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) exprs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static char *get_defined_attribute(const struct aspeed_pin_desc *pdesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) const char *(*get)(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const struct aspeed_sig_expr *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) char *found = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) size_t len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) const struct aspeed_sig_expr ***prios, **funcs, *expr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) prios = pdesc->prios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) while ((funcs = *prios)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) while ((expr = *funcs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const char *str = get(expr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) size_t delta = strlen(str) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) char *expanded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) expanded = krealloc(found, len + delta + 1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!expanded) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) kfree(found);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return expanded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) found = expanded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) found[len] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) len += delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) strcat(found, str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) strcat(found, ", ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) funcs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) prios++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (len < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) kfree(found);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) found[len - 2] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const char *aspeed_sig_expr_function(const struct aspeed_sig_expr *expr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return expr->function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static char *get_defined_functions(const struct aspeed_pin_desc *pdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return get_defined_attribute(pdesc, aspeed_sig_expr_function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const char *aspeed_sig_expr_signal(const struct aspeed_sig_expr *expr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return expr->signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static char *get_defined_signals(const struct aspeed_pin_desc *pdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return get_defined_attribute(pdesc, aspeed_sig_expr_signal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) const struct aspeed_pin_group *pgroup = &pdata->pinmux.groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) const struct aspeed_pin_function *pfunc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) &pdata->pinmux.functions[function];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (i = 0; i < pgroup->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int pin = pgroup->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) const struct aspeed_pin_desc *pdesc = pdata->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) const struct aspeed_sig_expr *expr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) const struct aspeed_sig_expr **funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) const struct aspeed_sig_expr ***prios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pr_debug("Muxing pin %s for %s\n", pdesc->name, pfunc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!pdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) prios = pdesc->prios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!prios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Disable functions at a higher priority than that requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) while ((funcs = *prios)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) expr = aspeed_find_expr_by_name(funcs, pfunc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (expr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = aspeed_disable_sig(&pdata->pinmux, funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) prios++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!expr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) char *functions = get_defined_functions(pdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) char *signals = get_defined_signals(pdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pr_warn("No function %s found on pin %s (%d). Found signal(s) %s for function(s) %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pfunc->name, pdesc->name, pin, signals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) kfree(signals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) kfree(functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = aspeed_sig_expr_enable(&pdata->pinmux, expr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pr_debug("Muxed pin %s as %s for %s\n", pdesc->name, expr->signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) expr->function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static bool aspeed_expr_is_gpio(const struct aspeed_sig_expr *expr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * We need to differentiate between GPIO and non-GPIO signals to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * implement the gpio_request_enable() interface. For better or worse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * the ASPEED pinctrl driver uses the expression names to determine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * whether an expression will mux a pin for GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Generally we have the following - A GPIO such as B1 has:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * - expr->signal set to "GPIOB1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * - expr->function set to "GPIOB1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Using this fact we can determine whether the provided expression is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * a GPIO expression by testing the signal name for the string prefix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * "GPIO".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * However, some GPIOs are input-only, and the ASPEED datasheets name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * them differently. An input-only GPIO such as T0 has:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * - expr->signal set to "GPIT0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * - expr->function set to "GPIT0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * It's tempting to generalise the prefix test from "GPIO" to "GPI" to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * account for both GPIOs and GPIs, but in doing so we run aground on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * another feature:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Some pins in the ASPEED BMC SoCs have a "pass-through" GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * function where the input state of one pin is replicated as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * output state of another (as if they were shorted together - a mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * configuration that is typically enabled by hardware strapping).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * This feature allows the BMC to pass e.g. power button state through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * to the host while the BMC is yet to boot, but take control of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * button state once the BMC has booted by muxing each pin as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * separate, pin-specific GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Conceptually this pass-through mode is a form of GPIO and is named
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * as such in the datasheets, e.g. "GPID0". This naming similarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * trips us up with the simple GPI-prefixed-signal-name scheme
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * discussed above, as the pass-through configuration is not what we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * want when muxing a pin as GPIO for the GPIO subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * On e.g. the AST2400, a pass-through function "GPID0" is grouped on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * balls A18 and D16, where we have:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * For ball A18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * - expr->signal set to "GPID0IN"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * - expr->function set to "GPID0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * For ball D16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * - expr->signal set to "GPID0OUT"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * - expr->function set to "GPID0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * By contrast, the pin-specific GPIO expressions for the same pins are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * For ball A18:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * - expr->signal looks like "GPIOD0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * - expr->function looks like "GPIOD0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * For ball D16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * - expr->signal looks like "GPIOD1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * - expr->function looks like "GPIOD1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Testing both the signal _and_ function names gives us the means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * differentiate the pass-through GPIO pinmux configuration from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * pin-specific configuration that the GPIO subsystem is after: An
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * expression is a pin-specific (non-pass-through) GPIO configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * if the signal prefix is "GPI" and the signal name matches the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * function name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return !strncmp(expr->signal, "GPI", 3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) !strcmp(expr->signal, expr->function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static bool aspeed_gpio_in_exprs(const struct aspeed_sig_expr **exprs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!exprs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) while (*exprs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (aspeed_expr_is_gpio(*exprs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) exprs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) const struct aspeed_sig_expr ***prios, **funcs, *expr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!pdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) prios = pdesc->prios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!prios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pr_debug("Muxing pin %s for GPIO\n", pdesc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Disable any functions of higher priority than GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) while ((funcs = *prios)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (aspeed_gpio_in_exprs(funcs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret = aspeed_disable_sig(&pdata->pinmux, funcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) prios++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!funcs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) char *signals = get_defined_signals(pdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pr_warn("No GPIO signal type found on pin %s (%d). Found: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pdesc->name, offset, signals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) kfree(signals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) expr = *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * Disabling all higher-priority expressions is enough to enable the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * lowest-priority signal type. As such it has no associated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * expression.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!expr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pr_debug("Muxed pin %s as GPIO\n", pdesc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * If GPIO is not the lowest priority signal type, assume there is only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * one expression defined to enable the GPIO function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = aspeed_sig_expr_enable(&pdata->pinmux, expr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pr_debug("Muxed pin %s as %s\n", pdesc->name, expr->signal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int aspeed_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct pinctrl_desc *pdesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct aspeed_pinctrl_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct device *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) parent = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(&pdev->dev, "No parent for syscon pincontroller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pdata->scu = syscon_node_to_regmap(parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (IS_ERR(pdata->scu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev_err(&pdev->dev, "No regmap for syscon pincontroller parent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return PTR_ERR(pdata->scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pdata->pinmux.maps[ASPEED_IP_SCU] = pdata->scu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pctl = pinctrl_register(pdesc, &pdev->dev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (IS_ERR(pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dev_err(&pdev->dev, "Failed to register pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return PTR_ERR(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) platform_set_drvdata(pdev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static inline bool pin_in_config_range(unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) const struct aspeed_pin_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return offset >= config->pins[0] && offset <= config->pins[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static inline const struct aspeed_pin_config *find_pinconf_config(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) const struct aspeed_pinctrl_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) enum pin_config_param param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) for (i = 0; i < pdata->nconfigs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (param == pdata->configs[i].param &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pin_in_config_range(offset, &pdata->configs[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return &pdata->configs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) enum aspeed_pin_config_map_type { MAP_TYPE_ARG, MAP_TYPE_VAL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const struct aspeed_pin_config_map *find_pinconf_map(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) const struct aspeed_pinctrl_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) enum pin_config_param param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) enum aspeed_pin_config_map_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) s64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) for (i = 0; i < pdata->nconfmaps; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) const struct aspeed_pin_config_map *elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) bool match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) elem = &pdata->confmaps[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case MAP_TYPE_ARG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) match = (elem->arg == -1 || elem->arg == value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case MAP_TYPE_VAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) match = (elem->val == value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (param == elem->param && match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return elem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) const enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) const struct aspeed_pin_config_map *pmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) const struct aspeed_pinctrl_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) const struct aspeed_pin_config *pconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pconf = find_pinconf_config(pdata, offset, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (!pconf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) rc = regmap_read(pdata->scu, pconf->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) pmap = find_pinconf_map(pdata, param, MAP_TYPE_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) (val & pconf->mask) >> __ffs(pconf->mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (!pmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (param == PIN_CONFIG_DRIVE_STRENGTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) arg = (u32) pmap->arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) arg = !!pmap->arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) const struct aspeed_pinctrl_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) pdata = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) const struct aspeed_pin_config_map *pmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) const struct aspeed_pin_config *pconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pconf = find_pinconf_config(pdata, offset, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!pconf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pmap = find_pinconf_map(pdata, param, MAP_TYPE_ARG, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (WARN_ON(!pmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) val = pmap->val << __ffs(pconf->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) rc = regmap_update_bits(pdata->scu, pconf->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) pconf->mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) pr_debug("%s: Set SCU%02X[0x%08X]=0x%X for param %d(=%d) on pin %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) __func__, pconf->reg, pconf->mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) val, param, arg, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) rc = aspeed_pinctrl_get_group_pins(pctldev, selector, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) rc = aspeed_pin_config_get(pctldev, pins[0], config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pr_debug("%s: Fetching pins for group selector %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) __func__, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) rc = aspeed_pinctrl_get_group_pins(pctldev, selector, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) rc = aspeed_pin_config_set(pctldev, pins[i], configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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