^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (C) 2019 IBM Corp. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "pinctrl-aspeed.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SCU400 0x400 /* Multi-function Pin Control #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SCU404 0x404 /* Multi-function Pin Control #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SCU40C 0x40C /* Multi-function Pin Control #3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SCU410 0x410 /* Multi-function Pin Control #4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SCU414 0x414 /* Multi-function Pin Control #5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SCU418 0x418 /* Multi-function Pin Control #6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SCU41C 0x41C /* Multi-function Pin Control #7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SCU430 0x430 /* Multi-function Pin Control #8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SCU434 0x434 /* Multi-function Pin Control #9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SCU438 0x438 /* Multi-function Pin Control #10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SCU440 0x440 /* USB Multi-function Pin Control #12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SCU450 0x450 /* Multi-function Pin Control #14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCU454 0x454 /* Multi-function Pin Control #15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCU458 0x458 /* Multi-function Pin Control #16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCU4BC 0x4BC /* Multi-function Pin Control #20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCU4D4 0x4D4 /* Multi-function Pin Control #22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCU500 0x500 /* Hardware Strap 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCU510 0x510 /* Hardware Strap 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCU610 0x610 /* Disable GPIO Internal Pull-Down #0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SCU694 0x694 /* Multi-function Pin Control #25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SCU69C 0x69C /* Multi-function Pin Control #27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SCUC20 0xC20 /* PCIE configuration Setting Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ASPEED_G6_NR_PINS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define M24 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) SIG_EXPR_LIST_DECL_SESG(M24, SCL11, I2C11, SIG_DESC_SET(SCU4B0, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PIN_DECL_2(M24, GPIOA0, MDC3, SCL11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define M25 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) SIG_EXPR_LIST_DECL_SESG(M25, MDIO3, MDIO3, SIG_DESC_SET(SCU410, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) SIG_EXPR_LIST_DECL_SESG(M25, SDA11, I2C11, SIG_DESC_SET(SCU4B0, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PIN_DECL_2(M25, GPIOA1, MDIO3, SDA11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FUNC_GROUP_DECL(MDIO3, M24, M25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FUNC_GROUP_DECL(I2C11, M24, M25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define L26 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SIG_EXPR_LIST_DECL_SESG(L26, MDC4, MDIO4, SIG_DESC_SET(SCU410, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SIG_EXPR_LIST_DECL_SESG(L26, SCL12, I2C12, SIG_DESC_SET(SCU4B0, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PIN_DECL_2(L26, GPIOA2, MDC4, SCL12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define K24 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SIG_EXPR_LIST_DECL_SESG(K24, MDIO4, MDIO4, SIG_DESC_SET(SCU410, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SIG_EXPR_LIST_DECL_SESG(K24, SDA12, I2C12, SIG_DESC_SET(SCU4B0, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PIN_DECL_2(K24, GPIOA3, MDIO4, SDA12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FUNC_GROUP_DECL(MDIO4, L26, K24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FUNC_GROUP_DECL(I2C12, L26, K24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define K26 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SIG_EXPR_LIST_DECL_SESG(K26, MACLINK1, MACLINK1, SIG_DESC_SET(SCU410, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SIG_EXPR_LIST_DECL_SESG(K26, SCL13, I2C13, SIG_DESC_SET(SCU4B0, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PIN_DECL_2(K26, GPIOA4, MACLINK1, SCL13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FUNC_GROUP_DECL(MACLINK1, K26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define L24 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SIG_EXPR_LIST_DECL_SESG(L24, MACLINK2, MACLINK2, SIG_DESC_SET(SCU410, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SIG_EXPR_LIST_DECL_SESG(L24, SDA13, I2C13, SIG_DESC_SET(SCU4B0, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PIN_DECL_2(L24, GPIOA5, MACLINK2, SDA13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FUNC_GROUP_DECL(MACLINK2, L24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FUNC_GROUP_DECL(I2C13, K26, L24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define L23 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SIG_EXPR_LIST_DECL_SESG(L23, MACLINK3, MACLINK3, SIG_DESC_SET(SCU410, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SIG_EXPR_LIST_DECL_SESG(L23, SCL14, I2C14, SIG_DESC_SET(SCU4B0, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PIN_DECL_2(L23, GPIOA6, MACLINK3, SCL14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) FUNC_GROUP_DECL(MACLINK3, L23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define K25 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SIG_EXPR_LIST_DECL_SESG(K25, SDA14, I2C14, SIG_DESC_SET(SCU4B0, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PIN_DECL_2(K25, GPIOA7, MACLINK4, SDA14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) FUNC_GROUP_DECL(MACLINK4, K25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FUNC_GROUP_DECL(I2C14, L23, K25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define J26 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SIG_EXPR_LIST_DECL_SESG(J26, SALT1, SALT1, SIG_DESC_SET(SCU410, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SIG_EXPR_LIST_DECL_SESG(J26, LHAD0, LPCHC, SIG_DESC_SET(SCU4B0, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PIN_DECL_2(J26, GPIOB0, SALT1, LHAD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FUNC_GROUP_DECL(SALT1, J26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define K23 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) SIG_EXPR_LIST_DECL_SESG(K23, SALT2, SALT2, SIG_DESC_SET(SCU410, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SIG_EXPR_LIST_DECL_SESG(K23, LHAD1, LPCHC, SIG_DESC_SET(SCU4B0, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PIN_DECL_2(K23, GPIOB1, SALT2, LHAD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FUNC_GROUP_DECL(SALT2, K23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define H26 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SIG_EXPR_LIST_DECL_SESG(H26, SALT3, SALT3, SIG_DESC_SET(SCU410, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SIG_EXPR_LIST_DECL_SESG(H26, LHAD2, LPCHC, SIG_DESC_SET(SCU4B0, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PIN_DECL_2(H26, GPIOB2, SALT3, LHAD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) FUNC_GROUP_DECL(SALT3, H26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define J25 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SIG_EXPR_LIST_DECL_SESG(J25, SALT4, SALT4, SIG_DESC_SET(SCU410, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SIG_EXPR_LIST_DECL_SESG(J25, LHAD3, LPCHC, SIG_DESC_SET(SCU4B0, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PIN_DECL_2(J25, GPIOB3, SALT4, LHAD3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) FUNC_GROUP_DECL(SALT4, J25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define J23 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SIG_EXPR_LIST_DECL_SESG(J23, MDC2, MDIO2, SIG_DESC_SET(SCU410, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SIG_EXPR_LIST_DECL_SESG(J23, LHCLK, LPCHC, SIG_DESC_SET(SCU4B0, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PIN_DECL_2(J23, GPIOB4, MDC2, LHCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define G26 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) SIG_EXPR_LIST_DECL_SESG(G26, MDIO2, MDIO2, SIG_DESC_SET(SCU410, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SIG_EXPR_LIST_DECL_SESG(G26, LHFRAME, LPCHC, SIG_DESC_SET(SCU4B0, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PIN_DECL_2(G26, GPIOB5, MDIO2, LHFRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FUNC_GROUP_DECL(MDIO2, J23, G26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define H25 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SIG_EXPR_LIST_DECL_SESG(H25, TXD4, TXD4, SIG_DESC_SET(SCU410, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) SIG_EXPR_LIST_DECL_SESG(H25, LHSIRQ, LHSIRQ, SIG_DESC_SET(SCU4B0, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PIN_DECL_2(H25, GPIOB6, TXD4, LHSIRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FUNC_GROUP_DECL(TXD4, H25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FUNC_GROUP_DECL(LHSIRQ, H25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define J24 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SIG_EXPR_LIST_DECL_SESG(J24, RXD4, RXD4, SIG_DESC_SET(SCU410, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SIG_EXPR_LIST_DECL_SESG(J24, LHRST, LPCHC, SIG_DESC_SET(SCU4B0, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PIN_DECL_2(J24, GPIOB7, RXD4, LHRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) FUNC_GROUP_DECL(RXD4, J24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) FUNC_GROUP_DECL(LPCHC, J26, K23, H26, J25, J23, G26, H25, J24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define H24 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SIG_EXPR_LIST_DECL_SESG(H24, RGMII3TXCK, RGMII3, SIG_DESC_SET(SCU410, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SIG_DESC_SET(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SIG_EXPR_LIST_DECL_SESG(H24, RMII3RCLKO, RMII3, SIG_DESC_SET(SCU410, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SIG_DESC_CLEAR(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PIN_DECL_2(H24, GPIOC0, RGMII3TXCK, RMII3RCLKO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define J22 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SIG_EXPR_LIST_DECL_SESG(J22, RGMII3TXCTL, RGMII3, SIG_DESC_SET(SCU410, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SIG_DESC_SET(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SIG_EXPR_LIST_DECL_SESG(J22, RMII3TXEN, RMII3, SIG_DESC_SET(SCU410, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SIG_DESC_CLEAR(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PIN_DECL_2(J22, GPIOC1, RGMII3TXCTL, RMII3TXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define H22 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SIG_EXPR_LIST_DECL_SESG(H22, RGMII3TXD0, RGMII3, SIG_DESC_SET(SCU410, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SIG_DESC_SET(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SIG_EXPR_LIST_DECL_SESG(H22, RMII3TXD0, RMII3, SIG_DESC_SET(SCU410, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) SIG_DESC_CLEAR(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PIN_DECL_2(H22, GPIOC2, RGMII3TXD0, RMII3TXD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define H23 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) SIG_EXPR_LIST_DECL_SESG(H23, RGMII3TXD1, RGMII3, SIG_DESC_SET(SCU410, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SIG_DESC_SET(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) SIG_EXPR_LIST_DECL_SESG(H23, RMII3TXD1, RMII3, SIG_DESC_SET(SCU410, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SIG_DESC_CLEAR(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PIN_DECL_2(H23, GPIOC3, RGMII3TXD1, RMII3TXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define G22 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SIG_EXPR_LIST_DECL_SESG(G22, RGMII3TXD2, RGMII3, SIG_DESC_SET(SCU410, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SIG_DESC_SET(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PIN_DECL_1(G22, GPIOC4, RGMII3TXD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define F22 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SIG_EXPR_LIST_DECL_SESG(F22, RGMII3TXD3, RGMII3, SIG_DESC_SET(SCU410, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SIG_DESC_SET(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PIN_DECL_1(F22, GPIOC5, RGMII3TXD3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define G23 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SIG_EXPR_LIST_DECL_SESG(G23, RGMII3RXCK, RGMII3, SIG_DESC_SET(SCU410, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SIG_DESC_SET(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SIG_EXPR_LIST_DECL_SESG(G23, RMII3RCLKI, RMII3, SIG_DESC_SET(SCU410, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) SIG_DESC_CLEAR(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PIN_DECL_2(G23, GPIOC6, RGMII3RXCK, RMII3RCLKI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define G24 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SIG_EXPR_LIST_DECL_SESG(G24, RGMII3RXCTL, RGMII3, SIG_DESC_SET(SCU410, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SIG_DESC_SET(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PIN_DECL_1(G24, GPIOC7, RGMII3RXCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define F23 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SIG_EXPR_LIST_DECL_SESG(F23, RGMII3RXD0, RGMII3, SIG_DESC_SET(SCU410, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) SIG_DESC_SET(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SIG_EXPR_LIST_DECL_SESG(F23, RMII3RXD0, RMII3, SIG_DESC_SET(SCU410, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) SIG_DESC_CLEAR(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PIN_DECL_2(F23, GPIOD0, RGMII3RXD0, RMII3RXD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define F26 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SIG_EXPR_LIST_DECL_SESG(F26, RGMII3RXD1, RGMII3, SIG_DESC_SET(SCU410, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SIG_DESC_SET(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SIG_EXPR_LIST_DECL_SESG(F26, RMII3RXD1, RMII3, SIG_DESC_SET(SCU410, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SIG_DESC_CLEAR(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PIN_DECL_2(F26, GPIOD1, RGMII3RXD1, RMII3RXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define F25 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SIG_EXPR_LIST_DECL_SESG(F25, RGMII3RXD2, RGMII3, SIG_DESC_SET(SCU410, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SIG_DESC_SET(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SIG_EXPR_LIST_DECL_SESG(F25, RMII3CRSDV, RMII3, SIG_DESC_SET(SCU410, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SIG_DESC_CLEAR(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PIN_DECL_2(F25, GPIOD2, RGMII3RXD2, RMII3CRSDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define E26 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SIG_EXPR_LIST_DECL_SESG(E26, RGMII3RXD3, RGMII3, SIG_DESC_SET(SCU410, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SIG_DESC_SET(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SIG_EXPR_LIST_DECL_SESG(E26, RMII3RXER, RMII3, SIG_DESC_SET(SCU410, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) SIG_DESC_CLEAR(SCU510, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PIN_DECL_2(E26, GPIOD3, RGMII3RXD3, RMII3RXER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) FUNC_GROUP_DECL(RGMII3, H24, J22, H22, H23, G22, F22, G23, G24, F23, F26, F25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) E26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) FUNC_GROUP_DECL(RMII3, H24, J22, H22, H23, G23, F23, F26, F25, E26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define F24 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) SIG_EXPR_LIST_DECL_SESG(F24, NCTS3, NCTS3, SIG_DESC_SET(SCU410, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) SIG_EXPR_LIST_DECL_SESG(F24, RGMII4TXCK, RGMII4, SIG_DESC_SET(SCU4B0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) SIG_DESC_SET(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SIG_EXPR_LIST_DECL_SESG(F24, RMII4RCLKO, RMII4, SIG_DESC_SET(SCU4B0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) SIG_DESC_CLEAR(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PIN_DECL_3(F24, GPIOD4, NCTS3, RGMII4TXCK, RMII4RCLKO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) FUNC_GROUP_DECL(NCTS3, F24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define E23 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) SIG_EXPR_LIST_DECL_SESG(E23, NDCD3, NDCD3, SIG_DESC_SET(SCU410, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) SIG_EXPR_LIST_DECL_SESG(E23, RGMII4TXCTL, RGMII4, SIG_DESC_SET(SCU4B0, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SIG_DESC_SET(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) SIG_EXPR_LIST_DECL_SESG(E23, RMII4TXEN, RMII4, SIG_DESC_SET(SCU4B0, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) SIG_DESC_CLEAR(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PIN_DECL_3(E23, GPIOD5, NDCD3, RGMII4TXCTL, RMII4TXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) FUNC_GROUP_DECL(NDCD3, E23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define E24 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) SIG_EXPR_LIST_DECL_SESG(E24, NDSR3, NDSR3, SIG_DESC_SET(SCU410, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) SIG_EXPR_LIST_DECL_SESG(E24, RGMII4TXD0, RGMII4, SIG_DESC_SET(SCU4B0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SIG_DESC_SET(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) SIG_EXPR_LIST_DECL_SESG(E24, RMII4TXD0, RMII4, SIG_DESC_SET(SCU4B0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) SIG_DESC_CLEAR(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PIN_DECL_3(E24, GPIOD6, NDSR3, RGMII4TXD0, RMII4TXD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) FUNC_GROUP_DECL(NDSR3, E24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define E25 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) SIG_EXPR_LIST_DECL_SESG(E25, NRI3, NRI3, SIG_DESC_SET(SCU410, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) SIG_EXPR_LIST_DECL_SESG(E25, RGMII4TXD1, RGMII4, SIG_DESC_SET(SCU4B0, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) SIG_DESC_SET(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SIG_EXPR_LIST_DECL_SESG(E25, RMII4TXD1, RMII4, SIG_DESC_SET(SCU4B0, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) SIG_DESC_CLEAR(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PIN_DECL_3(E25, GPIOD7, NRI3, RGMII4TXD1, RMII4TXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FUNC_GROUP_DECL(NRI3, E25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define D26 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SIG_EXPR_LIST_DECL_SESG(D26, NDTR3, NDTR3, SIG_DESC_SET(SCU414, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) SIG_EXPR_LIST_DECL_SESG(D26, RGMII4TXD2, RGMII4, SIG_DESC_SET(SCU4B4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) SIG_DESC_SET(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PIN_DECL_2(D26, GPIOE0, NDTR3, RGMII4TXD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) FUNC_GROUP_DECL(NDTR3, D26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define D24 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) SIG_EXPR_LIST_DECL_SESG(D24, NRTS3, NRTS3, SIG_DESC_SET(SCU414, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) SIG_EXPR_LIST_DECL_SESG(D24, RGMII4TXD3, RGMII4, SIG_DESC_SET(SCU4B4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) SIG_DESC_SET(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PIN_DECL_2(D24, GPIOE1, NRTS3, RGMII4TXD3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) FUNC_GROUP_DECL(NRTS3, D24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define C25 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) SIG_EXPR_LIST_DECL_SESG(C25, NCTS4, NCTS4, SIG_DESC_SET(SCU414, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) SIG_EXPR_LIST_DECL_SESG(C25, RGMII4RXCK, RGMII4, SIG_DESC_SET(SCU4B4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) SIG_DESC_SET(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) SIG_EXPR_LIST_DECL_SESG(C25, RMII4RCLKI, RMII4, SIG_DESC_SET(SCU4B4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) SIG_DESC_CLEAR(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PIN_DECL_3(C25, GPIOE2, NCTS4, RGMII4RXCK, RMII4RCLKI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) FUNC_GROUP_DECL(NCTS4, C25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define C26 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SIG_EXPR_LIST_DECL_SESG(C26, NDCD4, NDCD4, SIG_DESC_SET(SCU414, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) SIG_EXPR_LIST_DECL_SESG(C26, RGMII4RXCTL, RGMII4, SIG_DESC_SET(SCU4B4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) SIG_DESC_SET(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PIN_DECL_2(C26, GPIOE3, NDCD4, RGMII4RXCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) FUNC_GROUP_DECL(NDCD4, C26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define C24 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SIG_EXPR_LIST_DECL_SESG(C24, NDSR4, NDSR4, SIG_DESC_SET(SCU414, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SIG_EXPR_LIST_DECL_SESG(C24, RGMII4RXD0, RGMII4, SIG_DESC_SET(SCU4B4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) SIG_DESC_SET(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SIG_EXPR_LIST_DECL_SESG(C24, RMII4RXD0, RMII4, SIG_DESC_SET(SCU4B4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SIG_DESC_CLEAR(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PIN_DECL_3(C24, GPIOE4, NDSR4, RGMII4RXD0, RMII4RXD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) FUNC_GROUP_DECL(NDSR4, C24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define B26 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) SIG_EXPR_LIST_DECL_SESG(B26, NRI4, NRI4, SIG_DESC_SET(SCU414, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SIG_EXPR_LIST_DECL_SESG(B26, RGMII4RXD1, RGMII4, SIG_DESC_SET(SCU4B4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) SIG_DESC_SET(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SIG_EXPR_LIST_DECL_SESG(B26, RMII4RXD1, RMII4, SIG_DESC_SET(SCU4B4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SIG_DESC_CLEAR(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PIN_DECL_3(B26, GPIOE5, NRI4, RGMII4RXD1, RMII4RXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) FUNC_GROUP_DECL(NRI4, B26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define B25 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SIG_EXPR_LIST_DECL_SESG(B25, NDTR4, NDTR4, SIG_DESC_SET(SCU414, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SIG_EXPR_LIST_DECL_SESG(B25, RGMII4RXD2, RGMII4, SIG_DESC_SET(SCU4B4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) SIG_DESC_SET(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SIG_EXPR_LIST_DECL_SESG(B25, RMII4CRSDV, RMII4, SIG_DESC_SET(SCU4B4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) SIG_DESC_CLEAR(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PIN_DECL_3(B25, GPIOE6, NDTR4, RGMII4RXD2, RMII4CRSDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) FUNC_GROUP_DECL(NDTR4, B25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define B24 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SIG_EXPR_LIST_DECL_SESG(B24, NRTS4, NRTS4, SIG_DESC_SET(SCU414, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) SIG_EXPR_LIST_DECL_SESG(B24, RGMII4RXD3, RGMII4, SIG_DESC_SET(SCU4B4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) SIG_DESC_SET(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SIG_EXPR_LIST_DECL_SESG(B24, RMII4RXER, RMII4, SIG_DESC_SET(SCU4B4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) SIG_DESC_CLEAR(SCU510, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PIN_DECL_3(B24, GPIOE7, NRTS4, RGMII4RXD3, RMII4RXER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) FUNC_GROUP_DECL(NRTS4, B24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) FUNC_GROUP_DECL(RGMII4, F24, E23, E24, E25, D26, D24, C25, C26, C24, B26, B25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) B24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) FUNC_GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define D22 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) SIG_EXPR_LIST_DECL_SESG(D22, SD1CLK, SD1, SIG_DESC_SET(SCU414, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) SIG_EXPR_LIST_DECL_SEMG(D22, PWM8, PWM8G0, PWM8, SIG_DESC_SET(SCU4B4, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PIN_DECL_2(D22, GPIOF0, SD1CLK, PWM8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) GROUP_DECL(PWM8G0, D22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define E22 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) SIG_EXPR_LIST_DECL_SESG(E22, SD1CMD, SD1, SIG_DESC_SET(SCU414, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SIG_EXPR_LIST_DECL_SEMG(E22, PWM9, PWM9G0, PWM9, SIG_DESC_SET(SCU4B4, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PIN_DECL_2(E22, GPIOF1, SD1CMD, PWM9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) GROUP_DECL(PWM9G0, E22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define D23 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) SIG_EXPR_LIST_DECL_SESG(D23, SD1DAT0, SD1, SIG_DESC_SET(SCU414, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SIG_EXPR_LIST_DECL_SEMG(D23, PWM10, PWM10G0, PWM10, SIG_DESC_SET(SCU4B4, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PIN_DECL_2(D23, GPIOF2, SD1DAT0, PWM10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) GROUP_DECL(PWM10G0, D23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define C23 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) SIG_EXPR_LIST_DECL_SESG(C23, SD1DAT1, SD1, SIG_DESC_SET(SCU414, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) SIG_EXPR_LIST_DECL_SEMG(C23, PWM11, PWM11G0, PWM11, SIG_DESC_SET(SCU4B4, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PIN_DECL_2(C23, GPIOF3, SD1DAT1, PWM11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) GROUP_DECL(PWM11G0, C23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define C22 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) SIG_EXPR_LIST_DECL_SESG(C22, SD1DAT2, SD1, SIG_DESC_SET(SCU414, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) SIG_EXPR_LIST_DECL_SEMG(C22, PWM12, PWM12G0, PWM12, SIG_DESC_SET(SCU4B4, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PIN_DECL_2(C22, GPIOF4, SD1DAT2, PWM12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) GROUP_DECL(PWM12G0, C22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define A25 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) SIG_EXPR_LIST_DECL_SESG(A25, SD1DAT3, SD1, SIG_DESC_SET(SCU414, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) SIG_EXPR_LIST_DECL_SEMG(A25, PWM13, PWM13G0, PWM13, SIG_DESC_SET(SCU4B4, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PIN_DECL_2(A25, GPIOF5, SD1DAT3, PWM13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) GROUP_DECL(PWM13G0, A25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define A24 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) SIG_EXPR_LIST_DECL_SESG(A24, SD1CD, SD1, SIG_DESC_SET(SCU414, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) SIG_EXPR_LIST_DECL_SEMG(A24, PWM14, PWM14G0, PWM14, SIG_DESC_SET(SCU4B4, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PIN_DECL_2(A24, GPIOF6, SD1CD, PWM14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) GROUP_DECL(PWM14G0, A24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define A23 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) SIG_EXPR_LIST_DECL_SESG(A23, SD1WP, SD1, SIG_DESC_SET(SCU414, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) SIG_EXPR_LIST_DECL_SEMG(A23, PWM15, PWM15G0, PWM15, SIG_DESC_SET(SCU4B4, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PIN_DECL_2(A23, GPIOF7, SD1WP, PWM15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) GROUP_DECL(PWM15G0, A23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) FUNC_GROUP_DECL(SD1, D22, E22, D23, C23, C22, A25, A24, A23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define E21 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) SIG_EXPR_LIST_DECL_SESG(E21, TXD6, UART6, SIG_DESC_SET(SCU414, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SIG_EXPR_LIST_DECL_SESG(E21, SD2CLK, SD2, SIG_DESC_SET(SCU4B4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) SIG_DESC_SET(SCU450, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) SIG_EXPR_LIST_DECL_SEMG(E21, SALT9, SALT9G0, SALT9, SIG_DESC_SET(SCU694, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PIN_DECL_3(E21, GPIOG0, TXD6, SD2CLK, SALT9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) GROUP_DECL(SALT9G0, E21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define B22 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SIG_EXPR_LIST_DECL_SESG(B22, RXD6, UART6, SIG_DESC_SET(SCU414, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) SIG_EXPR_LIST_DECL_SESG(B22, SD2CMD, SD2, SIG_DESC_SET(SCU4B4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) SIG_DESC_SET(SCU450, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) SIG_EXPR_LIST_DECL_SEMG(B22, SALT10, SALT10G0, SALT10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SIG_DESC_SET(SCU694, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PIN_DECL_3(B22, GPIOG1, RXD6, SD2CMD, SALT10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) GROUP_DECL(SALT10G0, B22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) FUNC_GROUP_DECL(UART6, E21, B22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define C21 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) SIG_EXPR_LIST_DECL_SESG(C21, TXD7, UART7, SIG_DESC_SET(SCU414, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) SIG_EXPR_LIST_DECL_SESG(C21, SD2DAT0, SD2, SIG_DESC_SET(SCU4B4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) SIG_DESC_SET(SCU450, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) SIG_EXPR_LIST_DECL_SEMG(C21, SALT11, SALT11G0, SALT11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) SIG_DESC_SET(SCU694, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PIN_DECL_3(C21, GPIOG2, TXD7, SD2DAT0, SALT11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) GROUP_DECL(SALT11G0, C21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define A22 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) SIG_EXPR_LIST_DECL_SESG(A22, RXD7, UART7, SIG_DESC_SET(SCU414, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) SIG_EXPR_LIST_DECL_SESG(A22, SD2DAT1, SD2, SIG_DESC_SET(SCU4B4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) SIG_DESC_SET(SCU450, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) SIG_EXPR_LIST_DECL_SEMG(A22, SALT12, SALT12G0, SALT12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) SIG_DESC_SET(SCU694, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PIN_DECL_3(A22, GPIOG3, RXD7, SD2DAT1, SALT12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) GROUP_DECL(SALT12G0, A22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) FUNC_GROUP_DECL(UART7, C21, A22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define A21 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) SIG_EXPR_LIST_DECL_SESG(A21, TXD8, UART8, SIG_DESC_SET(SCU414, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) SIG_EXPR_LIST_DECL_SESG(A21, SD2DAT2, SD2, SIG_DESC_SET(SCU4B4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) SIG_DESC_SET(SCU450, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) SIG_EXPR_LIST_DECL_SEMG(A21, SALT13, SALT13G0, SALT13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) SIG_DESC_SET(SCU694, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PIN_DECL_3(A21, GPIOG4, TXD8, SD2DAT2, SALT13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) GROUP_DECL(SALT13G0, A21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define E20 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) SIG_EXPR_LIST_DECL_SESG(E20, RXD8, UART8, SIG_DESC_SET(SCU414, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) SIG_EXPR_LIST_DECL_SESG(E20, SD2DAT3, SD2, SIG_DESC_SET(SCU4B4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) SIG_DESC_SET(SCU450, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) SIG_EXPR_LIST_DECL_SEMG(E20, SALT14, SALT14G0, SALT14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SIG_DESC_SET(SCU694, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PIN_DECL_3(E20, GPIOG5, RXD8, SD2DAT3, SALT14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) GROUP_DECL(SALT14G0, E20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) FUNC_GROUP_DECL(UART8, A21, E20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define D21 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) SIG_EXPR_LIST_DECL_SESG(D21, TXD9, UART9, SIG_DESC_SET(SCU414, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) SIG_EXPR_LIST_DECL_SESG(D21, SD2CD, SD2, SIG_DESC_SET(SCU4B4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) SIG_DESC_SET(SCU450, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SIG_EXPR_LIST_DECL_SEMG(D21, SALT15, SALT15G0, SALT15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) SIG_DESC_SET(SCU694, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PIN_DECL_3(D21, GPIOG6, TXD9, SD2CD, SALT15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) GROUP_DECL(SALT15G0, D21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define B21 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SIG_EXPR_LIST_DECL_SESG(B21, RXD9, UART9, SIG_DESC_SET(SCU414, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) SIG_EXPR_LIST_DECL_SESG(B21, SD2WP, SD2, SIG_DESC_SET(SCU4B4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) SIG_DESC_SET(SCU450, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) SIG_EXPR_LIST_DECL_SEMG(B21, SALT16, SALT16G0, SALT16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) SIG_DESC_SET(SCU694, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PIN_DECL_3(B21, GPIOG7, RXD9, SD2WP, SALT16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) GROUP_DECL(SALT16G0, B21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) FUNC_GROUP_DECL(UART9, D21, B21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) FUNC_GROUP_DECL(SD2, E21, B22, C21, A22, A21, E20, D21, B21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define A18 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) SIG_EXPR_LIST_DECL_SESG(A18, SGPM1CLK, SGPM1, SIG_DESC_SET(SCU414, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PIN_DECL_1(A18, GPIOH0, SGPM1CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define B18 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SIG_EXPR_LIST_DECL_SESG(B18, SGPM1LD, SGPM1, SIG_DESC_SET(SCU414, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PIN_DECL_1(B18, GPIOH1, SGPM1LD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define C18 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) SIG_EXPR_LIST_DECL_SESG(C18, SGPM1O, SGPM1, SIG_DESC_SET(SCU414, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PIN_DECL_1(C18, GPIOH2, SGPM1O);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define A17 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) SIG_EXPR_LIST_DECL_SESG(A17, SGPM1I, SGPM1, SIG_DESC_SET(SCU414, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PIN_DECL_1(A17, GPIOH3, SGPM1I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) FUNC_GROUP_DECL(SGPM1, A18, B18, C18, A17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define D18 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) SIG_EXPR_LIST_DECL_SESG(D18, SGPS1CK, SGPS1, SIG_DESC_SET(SCU414, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) SIG_EXPR_LIST_DECL_SESG(D18, SCL15, I2C15, SIG_DESC_SET(SCU4B4, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PIN_DECL_2(D18, GPIOH4, SGPS1CK, SCL15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define B17 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) SIG_EXPR_LIST_DECL_SESG(B17, SGPS1LD, SGPS1, SIG_DESC_SET(SCU414, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) SIG_EXPR_LIST_DECL_SESG(B17, SDA15, I2C15, SIG_DESC_SET(SCU4B4, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PIN_DECL_2(B17, GPIOH5, SGPS1LD, SDA15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) FUNC_GROUP_DECL(I2C15, D18, B17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define C17 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SIG_EXPR_LIST_DECL_SESG(C17, SGPS1O, SGPS1, SIG_DESC_SET(SCU414, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) SIG_EXPR_LIST_DECL_SESG(C17, SCL16, I2C16, SIG_DESC_SET(SCU4B4, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PIN_DECL_2(C17, GPIOH6, SGPS1O, SCL16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define E18 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) SIG_EXPR_LIST_DECL_SESG(E18, SGPS1I, SGPS1, SIG_DESC_SET(SCU414, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SIG_EXPR_LIST_DECL_SESG(E18, SDA16, I2C16, SIG_DESC_SET(SCU4B4, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PIN_DECL_2(E18, GPIOH7, SGPS1I, SDA16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) FUNC_GROUP_DECL(I2C16, C17, E18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) FUNC_GROUP_DECL(SGPS1, D18, B17, C17, E18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define D17 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) SIG_EXPR_LIST_DECL_SESG(D17, MTRSTN, JTAGM, SIG_DESC_SET(SCU418, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SIG_EXPR_LIST_DECL_SEMG(D17, TXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PIN_DECL_2(D17, GPIOI0, MTRSTN, TXD12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define A16 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) SIG_EXPR_LIST_DECL_SESG(A16, MTDI, JTAGM, SIG_DESC_SET(SCU418, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) SIG_EXPR_LIST_DECL_SEMG(A16, RXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PIN_DECL_2(A16, GPIOI1, MTDI, RXD12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) GROUP_DECL(UART12G0, D17, A16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define E17 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) SIG_EXPR_LIST_DECL_SESG(E17, MTCK, JTAGM, SIG_DESC_SET(SCU418, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) SIG_EXPR_LIST_DECL_SEMG(E17, TXD13, UART13G0, UART13, SIG_DESC_SET(SCU4B8, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PIN_DECL_2(E17, GPIOI2, MTCK, TXD13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define D16 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) SIG_EXPR_LIST_DECL_SESG(D16, MTMS, JTAGM, SIG_DESC_SET(SCU418, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) SIG_EXPR_LIST_DECL_SEMG(D16, RXD13, UART13G0, UART13, SIG_DESC_SET(SCU4B8, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PIN_DECL_2(D16, GPIOI3, MTMS, RXD13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GROUP_DECL(UART13G0, E17, D16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define C16 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) SIG_EXPR_LIST_DECL_SESG(C16, MTDO, JTAGM, SIG_DESC_SET(SCU418, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PIN_DECL_1(C16, GPIOI4, MTDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) FUNC_GROUP_DECL(JTAGM, D17, A16, E17, D16, C16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define E16 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) SIG_EXPR_LIST_DECL_SESG(E16, SIOPBO, SIOPBO, SIG_DESC_SET(SCU418, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PIN_DECL_1(E16, GPIOI5, SIOPBO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) FUNC_GROUP_DECL(SIOPBO, E16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define B16 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) SIG_EXPR_LIST_DECL_SESG(B16, SIOPBI, SIOPBI, SIG_DESC_SET(SCU418, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PIN_DECL_1(B16, GPIOI6, SIOPBI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) FUNC_GROUP_DECL(SIOPBI, B16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define A15 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SIG_EXPR_LIST_DECL_SESG(A15, BMCINT, BMCINT, SIG_DESC_SET(SCU418, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) SIG_EXPR_LIST_DECL_SESG(A15, SIOSCI, SIOSCI, SIG_DESC_SET(SCU4B8, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PIN_DECL_2(A15, GPIOI7, BMCINT, SIOSCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) FUNC_GROUP_DECL(BMCINT, A15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) FUNC_GROUP_DECL(SIOSCI, A15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define B20 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) SIG_EXPR_LIST_DECL_SEMG(B20, I3C3SCL, HVI3C3, I3C3, SIG_DESC_SET(SCU418, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) SIG_EXPR_LIST_DECL_SESG(B20, SCL1, I2C1, SIG_DESC_SET(SCU4B8, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PIN_DECL_2(B20, GPIOJ0, I3C3SCL, SCL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define A20 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) SIG_EXPR_LIST_DECL_SEMG(A20, I3C3SDA, HVI3C3, I3C3, SIG_DESC_SET(SCU418, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) SIG_EXPR_LIST_DECL_SESG(A20, SDA1, I2C1, SIG_DESC_SET(SCU4B8, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PIN_DECL_2(A20, GPIOJ1, I3C3SDA, SDA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) GROUP_DECL(HVI3C3, B20, A20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) FUNC_GROUP_DECL(I2C1, B20, A20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define E19 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) SIG_EXPR_LIST_DECL_SEMG(E19, I3C4SCL, HVI3C4, I3C4, SIG_DESC_SET(SCU418, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) SIG_EXPR_LIST_DECL_SESG(E19, SCL2, I2C2, SIG_DESC_SET(SCU4B8, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PIN_DECL_2(E19, GPIOJ2, I3C4SCL, SCL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define D20 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) SIG_EXPR_LIST_DECL_SEMG(D20, I3C4SDA, HVI3C4, I3C4, SIG_DESC_SET(SCU418, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) SIG_EXPR_LIST_DECL_SESG(D20, SDA2, I2C2, SIG_DESC_SET(SCU4B8, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PIN_DECL_2(D20, GPIOJ3, I3C4SDA, SDA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GROUP_DECL(HVI3C4, E19, D20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) FUNC_GROUP_DECL(I2C2, E19, D20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define C19 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) SIG_EXPR_LIST_DECL_SESG(C19, I3C5SCL, I3C5, SIG_DESC_SET(SCU418, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) SIG_EXPR_LIST_DECL_SESG(C19, SCL3, I2C3, SIG_DESC_SET(SCU4B8, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PIN_DECL_2(C19, GPIOJ4, I3C5SCL, SCL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define A19 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) SIG_EXPR_LIST_DECL_SESG(A19, I3C5SDA, I3C5, SIG_DESC_SET(SCU418, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) SIG_EXPR_LIST_DECL_SESG(A19, SDA3, I2C3, SIG_DESC_SET(SCU4B8, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PIN_DECL_2(A19, GPIOJ5, I3C5SDA, SDA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) FUNC_GROUP_DECL(I3C5, C19, A19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) FUNC_GROUP_DECL(I2C3, C19, A19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define C20 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) SIG_EXPR_LIST_DECL_SESG(C20, I3C6SCL, I3C6, SIG_DESC_SET(SCU418, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) SIG_EXPR_LIST_DECL_SESG(C20, SCL4, I2C4, SIG_DESC_SET(SCU4B8, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PIN_DECL_2(C20, GPIOJ6, I3C6SCL, SCL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define D19 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) SIG_EXPR_LIST_DECL_SESG(D19, I3C6SDA, I3C6, SIG_DESC_SET(SCU418, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) SIG_EXPR_LIST_DECL_SESG(D19, SDA4, I2C4, SIG_DESC_SET(SCU4B8, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PIN_DECL_2(D19, GPIOJ7, I3C6SDA, SDA4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) FUNC_GROUP_DECL(I3C6, C20, D19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) FUNC_GROUP_DECL(I2C4, C20, D19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define A11 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) SIG_EXPR_LIST_DECL_SESG(A11, SCL5, I2C5, SIG_DESC_SET(SCU418, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PIN_DECL_1(A11, GPIOK0, SCL5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define C11 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) SIG_EXPR_LIST_DECL_SESG(C11, SDA5, I2C5, SIG_DESC_SET(SCU418, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PIN_DECL_1(C11, GPIOK1, SDA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) FUNC_GROUP_DECL(I2C5, A11, C11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define D12 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) SIG_EXPR_LIST_DECL_SESG(D12, SCL6, I2C6, SIG_DESC_SET(SCU418, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PIN_DECL_1(D12, GPIOK2, SCL6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define E13 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) SIG_EXPR_LIST_DECL_SESG(E13, SDA6, I2C6, SIG_DESC_SET(SCU418, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PIN_DECL_1(E13, GPIOK3, SDA6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) FUNC_GROUP_DECL(I2C6, D12, E13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define D11 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) SIG_EXPR_LIST_DECL_SESG(D11, SCL7, I2C7, SIG_DESC_SET(SCU418, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PIN_DECL_1(D11, GPIOK4, SCL7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define E11 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) SIG_EXPR_LIST_DECL_SESG(E11, SDA7, I2C7, SIG_DESC_SET(SCU418, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PIN_DECL_1(E11, GPIOK5, SDA7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) FUNC_GROUP_DECL(I2C7, D11, E11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define F13 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) SIG_EXPR_LIST_DECL_SESG(F13, SCL8, I2C8, SIG_DESC_SET(SCU418, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PIN_DECL_1(F13, GPIOK6, SCL8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define E12 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SIG_EXPR_LIST_DECL_SESG(E12, SDA8, I2C8, SIG_DESC_SET(SCU418, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PIN_DECL_1(E12, GPIOK7, SDA8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) FUNC_GROUP_DECL(I2C8, F13, E12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define D15 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) SIG_EXPR_LIST_DECL_SESG(D15, SCL9, I2C9, SIG_DESC_SET(SCU418, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PIN_DECL_1(D15, GPIOL0, SCL9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define A14 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) SIG_EXPR_LIST_DECL_SESG(A14, SDA9, I2C9, SIG_DESC_SET(SCU418, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PIN_DECL_1(A14, GPIOL1, SDA9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) FUNC_GROUP_DECL(I2C9, D15, A14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define E15 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) SIG_EXPR_LIST_DECL_SESG(E15, SCL10, I2C10, SIG_DESC_SET(SCU418, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PIN_DECL_1(E15, GPIOL2, SCL10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define A13 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) SIG_EXPR_LIST_DECL_SESG(A13, SDA10, I2C10, SIG_DESC_SET(SCU418, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PIN_DECL_1(A13, GPIOL3, SDA10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) FUNC_GROUP_DECL(I2C10, E15, A13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define C15 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) SSSF_PIN_DECL(C15, GPIOL4, TXD3, SIG_DESC_SET(SCU418, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define F15 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) SSSF_PIN_DECL(F15, GPIOL5, RXD3, SIG_DESC_SET(SCU418, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define B14 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) SSSF_PIN_DECL(B14, GPIOL6, VGAHS, SIG_DESC_SET(SCU418, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define C14 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) SSSF_PIN_DECL(C14, GPIOL7, VGAVS, SIG_DESC_SET(SCU418, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define D14 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) SSSF_PIN_DECL(D14, GPIOM0, NCTS1, SIG_DESC_SET(SCU41C, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define B13 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) SSSF_PIN_DECL(B13, GPIOM1, NDCD1, SIG_DESC_SET(SCU41C, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define A12 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) SSSF_PIN_DECL(A12, GPIOM2, NDSR1, SIG_DESC_SET(SCU41C, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define E14 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) SSSF_PIN_DECL(E14, GPIOM3, NRI1, SIG_DESC_SET(SCU41C, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define B12 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) SSSF_PIN_DECL(B12, GPIOM4, NDTR1, SIG_DESC_SET(SCU41C, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define C12 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) SSSF_PIN_DECL(C12, GPIOM5, NRTS1, SIG_DESC_SET(SCU41C, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define C13 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) SSSF_PIN_DECL(C13, GPIOM6, TXD1, SIG_DESC_SET(SCU41C, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define D13 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) SSSF_PIN_DECL(D13, GPIOM7, RXD1, SIG_DESC_SET(SCU41C, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define P25 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) SSSF_PIN_DECL(P25, GPION0, NCTS2, SIG_DESC_SET(SCU41C, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define N23 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) SSSF_PIN_DECL(N23, GPION1, NDCD2, SIG_DESC_SET(SCU41C, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define N25 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) SSSF_PIN_DECL(N25, GPION2, NDSR2, SIG_DESC_SET(SCU41C, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define N24 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) SSSF_PIN_DECL(N24, GPION3, NRI2, SIG_DESC_SET(SCU41C, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define P26 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) SSSF_PIN_DECL(P26, GPION4, NDTR2, SIG_DESC_SET(SCU41C, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define M23 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) SSSF_PIN_DECL(M23, GPION5, NRTS2, SIG_DESC_SET(SCU41C, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define N26 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) SSSF_PIN_DECL(N26, GPION6, TXD2, SIG_DESC_SET(SCU41C, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define M26 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) SSSF_PIN_DECL(M26, GPION7, RXD2, SIG_DESC_SET(SCU41C, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define AD26 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) SSSF_PIN_DECL(AD26, GPIOO0, PWM0, SIG_DESC_SET(SCU41C, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define AD22 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) SSSF_PIN_DECL(AD22, GPIOO1, PWM1, SIG_DESC_SET(SCU41C, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define AD23 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) SSSF_PIN_DECL(AD23, GPIOO2, PWM2, SIG_DESC_SET(SCU41C, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define AD24 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) SSSF_PIN_DECL(AD24, GPIOO3, PWM3, SIG_DESC_SET(SCU41C, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define AD25 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) SSSF_PIN_DECL(AD25, GPIOO4, PWM4, SIG_DESC_SET(SCU41C, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define AC22 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) SSSF_PIN_DECL(AC22, GPIOO5, PWM5, SIG_DESC_SET(SCU41C, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define AC24 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) SSSF_PIN_DECL(AC24, GPIOO6, PWM6, SIG_DESC_SET(SCU41C, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define AC23 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) SSSF_PIN_DECL(AC23, GPIOO7, PWM7, SIG_DESC_SET(SCU41C, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define AB22 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) SIG_EXPR_LIST_DECL_SEMG(AB22, PWM8, PWM8G1, PWM8, SIG_DESC_SET(SCU41C, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) SIG_EXPR_LIST_DECL_SESG(AB22, THRUIN0, THRU0, SIG_DESC_SET(SCU4BC, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PIN_DECL_2(AB22, GPIOP0, PWM8, THRUIN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) GROUP_DECL(PWM8G1, AB22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) FUNC_DECL_2(PWM8, PWM8G0, PWM8G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define W24 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) SIG_EXPR_LIST_DECL_SEMG(W24, PWM9, PWM9G1, PWM9, SIG_DESC_SET(SCU41C, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) SIG_EXPR_LIST_DECL_SESG(W24, THRUOUT0, THRU0, SIG_DESC_SET(SCU4BC, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) PIN_DECL_2(W24, GPIOP1, PWM9, THRUOUT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) FUNC_GROUP_DECL(THRU0, AB22, W24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) GROUP_DECL(PWM9G1, W24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) FUNC_DECL_2(PWM9, PWM9G0, PWM9G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define AA23 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) SIG_EXPR_LIST_DECL_SEMG(AA23, PWM10, PWM10G1, PWM10, SIG_DESC_SET(SCU41C, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) SIG_EXPR_LIST_DECL_SESG(AA23, THRUIN1, THRU1, SIG_DESC_SET(SCU4BC, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) PIN_DECL_2(AA23, GPIOP2, PWM10, THRUIN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) GROUP_DECL(PWM10G1, AA23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) FUNC_DECL_2(PWM10, PWM10G0, PWM10G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define AA24 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) SIG_EXPR_LIST_DECL_SEMG(AA24, PWM11, PWM11G1, PWM11, SIG_DESC_SET(SCU41C, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) SIG_EXPR_LIST_DECL_SESG(AA24, THRUOUT1, THRU1, SIG_DESC_SET(SCU4BC, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PIN_DECL_2(AA24, GPIOP3, PWM11, THRUOUT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) GROUP_DECL(PWM11G1, AA24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) FUNC_DECL_2(PWM11, PWM11G0, PWM11G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) FUNC_GROUP_DECL(THRU1, AA23, AA24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define W23 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) SIG_EXPR_LIST_DECL_SEMG(W23, PWM12, PWM12G1, PWM12, SIG_DESC_SET(SCU41C, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) SIG_EXPR_LIST_DECL_SESG(W23, THRUIN2, THRU2, SIG_DESC_SET(SCU4BC, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) PIN_DECL_2(W23, GPIOP4, PWM12, THRUIN2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) GROUP_DECL(PWM12G1, W23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) FUNC_DECL_2(PWM12, PWM12G0, PWM12G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define AB23 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) SIG_EXPR_LIST_DECL_SEMG(AB23, PWM13, PWM13G1, PWM13, SIG_DESC_SET(SCU41C, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) SIG_EXPR_LIST_DECL_SESG(AB23, THRUOUT2, THRU2, SIG_DESC_SET(SCU4BC, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PIN_DECL_2(AB23, GPIOP5, PWM13, THRUOUT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) GROUP_DECL(PWM13G1, AB23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) FUNC_DECL_2(PWM13, PWM13G0, PWM13G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) FUNC_GROUP_DECL(THRU2, W23, AB23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define AB24 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) SIG_EXPR_LIST_DECL_SEMG(AB24, PWM14, PWM14G1, PWM14, SIG_DESC_SET(SCU41C, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) SIG_EXPR_LIST_DECL_SESG(AB24, THRUIN3, THRU3, SIG_DESC_SET(SCU4BC, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) PIN_DECL_2(AB24, GPIOP6, PWM14, THRUIN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) GROUP_DECL(PWM14G1, AB24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) FUNC_DECL_2(PWM14, PWM14G0, PWM14G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define Y23 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) SIG_EXPR_LIST_DECL_SEMG(Y23, PWM15, PWM15G1, PWM15, SIG_DESC_SET(SCU41C, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) SIG_EXPR_LIST_DECL_SESG(Y23, THRUOUT3, THRU3, SIG_DESC_SET(SCU4BC, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) SIG_EXPR_LIST_DECL_SESG(Y23, HEARTBEAT, HEARTBEAT, SIG_DESC_SET(SCU69C, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PIN_DECL_3(Y23, GPIOP7, PWM15, THRUOUT3, HEARTBEAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) GROUP_DECL(PWM15G1, Y23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) FUNC_DECL_2(PWM15, PWM15G0, PWM15G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) FUNC_GROUP_DECL(THRU3, AB24, Y23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) FUNC_GROUP_DECL(HEARTBEAT, Y23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define AA25 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) SSSF_PIN_DECL(AA25, GPIOQ0, TACH0, SIG_DESC_SET(SCU430, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define AB25 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) SSSF_PIN_DECL(AB25, GPIOQ1, TACH1, SIG_DESC_SET(SCU430, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define Y24 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) SSSF_PIN_DECL(Y24, GPIOQ2, TACH2, SIG_DESC_SET(SCU430, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define AB26 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) SSSF_PIN_DECL(AB26, GPIOQ3, TACH3, SIG_DESC_SET(SCU430, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define Y26 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) SSSF_PIN_DECL(Y26, GPIOQ4, TACH4, SIG_DESC_SET(SCU430, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define AC26 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) SSSF_PIN_DECL(AC26, GPIOQ5, TACH5, SIG_DESC_SET(SCU430, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define Y25 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) SSSF_PIN_DECL(Y25, GPIOQ6, TACH6, SIG_DESC_SET(SCU430, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define AA26 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) SSSF_PIN_DECL(AA26, GPIOQ7, TACH7, SIG_DESC_SET(SCU430, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define V25 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) SSSF_PIN_DECL(V25, GPIOR0, TACH8, SIG_DESC_SET(SCU430, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define U24 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) SSSF_PIN_DECL(U24, GPIOR1, TACH9, SIG_DESC_SET(SCU430, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define V24 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) SSSF_PIN_DECL(V24, GPIOR2, TACH10, SIG_DESC_SET(SCU430, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define V26 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) SSSF_PIN_DECL(V26, GPIOR3, TACH11, SIG_DESC_SET(SCU430, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define U25 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) SSSF_PIN_DECL(U25, GPIOR4, TACH12, SIG_DESC_SET(SCU430, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define T23 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) SSSF_PIN_DECL(T23, GPIOR5, TACH13, SIG_DESC_SET(SCU430, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define W26 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) SSSF_PIN_DECL(W26, GPIOR6, TACH14, SIG_DESC_SET(SCU430, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define U26 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) SSSF_PIN_DECL(U26, GPIOR7, TACH15, SIG_DESC_SET(SCU430, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define R23 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) SIG_EXPR_LIST_DECL_SESG(R23, MDC1, MDIO1, SIG_DESC_SET(SCU430, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) PIN_DECL_1(R23, GPIOS0, MDC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define T25 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) SIG_EXPR_LIST_DECL_SESG(T25, MDIO1, MDIO1, SIG_DESC_SET(SCU430, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) PIN_DECL_1(T25, GPIOS1, MDIO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) FUNC_GROUP_DECL(MDIO1, R23, T25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define T26 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) SSSF_PIN_DECL(T26, GPIOS2, PEWAKE, SIG_DESC_SET(SCU430, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define R24 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) SSSF_PIN_DECL(R24, GPIOS3, OSCCLK, SIG_DESC_SET(SCU430, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define R26 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) SIG_EXPR_LIST_DECL_SESG(R26, TXD10, UART10, SIG_DESC_SET(SCU430, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) PIN_DECL_1(R26, GPIOS4, TXD10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define P24 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) SIG_EXPR_LIST_DECL_SESG(P24, RXD10, UART10, SIG_DESC_SET(SCU430, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PIN_DECL_1(P24, GPIOS5, RXD10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) FUNC_GROUP_DECL(UART10, R26, P24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define P23 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) SIG_EXPR_LIST_DECL_SESG(P23, TXD11, UART11, SIG_DESC_SET(SCU430, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PIN_DECL_1(P23, GPIOS6, TXD11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define T24 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) SIG_EXPR_LIST_DECL_SESG(T24, RXD11, UART11, SIG_DESC_SET(SCU430, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PIN_DECL_1(T24, GPIOS7, RXD11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) FUNC_GROUP_DECL(UART11, P23, T24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define AD20 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) SIG_EXPR_LIST_DECL_SESG(AD20, GPIT0, GPIT0, SIG_DESC_SET(SCU430, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) SIG_EXPR_LIST_DECL_SESG(AD20, ADC0, ADC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) PIN_DECL_(AD20, SIG_EXPR_LIST_PTR(AD20, GPIT0), SIG_EXPR_LIST_PTR(AD20, ADC0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) FUNC_GROUP_DECL(GPIT0, AD20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) FUNC_GROUP_DECL(ADC0, AD20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define AC18 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) SIG_EXPR_LIST_DECL_SESG(AC18, GPIT1, GPIT1, SIG_DESC_SET(SCU430, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) SIG_EXPR_LIST_DECL_SESG(AC18, ADC1, ADC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PIN_DECL_(AC18, SIG_EXPR_LIST_PTR(AC18, GPIT1), SIG_EXPR_LIST_PTR(AC18, ADC1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) FUNC_GROUP_DECL(GPIT1, AC18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) FUNC_GROUP_DECL(ADC1, AC18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define AE19 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) SIG_EXPR_LIST_DECL_SESG(AE19, GPIT2, GPIT2, SIG_DESC_SET(SCU430, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) SIG_EXPR_LIST_DECL_SESG(AE19, ADC2, ADC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PIN_DECL_(AE19, SIG_EXPR_LIST_PTR(AE19, GPIT2), SIG_EXPR_LIST_PTR(AE19, ADC2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) FUNC_GROUP_DECL(GPIT2, AE19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) FUNC_GROUP_DECL(ADC2, AE19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define AD19 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) SIG_EXPR_LIST_DECL_SESG(AD19, GPIT3, GPIT3, SIG_DESC_SET(SCU430, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) SIG_EXPR_LIST_DECL_SESG(AD19, ADC3, ADC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) PIN_DECL_(AD19, SIG_EXPR_LIST_PTR(AD19, GPIT3), SIG_EXPR_LIST_PTR(AD19, ADC3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) FUNC_GROUP_DECL(GPIT3, AD19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) FUNC_GROUP_DECL(ADC3, AD19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define AC19 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) SIG_EXPR_LIST_DECL_SESG(AC19, GPIT4, GPIT4, SIG_DESC_SET(SCU430, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) SIG_EXPR_LIST_DECL_SESG(AC19, ADC4, ADC4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) PIN_DECL_(AC19, SIG_EXPR_LIST_PTR(AC19, GPIT4), SIG_EXPR_LIST_PTR(AC19, ADC4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) FUNC_GROUP_DECL(GPIT4, AC19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) FUNC_GROUP_DECL(ADC4, AC19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define AB19 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) SIG_EXPR_LIST_DECL_SESG(AB19, GPIT5, GPIT5, SIG_DESC_SET(SCU430, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) SIG_EXPR_LIST_DECL_SESG(AB19, ADC5, ADC5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PIN_DECL_(AB19, SIG_EXPR_LIST_PTR(AB19, GPIT5), SIG_EXPR_LIST_PTR(AB19, ADC5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) FUNC_GROUP_DECL(GPIT5, AB19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) FUNC_GROUP_DECL(ADC5, AB19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define AB18 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) SIG_EXPR_LIST_DECL_SESG(AB18, GPIT6, GPIT6, SIG_DESC_SET(SCU430, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) SIG_EXPR_LIST_DECL_SESG(AB18, ADC6, ADC6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PIN_DECL_(AB18, SIG_EXPR_LIST_PTR(AB18, GPIT6), SIG_EXPR_LIST_PTR(AB18, ADC6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) FUNC_GROUP_DECL(GPIT6, AB18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) FUNC_GROUP_DECL(ADC6, AB18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define AE18 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) SIG_EXPR_LIST_DECL_SESG(AE18, GPIT7, GPIT7, SIG_DESC_SET(SCU430, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) SIG_EXPR_LIST_DECL_SESG(AE18, ADC7, ADC7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PIN_DECL_(AE18, SIG_EXPR_LIST_PTR(AE18, GPIT7), SIG_EXPR_LIST_PTR(AE18, ADC7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) FUNC_GROUP_DECL(GPIT7, AE18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) FUNC_GROUP_DECL(ADC7, AE18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define AB16 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) SIG_EXPR_LIST_DECL_SEMG(AB16, SALT9, SALT9G1, SALT9, SIG_DESC_SET(SCU434, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) SIG_DESC_CLEAR(SCU694, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) SIG_EXPR_LIST_DECL_SESG(AB16, GPIU0, GPIU0, SIG_DESC_SET(SCU434, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) SIG_DESC_SET(SCU694, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) SIG_EXPR_LIST_DECL_SESG(AB16, ADC8, ADC8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PIN_DECL_(AB16, SIG_EXPR_LIST_PTR(AB16, SALT9), SIG_EXPR_LIST_PTR(AB16, GPIU0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) SIG_EXPR_LIST_PTR(AB16, ADC8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) GROUP_DECL(SALT9G1, AB16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) FUNC_DECL_2(SALT9, SALT9G0, SALT9G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) FUNC_GROUP_DECL(GPIU0, AB16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) FUNC_GROUP_DECL(ADC8, AB16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define AA17 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) SIG_EXPR_LIST_DECL_SEMG(AA17, SALT10, SALT10G1, SALT10, SIG_DESC_SET(SCU434, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) SIG_DESC_CLEAR(SCU694, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) SIG_EXPR_LIST_DECL_SESG(AA17, GPIU1, GPIU1, SIG_DESC_SET(SCU434, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) SIG_DESC_SET(SCU694, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) SIG_EXPR_LIST_DECL_SESG(AA17, ADC9, ADC9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) PIN_DECL_(AA17, SIG_EXPR_LIST_PTR(AA17, SALT10), SIG_EXPR_LIST_PTR(AA17, GPIU1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) SIG_EXPR_LIST_PTR(AA17, ADC9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) GROUP_DECL(SALT10G1, AA17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) FUNC_DECL_2(SALT10, SALT10G0, SALT10G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) FUNC_GROUP_DECL(GPIU1, AA17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) FUNC_GROUP_DECL(ADC9, AA17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define AB17 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) SIG_EXPR_LIST_DECL_SEMG(AB17, SALT11, SALT11G1, SALT11, SIG_DESC_SET(SCU434, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) SIG_DESC_CLEAR(SCU694, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) SIG_EXPR_LIST_DECL_SESG(AB17, GPIU2, GPIU2, SIG_DESC_SET(SCU434, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) SIG_DESC_SET(SCU694, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) SIG_EXPR_LIST_DECL_SESG(AB17, ADC10, ADC10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PIN_DECL_(AB17, SIG_EXPR_LIST_PTR(AB17, SALT11), SIG_EXPR_LIST_PTR(AB17, GPIU2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) SIG_EXPR_LIST_PTR(AB17, ADC10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) GROUP_DECL(SALT11G1, AB17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) FUNC_DECL_2(SALT11, SALT11G0, SALT11G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) FUNC_GROUP_DECL(GPIU2, AB17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) FUNC_GROUP_DECL(ADC10, AB17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define AE16 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) SIG_EXPR_LIST_DECL_SEMG(AE16, SALT12, SALT12G1, SALT12, SIG_DESC_SET(SCU434, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) SIG_DESC_CLEAR(SCU694, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) SIG_EXPR_LIST_DECL_SESG(AE16, GPIU3, GPIU3, SIG_DESC_SET(SCU434, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) SIG_DESC_SET(SCU694, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) SIG_EXPR_LIST_DECL_SESG(AE16, ADC11, ADC11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PIN_DECL_(AE16, SIG_EXPR_LIST_PTR(AE16, SALT12), SIG_EXPR_LIST_PTR(AE16, GPIU3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) SIG_EXPR_LIST_PTR(AE16, ADC11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) GROUP_DECL(SALT12G1, AE16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) FUNC_DECL_2(SALT12, SALT12G0, SALT12G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) FUNC_GROUP_DECL(GPIU3, AE16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) FUNC_GROUP_DECL(ADC11, AE16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define AC16 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) SIG_EXPR_LIST_DECL_SEMG(AC16, SALT13, SALT13G1, SALT13, SIG_DESC_SET(SCU434, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) SIG_DESC_CLEAR(SCU694, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) SIG_EXPR_LIST_DECL_SESG(AC16, GPIU4, GPIU4, SIG_DESC_SET(SCU434, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) SIG_DESC_SET(SCU694, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) SIG_EXPR_LIST_DECL_SESG(AC16, ADC12, ADC12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PIN_DECL_(AC16, SIG_EXPR_LIST_PTR(AC16, SALT13), SIG_EXPR_LIST_PTR(AC16, GPIU4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) SIG_EXPR_LIST_PTR(AC16, ADC12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) GROUP_DECL(SALT13G1, AC16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) FUNC_DECL_2(SALT13, SALT13G0, SALT13G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) FUNC_GROUP_DECL(GPIU4, AC16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) FUNC_GROUP_DECL(ADC12, AC16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #define AA16 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) SIG_EXPR_LIST_DECL_SEMG(AA16, SALT14, SALT14G1, SALT14, SIG_DESC_SET(SCU434, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) SIG_DESC_CLEAR(SCU694, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) SIG_EXPR_LIST_DECL_SESG(AA16, GPIU5, GPIU5, SIG_DESC_SET(SCU434, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) SIG_DESC_SET(SCU694, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) SIG_EXPR_LIST_DECL_SESG(AA16, ADC13, ADC13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PIN_DECL_(AA16, SIG_EXPR_LIST_PTR(AA16, SALT14), SIG_EXPR_LIST_PTR(AA16, GPIU5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) SIG_EXPR_LIST_PTR(AA16, ADC13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) GROUP_DECL(SALT14G1, AA16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) FUNC_DECL_2(SALT14, SALT14G0, SALT14G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) FUNC_GROUP_DECL(GPIU5, AA16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) FUNC_GROUP_DECL(ADC13, AA16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define AD16 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) SIG_EXPR_LIST_DECL_SEMG(AD16, SALT15, SALT15G1, SALT15, SIG_DESC_SET(SCU434, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) SIG_DESC_CLEAR(SCU694, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) SIG_EXPR_LIST_DECL_SESG(AD16, GPIU6, GPIU6, SIG_DESC_SET(SCU434, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) SIG_DESC_SET(SCU694, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) SIG_EXPR_LIST_DECL_SESG(AD16, ADC14, ADC14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) PIN_DECL_(AD16, SIG_EXPR_LIST_PTR(AD16, SALT15), SIG_EXPR_LIST_PTR(AD16, GPIU6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) SIG_EXPR_LIST_PTR(AD16, ADC14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) GROUP_DECL(SALT15G1, AD16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) FUNC_DECL_2(SALT15, SALT15G0, SALT15G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) FUNC_GROUP_DECL(GPIU6, AD16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) FUNC_GROUP_DECL(ADC14, AD16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define AC17 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) SIG_EXPR_LIST_DECL_SEMG(AC17, SALT16, SALT16G1, SALT16, SIG_DESC_SET(SCU434, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) SIG_DESC_CLEAR(SCU694, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) SIG_EXPR_LIST_DECL_SESG(AC17, GPIU7, GPIU7, SIG_DESC_SET(SCU434, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) SIG_DESC_SET(SCU694, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) SIG_EXPR_LIST_DECL_SESG(AC17, ADC15, ADC15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PIN_DECL_(AC17, SIG_EXPR_LIST_PTR(AC17, SALT16), SIG_EXPR_LIST_PTR(AC17, GPIU7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) SIG_EXPR_LIST_PTR(AC17, ADC15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) GROUP_DECL(SALT16G1, AC17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) FUNC_DECL_2(SALT16, SALT16G0, SALT16G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) FUNC_GROUP_DECL(GPIU7, AC17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) FUNC_GROUP_DECL(ADC15, AC17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define AB15 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) SSSF_PIN_DECL(AB15, GPIOV0, SIOS3, SIG_DESC_SET(SCU434, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define AF14 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) SSSF_PIN_DECL(AF14, GPIOV1, SIOS5, SIG_DESC_SET(SCU434, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define AD14 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) SSSF_PIN_DECL(AD14, GPIOV2, SIOPWREQ, SIG_DESC_SET(SCU434, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define AC15 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) SSSF_PIN_DECL(AC15, GPIOV3, SIOONCTRL, SIG_DESC_SET(SCU434, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define AE15 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) SSSF_PIN_DECL(AE15, GPIOV4, SIOPWRGD, SIG_DESC_SET(SCU434, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define AE14 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) SIG_EXPR_LIST_DECL_SESG(AE14, LPCPD, LPCPD, SIG_DESC_SET(SCU434, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) SIG_EXPR_LIST_DECL_SESG(AE14, LHPD, LHPD, SIG_DESC_SET(SCU4D4, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) PIN_DECL_2(AE14, GPIOV5, LPCPD, LHPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) FUNC_GROUP_DECL(LPCPD, AE14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) FUNC_GROUP_DECL(LHPD, AE14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define AD15 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) SSSF_PIN_DECL(AD15, GPIOV6, LPCPME, SIG_DESC_SET(SCU434, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define AF15 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) SSSF_PIN_DECL(AF15, GPIOV7, LPCSMI, SIG_DESC_SET(SCU434, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define AB7 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) SIG_EXPR_LIST_DECL_SESG(AB7, LAD0, LPC, SIG_DESC_SET(SCU434, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) SIG_DESC_SET(SCU510, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) SIG_EXPR_LIST_DECL_SESG(AB7, ESPID0, ESPI, SIG_DESC_SET(SCU434, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PIN_DECL_2(AB7, GPIOW0, LAD0, ESPID0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define AB8 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) SIG_EXPR_LIST_DECL_SESG(AB8, LAD1, LPC, SIG_DESC_SET(SCU434, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) SIG_DESC_SET(SCU510, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) SIG_EXPR_LIST_DECL_SESG(AB8, ESPID1, ESPI, SIG_DESC_SET(SCU434, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PIN_DECL_2(AB8, GPIOW1, LAD1, ESPID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define AC8 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) SIG_EXPR_LIST_DECL_SESG(AC8, LAD2, LPC, SIG_DESC_SET(SCU434, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) SIG_DESC_SET(SCU510, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) SIG_EXPR_LIST_DECL_SESG(AC8, ESPID2, ESPI, SIG_DESC_SET(SCU434, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) PIN_DECL_2(AC8, GPIOW2, LAD2, ESPID2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define AC7 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) SIG_EXPR_LIST_DECL_SESG(AC7, LAD3, LPC, SIG_DESC_SET(SCU434, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) SIG_DESC_SET(SCU510, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) SIG_EXPR_LIST_DECL_SESG(AC7, ESPID3, ESPI, SIG_DESC_SET(SCU434, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PIN_DECL_2(AC7, GPIOW3, LAD3, ESPID3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define AE7 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) SIG_EXPR_LIST_DECL_SESG(AE7, LCLK, LPC, SIG_DESC_SET(SCU434, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) SIG_DESC_SET(SCU510, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) SIG_EXPR_LIST_DECL_SESG(AE7, ESPICK, ESPI, SIG_DESC_SET(SCU434, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PIN_DECL_2(AE7, GPIOW4, LCLK, ESPICK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define AF7 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) SIG_EXPR_LIST_DECL_SESG(AF7, LFRAME, LPC, SIG_DESC_SET(SCU434, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) SIG_DESC_SET(SCU510, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) SIG_EXPR_LIST_DECL_SESG(AF7, ESPICS, ESPI, SIG_DESC_SET(SCU434, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PIN_DECL_2(AF7, GPIOW5, LFRAME, ESPICS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define AD7 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) SIG_EXPR_LIST_DECL_SESG(AD7, LSIRQ, LSIRQ, SIG_DESC_SET(SCU434, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) SIG_DESC_SET(SCU510, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) SIG_EXPR_LIST_DECL_SESG(AD7, ESPIALT, ESPIALT, SIG_DESC_SET(SCU434, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PIN_DECL_2(AD7, GPIOW6, LSIRQ, ESPIALT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) FUNC_GROUP_DECL(LSIRQ, AD7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) FUNC_GROUP_DECL(ESPIALT, AD7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define AD8 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) SIG_EXPR_LIST_DECL_SESG(AD8, LPCRST, LPC, SIG_DESC_SET(SCU434, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) SIG_DESC_SET(SCU510, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) SIG_EXPR_LIST_DECL_SESG(AD8, ESPIRST, ESPI, SIG_DESC_SET(SCU434, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PIN_DECL_2(AD8, GPIOW7, LPCRST, ESPIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) FUNC_GROUP_DECL(LPC, AB7, AB8, AC8, AC7, AE7, AF7, AD8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) FUNC_GROUP_DECL(ESPI, AB7, AB8, AC8, AC7, AE7, AF7, AD8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define AE8 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) SIG_EXPR_LIST_DECL_SEMG(AE8, SPI2CS0, SPI2, SPI2, SIG_DESC_SET(SCU434, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PIN_DECL_1(AE8, GPIOX0, SPI2CS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define AA9 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) SSSF_PIN_DECL(AA9, GPIOX1, SPI2CS1, SIG_DESC_SET(SCU434, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define AC9 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) SSSF_PIN_DECL(AC9, GPIOX2, SPI2CS2, SIG_DESC_SET(SCU434, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define AF8 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) SIG_EXPR_LIST_DECL_SEMG(AF8, SPI2CK, SPI2, SPI2, SIG_DESC_SET(SCU434, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PIN_DECL_1(AF8, GPIOX3, SPI2CK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define AB9 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) SIG_EXPR_LIST_DECL_SEMG(AB9, SPI2MOSI, SPI2, SPI2, SIG_DESC_SET(SCU434, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PIN_DECL_1(AB9, GPIOX4, SPI2MOSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define AD9 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) SIG_EXPR_LIST_DECL_SEMG(AD9, SPI2MISO, SPI2, SPI2, SIG_DESC_SET(SCU434, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PIN_DECL_1(AD9, GPIOX5, SPI2MISO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) GROUP_DECL(SPI2, AE8, AF8, AB9, AD9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define AF9 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) SIG_EXPR_LIST_DECL_SEMG(AF9, SPI2DQ2, QSPI2, SPI2, SIG_DESC_SET(SCU434, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) SIG_EXPR_LIST_DECL_SEMG(AF9, TXD12, UART12G1, UART12, SIG_DESC_SET(SCU4D4, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PIN_DECL_2(AF9, GPIOX6, SPI2DQ2, TXD12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define AB10 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) SIG_EXPR_LIST_DECL_SEMG(AB10, SPI2DQ3, QSPI2, SPI2, SIG_DESC_SET(SCU434, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) SIG_EXPR_LIST_DECL_SEMG(AB10, RXD12, UART12G1, UART12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) SIG_DESC_SET(SCU4D4, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PIN_DECL_2(AB10, GPIOX7, SPI2DQ3, RXD12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) GROUP_DECL(QSPI2, AE8, AF8, AB9, AD9, AF9, AB10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) FUNC_DECL_2(SPI2, SPI2, QSPI2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) GROUP_DECL(UART12G1, AF9, AB10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) FUNC_DECL_2(UART12, UART12G0, UART12G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define AF11 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) SIG_EXPR_LIST_DECL_SESG(AF11, SALT5, SALT5, SIG_DESC_SET(SCU438, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) SIG_EXPR_LIST_DECL_SESG(AF11, WDTRST1, WDTRST1, SIG_DESC_SET(SCU4D8, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PIN_DECL_2(AF11, GPIOY0, SALT5, WDTRST1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) FUNC_GROUP_DECL(SALT5, AF11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) FUNC_GROUP_DECL(WDTRST1, AF11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define AD12 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) SIG_EXPR_LIST_DECL_SESG(AD12, SALT6, SALT6, SIG_DESC_SET(SCU438, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) SIG_EXPR_LIST_DECL_SESG(AD12, WDTRST2, WDTRST2, SIG_DESC_SET(SCU4D8, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PIN_DECL_2(AD12, GPIOY1, SALT6, WDTRST2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) FUNC_GROUP_DECL(SALT6, AD12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) FUNC_GROUP_DECL(WDTRST2, AD12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define AE11 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) SIG_EXPR_LIST_DECL_SESG(AE11, SALT7, SALT7, SIG_DESC_SET(SCU438, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) SIG_EXPR_LIST_DECL_SESG(AE11, WDTRST3, WDTRST3, SIG_DESC_SET(SCU4D8, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PIN_DECL_2(AE11, GPIOY2, SALT7, WDTRST3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) FUNC_GROUP_DECL(SALT7, AE11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) FUNC_GROUP_DECL(WDTRST3, AE11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define AA12 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) SIG_EXPR_LIST_DECL_SESG(AA12, SALT8, SALT8, SIG_DESC_SET(SCU438, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) SIG_EXPR_LIST_DECL_SESG(AA12, WDTRST4, WDTRST4, SIG_DESC_SET(SCU4D8, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PIN_DECL_2(AA12, GPIOY3, SALT8, WDTRST4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) FUNC_GROUP_DECL(SALT8, AA12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) FUNC_GROUP_DECL(WDTRST4, AA12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define AE12 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) SIG_EXPR_LIST_DECL_SEMG(AE12, FWSPIDQ2, FWQSPID, FWSPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) SIG_DESC_SET(SCU438, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIDQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) SIG_EXPR_LIST_PTR(AE12, GPIOY4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define AF12 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) SIG_EXPR_LIST_DECL_SEMG(AF12, FWSPIDQ3, FWQSPID, FWSPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) SIG_DESC_SET(SCU438, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIDQ3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) SIG_EXPR_LIST_PTR(AF12, GPIOY5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define AC12 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define AB12 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) SSSF_PIN_DECL(AB12, GPIOY7, FWSPIWP, SIG_DESC_SET(SCU438, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define AC10 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) SSSF_PIN_DECL(AC10, GPIOZ0, SPI1CS1, SIG_DESC_SET(SCU438, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define AD10 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) SSSF_PIN_DECL(AD10, GPIOZ1, SPI1ABR, SIG_DESC_SET(SCU438, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define AE10 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) SSSF_PIN_DECL(AE10, GPIOZ2, SPI1WP, SIG_DESC_SET(SCU438, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define AB11 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) SIG_EXPR_LIST_DECL_SEMG(AB11, SPI1CK, SPI1, SPI1, SIG_DESC_SET(SCU438, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PIN_DECL_1(AB11, GPIOZ3, SPI1CK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define AC11 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) SIG_EXPR_LIST_DECL_SEMG(AC11, SPI1MOSI, SPI1, SPI1, SIG_DESC_SET(SCU438, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) PIN_DECL_1(AC11, GPIOZ4, SPI1MOSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define AA11 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) SIG_EXPR_LIST_DECL_SEMG(AA11, SPI1MISO, SPI1, SPI1, SIG_DESC_SET(SCU438, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) PIN_DECL_1(AA11, GPIOZ5, SPI1MISO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) GROUP_DECL(SPI1, AB11, AC11, AA11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define AD11 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) SIG_EXPR_LIST_DECL_SEMG(AD11, SPI1DQ2, QSPI1, SPI1, SIG_DESC_SET(SCU438, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) SIG_EXPR_LIST_DECL_SEMG(AD11, TXD13, UART13G1, UART13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) SIG_DESC_CLEAR(SCU4B8, 2), SIG_DESC_SET(SCU4D8, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) PIN_DECL_2(AD11, GPIOZ6, SPI1DQ2, TXD13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define AF10 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) SIG_EXPR_LIST_DECL_SEMG(AF10, SPI1DQ3, QSPI1, SPI1, SIG_DESC_SET(SCU438, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) SIG_EXPR_LIST_DECL_SEMG(AF10, RXD13, UART13G1, UART13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) SIG_DESC_CLEAR(SCU4B8, 3), SIG_DESC_SET(SCU4D8, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) PIN_DECL_2(AF10, GPIOZ7, SPI1DQ3, RXD13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) GROUP_DECL(QSPI1, AB11, AC11, AA11, AD11, AF10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) FUNC_DECL_2(SPI1, SPI1, QSPI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) GROUP_DECL(UART13G1, AD11, AF10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) FUNC_DECL_2(UART13, UART13G0, UART13G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define C6 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) SIG_EXPR_LIST_DECL_SESG(C6, RGMII1TXCK, RGMII1, SIG_DESC_SET(SCU400, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) SIG_DESC_SET(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) SIG_EXPR_LIST_DECL_SESG(C6, RMII1RCLKO, RMII1, SIG_DESC_SET(SCU400, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) SIG_DESC_CLEAR(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PIN_DECL_2(C6, GPIO18A0, RGMII1TXCK, RMII1RCLKO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define D6 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) SIG_EXPR_LIST_DECL_SESG(D6, RGMII1TXCTL, RGMII1, SIG_DESC_SET(SCU400, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) SIG_DESC_SET(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) SIG_EXPR_LIST_DECL_SESG(D6, RMII1TXEN, RMII1, SIG_DESC_SET(SCU400, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) SIG_DESC_CLEAR(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) PIN_DECL_2(D6, GPIO18A1, RGMII1TXCTL, RMII1TXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define D5 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) SIG_EXPR_LIST_DECL_SESG(D5, RGMII1TXD0, RGMII1, SIG_DESC_SET(SCU400, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) SIG_DESC_SET(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) SIG_EXPR_LIST_DECL_SESG(D5, RMII1TXD0, RMII1, SIG_DESC_SET(SCU400, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) SIG_DESC_CLEAR(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) PIN_DECL_2(D5, GPIO18A2, RGMII1TXD0, RMII1TXD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define A3 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) SIG_EXPR_LIST_DECL_SESG(A3, RGMII1TXD1, RGMII1, SIG_DESC_SET(SCU400, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) SIG_DESC_SET(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) SIG_EXPR_LIST_DECL_SESG(A3, RMII1TXD1, RMII1, SIG_DESC_SET(SCU400, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) SIG_DESC_CLEAR(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) PIN_DECL_2(A3, GPIO18A3, RGMII1TXD1, RMII1TXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define C5 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) SIG_EXPR_LIST_DECL_SESG(C5, RGMII1TXD2, RGMII1, SIG_DESC_SET(SCU400, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) SIG_DESC_SET(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PIN_DECL_1(C5, GPIO18A4, RGMII1TXD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define E6 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) SIG_EXPR_LIST_DECL_SESG(E6, RGMII1TXD3, RGMII1, SIG_DESC_SET(SCU400, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) SIG_DESC_SET(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) PIN_DECL_1(E6, GPIO18A5, RGMII1TXD3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define B3 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) SIG_EXPR_LIST_DECL_SESG(B3, RGMII1RXCK, RGMII1, SIG_DESC_SET(SCU400, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) SIG_DESC_SET(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) SIG_EXPR_LIST_DECL_SESG(B3, RMII1RCLKI, RMII1, SIG_DESC_SET(SCU400, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) SIG_DESC_CLEAR(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) PIN_DECL_2(B3, GPIO18A6, RGMII1RXCK, RMII1RCLKI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define A2 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) SIG_EXPR_LIST_DECL_SESG(A2, RGMII1RXCTL, RGMII1, SIG_DESC_SET(SCU400, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) SIG_DESC_SET(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PIN_DECL_1(A2, GPIO18A7, RGMII1RXCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define B2 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) SIG_EXPR_LIST_DECL_SESG(B2, RGMII1RXD0, RGMII1, SIG_DESC_SET(SCU400, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) SIG_DESC_SET(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) SIG_EXPR_LIST_DECL_SESG(B2, RMII1RXD0, RMII1, SIG_DESC_SET(SCU400, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) SIG_DESC_CLEAR(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PIN_DECL_2(B2, GPIO18B0, RGMII1RXD0, RMII1RXD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define B1 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) SIG_EXPR_LIST_DECL_SESG(B1, RGMII1RXD1, RGMII1, SIG_DESC_SET(SCU400, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) SIG_DESC_SET(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) SIG_EXPR_LIST_DECL_SESG(B1, RMII1RXD1, RMII1, SIG_DESC_SET(SCU400, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) SIG_DESC_CLEAR(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PIN_DECL_2(B1, GPIO18B1, RGMII1RXD1, RMII1RXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define C4 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) SIG_EXPR_LIST_DECL_SESG(C4, RGMII1RXD2, RGMII1, SIG_DESC_SET(SCU400, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) SIG_DESC_SET(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) SIG_EXPR_LIST_DECL_SESG(C4, RMII1CRSDV, RMII1, SIG_DESC_SET(SCU400, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) SIG_DESC_CLEAR(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PIN_DECL_2(C4, GPIO18B2, RGMII1RXD2, RMII1CRSDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define E5 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) SIG_EXPR_LIST_DECL_SESG(E5, RGMII1RXD3, RGMII1, SIG_DESC_SET(SCU400, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) SIG_DESC_SET(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) SIG_EXPR_LIST_DECL_SESG(E5, RMII1RXER, RMII1, SIG_DESC_SET(SCU400, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) SIG_DESC_CLEAR(SCU500, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PIN_DECL_2(E5, GPIO18B3, RGMII1RXD3, RMII1RXER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) FUNC_GROUP_DECL(RGMII1, C6, D6, D5, A3, C5, E6, B3, A2, B2, B1, C4, E5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) FUNC_GROUP_DECL(RMII1, C6, D6, D5, A3, B3, B2, B1, C4, E5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define D4 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) SIG_EXPR_LIST_DECL_SESG(D4, RGMII2TXCK, RGMII2, SIG_DESC_SET(SCU400, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) SIG_DESC_SET(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) SIG_EXPR_LIST_DECL_SESG(D4, RMII2RCLKO, RMII2, SIG_DESC_SET(SCU400, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) SIG_DESC_CLEAR(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) PIN_DECL_2(D4, GPIO18B4, RGMII2TXCK, RMII2RCLKO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define C2 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) SIG_EXPR_LIST_DECL_SESG(C2, RGMII2TXCTL, RGMII2, SIG_DESC_SET(SCU400, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) SIG_DESC_SET(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) SIG_EXPR_LIST_DECL_SESG(C2, RMII2TXEN, RMII2, SIG_DESC_SET(SCU400, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) SIG_DESC_CLEAR(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) PIN_DECL_2(C2, GPIO18B5, RGMII2TXCTL, RMII2TXEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define C1 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) SIG_EXPR_LIST_DECL_SESG(C1, RGMII2TXD0, RGMII2, SIG_DESC_SET(SCU400, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) SIG_DESC_SET(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) SIG_EXPR_LIST_DECL_SESG(C1, RMII2TXD0, RMII2, SIG_DESC_SET(SCU400, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) SIG_DESC_CLEAR(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PIN_DECL_2(C1, GPIO18B6, RGMII2TXD0, RMII2TXD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define D3 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) SIG_EXPR_LIST_DECL_SESG(D3, RGMII2TXD1, RGMII2, SIG_DESC_SET(SCU400, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) SIG_DESC_SET(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) SIG_EXPR_LIST_DECL_SESG(D3, RMII2TXD1, RMII2, SIG_DESC_SET(SCU400, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) SIG_DESC_CLEAR(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) PIN_DECL_2(D3, GPIO18B7, RGMII2TXD1, RMII2TXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define E4 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) SIG_EXPR_LIST_DECL_SESG(E4, RGMII2TXD2, RGMII2, SIG_DESC_SET(SCU400, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) SIG_DESC_SET(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) PIN_DECL_1(E4, GPIO18C0, RGMII2TXD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define F5 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) SIG_EXPR_LIST_DECL_SESG(F5, RGMII2TXD3, RGMII2, SIG_DESC_SET(SCU400, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) SIG_DESC_SET(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) PIN_DECL_1(F5, GPIO18C1, RGMII2TXD3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define D2 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) SIG_EXPR_LIST_DECL_SESG(D2, RGMII2RXCK, RGMII2, SIG_DESC_SET(SCU400, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) SIG_DESC_SET(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) SIG_EXPR_LIST_DECL_SESG(D2, RMII2RCLKI, RMII2, SIG_DESC_SET(SCU400, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) SIG_DESC_CLEAR(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) PIN_DECL_2(D2, GPIO18C2, RGMII2RXCK, RMII2RCLKI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define E3 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) SIG_EXPR_LIST_DECL_SESG(E3, RGMII2RXCTL, RGMII2, SIG_DESC_SET(SCU400, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) SIG_DESC_SET(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) PIN_DECL_1(E3, GPIO18C3, RGMII2RXCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define D1 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) SIG_EXPR_LIST_DECL_SESG(D1, RGMII2RXD0, RGMII2, SIG_DESC_SET(SCU400, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) SIG_DESC_SET(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) SIG_EXPR_LIST_DECL_SESG(D1, RMII2RXD0, RMII2, SIG_DESC_SET(SCU400, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) SIG_DESC_CLEAR(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) PIN_DECL_2(D1, GPIO18C4, RGMII2RXD0, RMII2RXD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define F4 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) SIG_EXPR_LIST_DECL_SESG(F4, RGMII2RXD1, RGMII2, SIG_DESC_SET(SCU400, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) SIG_DESC_SET(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) SIG_EXPR_LIST_DECL_SESG(F4, RMII2RXD1, RMII2, SIG_DESC_SET(SCU400, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) SIG_DESC_CLEAR(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) PIN_DECL_2(F4, GPIO18C5, RGMII2RXD1, RMII2RXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define E2 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) SIG_EXPR_LIST_DECL_SESG(E2, RGMII2RXD2, RGMII2, SIG_DESC_SET(SCU400, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) SIG_DESC_SET(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) SIG_EXPR_LIST_DECL_SESG(E2, RMII2CRSDV, RMII2, SIG_DESC_SET(SCU400, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) SIG_DESC_CLEAR(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) PIN_DECL_2(E2, GPIO18C6, RGMII2RXD2, RMII2CRSDV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define E1 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) SIG_EXPR_LIST_DECL_SESG(E1, RGMII2RXD3, RGMII2, SIG_DESC_SET(SCU400, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) SIG_DESC_SET(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) SIG_EXPR_LIST_DECL_SESG(E1, RMII2RXER, RMII2, SIG_DESC_SET(SCU400, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) SIG_DESC_CLEAR(SCU500, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) PIN_DECL_2(E1, GPIO18C7, RGMII2RXD3, RMII2RXER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define AB4 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) SIG_EXPR_LIST_DECL_SEMG(AB4, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) PIN_DECL_1(AB4, GPIO18D0, EMMCCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define AA4 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) SIG_EXPR_LIST_DECL_SEMG(AA4, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) PIN_DECL_1(AA4, GPIO18D1, EMMCCMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define AC4 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) SIG_EXPR_LIST_DECL_SEMG(AC4, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) PIN_DECL_1(AC4, GPIO18D2, EMMCDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define AA5 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) SIG_EXPR_LIST_DECL_SEMG(AA5, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) PIN_DECL_1(AA5, GPIO18D3, EMMCDAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define Y5 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) SIG_EXPR_LIST_DECL_SEMG(Y5, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) PIN_DECL_1(Y5, GPIO18D4, EMMCDAT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define AB5 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) SIG_EXPR_LIST_DECL_SEMG(AB5, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) PIN_DECL_1(AB5, GPIO18D5, EMMCDAT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define AB6 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) SIG_EXPR_LIST_DECL_SEMG(AB6, EMMCCD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) PIN_DECL_1(AB6, GPIO18D6, EMMCCD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define AC5 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) SIG_EXPR_LIST_DECL_SEMG(AC5, EMMCWP, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) PIN_DECL_1(AC5, GPIO18D7, EMMCWP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) GROUP_DECL(EMMCG1, AB4, AA4, AC4, AB6, AC5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) GROUP_DECL(EMMCG4, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #define Y1 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) SIG_EXPR_LIST_DECL_SEMG(Y1, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, EMMCDAT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #define Y2 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) SIG_EXPR_LIST_DECL_SEMG(Y2, FWSPIDCK, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) SIG_EXPR_LIST_DECL_SESG(Y2, VBCK, VB, SIG_DESC_SET(SCU500, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) SIG_EXPR_LIST_DECL_SEMG(Y2, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, EMMCDAT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define Y3 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) SIG_EXPR_LIST_DECL_SEMG(Y3, FWSPIDMOSI, FWSPID, FWSPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) SIG_DESC_SET(SCU500, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) SIG_EXPR_LIST_DECL_SESG(Y3, VBMOSI, VB, SIG_DESC_SET(SCU500, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) SIG_EXPR_LIST_DECL_SEMG(Y3, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, EMMCDAT6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define Y4 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) SIG_EXPR_LIST_DECL_SEMG(Y4, FWSPIDMISO, FWSPID, FWSPID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) SIG_DESC_SET(SCU500, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) SIG_EXPR_LIST_DECL_SESG(Y4, VBMISO, VB, SIG_DESC_SET(SCU500, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) FUNC_DECL_2(FWSPID, FWSPID, FWQSPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * FIXME: Confirm bits and priorities are the right way around for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) * following 4 pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define AF25 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_SET(SCU4D8, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) PIN_DECL_(AF25, SIG_EXPR_LIST_PTR(AF25, I3C3SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) SIG_EXPR_LIST_PTR(AF25, FSI1CLK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define AE26 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_SET(SCU4D8, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) PIN_DECL_(AE26, SIG_EXPR_LIST_PTR(AE26, I3C3SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) SIG_EXPR_LIST_PTR(AE26, FSI1DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) GROUP_DECL(I3C3, AF25, AE26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) FUNC_DECL_2(I3C3, HVI3C3, I3C3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) FUNC_GROUP_DECL(FSI1, AF25, AE26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define AE25 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_SET(SCU4D8, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) PIN_DECL_(AE25, SIG_EXPR_LIST_PTR(AE25, I3C4SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) SIG_EXPR_LIST_PTR(AE25, FSI2CLK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) #define AF24 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_SET(SCU4D8, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) PIN_DECL_(AF24, SIG_EXPR_LIST_PTR(AF24, I3C4SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) SIG_EXPR_LIST_PTR(AF24, FSI2DATA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) GROUP_DECL(I3C4, AE25, AF24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) FUNC_DECL_2(I3C4, HVI3C4, I3C4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) FUNC_GROUP_DECL(FSI2, AE25, AF24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define AF23 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) SIG_EXPR_LIST_DECL_SESG(AF23, I3C1SCL, I3C1, SIG_DESC_SET(SCU438, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) PIN_DECL_(AF23, SIG_EXPR_LIST_PTR(AF23, I3C1SCL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) #define AE24 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) SIG_EXPR_LIST_DECL_SESG(AE24, I3C1SDA, I3C1, SIG_DESC_SET(SCU438, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) PIN_DECL_(AE24, SIG_EXPR_LIST_PTR(AE24, I3C1SDA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) FUNC_GROUP_DECL(I3C1, AF23, AE24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) #define AF22 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) SIG_EXPR_LIST_DECL_SESG(AF22, I3C2SCL, I3C2, SIG_DESC_SET(SCU438, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) PIN_DECL_(AF22, SIG_EXPR_LIST_PTR(AF22, I3C2SCL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) #define AE22 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) SIG_EXPR_LIST_DECL_SESG(AE22, I3C2SDA, I3C2, SIG_DESC_SET(SCU438, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) PIN_DECL_(AE22, SIG_EXPR_LIST_PTR(AE22, I3C2SDA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) FUNC_GROUP_DECL(I3C2, AF22, AE22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define USB2ADP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) #define USB2AD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 1, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #define USB2AH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 2, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define USB2AHP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 3, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #define USB11BHID_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #define USB2BD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 1, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) #define USB2BH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 2, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #define A4 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADPDP, USBA, USB2ADP, USB2ADP_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) SIG_DESC_SET(SCUC20, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADDP, USBA, USB2AD, USB2AD_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHDP, USBA, USB2AH, USB2AH_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, USB2ADPDP), SIG_EXPR_LIST_PTR(A4, USB2ADDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) SIG_EXPR_LIST_PTR(A4, USB2AHDP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) #define B4 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADPDN, USBA, USB2ADP, USB2ADP_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADDN, USBA, USB2AD, USB2AD_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHDN, USBA, USB2AH, USB2AH_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHPDN, USBA, USB2AHP, USB2AHP_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, USB2ADPDN), SIG_EXPR_LIST_PTR(B4, USB2ADDN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) SIG_EXPR_LIST_PTR(B4, USB2AHDN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) GROUP_DECL(USBA, A4, B4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) FUNC_DECL_1(USB2ADP, USBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) FUNC_DECL_1(USB2AD, USBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) FUNC_DECL_1(USB2AH, USBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) FUNC_DECL_1(USB2AHP, USBA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define A6 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) SIG_EXPR_LIST_DECL_SEMG(A6, USB11BDP, USBB, USB11BHID, USB11BHID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) SIG_EXPR_LIST_DECL_SEMG(A6, USB2BDDP, USBB, USB2BD, USB2BD_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) SIG_EXPR_LIST_DECL_SEMG(A6, USB2BHDP, USBB, USB2BH, USB2BH_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDP), SIG_EXPR_LIST_PTR(A6, USB2BDDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) SIG_EXPR_LIST_PTR(A6, USB2BHDP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define B6 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) SIG_EXPR_LIST_DECL_SEMG(B6, USB11BDN, USBB, USB11BHID, USB11BHID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) SIG_EXPR_LIST_DECL_SEMG(B6, USB2BDDN, USBB, USB2BD, USB2BD_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) SIG_EXPR_LIST_DECL_SEMG(B6, USB2BHDN, USBB, USB2BH, USB2BH_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDN), SIG_EXPR_LIST_PTR(B6, USB2BDDN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) SIG_EXPR_LIST_PTR(B6, USB2BHDN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) GROUP_DECL(USBB, A6, B6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) FUNC_DECL_1(USB11BHID, USBB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) FUNC_DECL_1(USB2BD, USBB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) FUNC_DECL_1(USB2BH, USBB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ASPEED_PINCTRL_PIN(A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) ASPEED_PINCTRL_PIN(A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) ASPEED_PINCTRL_PIN(A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) ASPEED_PINCTRL_PIN(A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) ASPEED_PINCTRL_PIN(A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) ASPEED_PINCTRL_PIN(A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) ASPEED_PINCTRL_PIN(A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ASPEED_PINCTRL_PIN(A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) ASPEED_PINCTRL_PIN(A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) ASPEED_PINCTRL_PIN(A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ASPEED_PINCTRL_PIN(A20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ASPEED_PINCTRL_PIN(A21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ASPEED_PINCTRL_PIN(A22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) ASPEED_PINCTRL_PIN(A23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ASPEED_PINCTRL_PIN(A24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) ASPEED_PINCTRL_PIN(A25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) ASPEED_PINCTRL_PIN(A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) ASPEED_PINCTRL_PIN(A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) ASPEED_PINCTRL_PIN(A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) ASPEED_PINCTRL_PIN(AA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ASPEED_PINCTRL_PIN(AA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ASPEED_PINCTRL_PIN(AA16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) ASPEED_PINCTRL_PIN(AA17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ASPEED_PINCTRL_PIN(AA23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) ASPEED_PINCTRL_PIN(AA24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) ASPEED_PINCTRL_PIN(AA25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) ASPEED_PINCTRL_PIN(AA26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) ASPEED_PINCTRL_PIN(AA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) ASPEED_PINCTRL_PIN(AA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) ASPEED_PINCTRL_PIN(AA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ASPEED_PINCTRL_PIN(AB10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) ASPEED_PINCTRL_PIN(AB11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) ASPEED_PINCTRL_PIN(AB12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ASPEED_PINCTRL_PIN(AB15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) ASPEED_PINCTRL_PIN(AB16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) ASPEED_PINCTRL_PIN(AB17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ASPEED_PINCTRL_PIN(AB18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) ASPEED_PINCTRL_PIN(AB19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ASPEED_PINCTRL_PIN(AB22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) ASPEED_PINCTRL_PIN(AB23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) ASPEED_PINCTRL_PIN(AB24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ASPEED_PINCTRL_PIN(AB25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) ASPEED_PINCTRL_PIN(AB26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) ASPEED_PINCTRL_PIN(AB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) ASPEED_PINCTRL_PIN(AB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) ASPEED_PINCTRL_PIN(AB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) ASPEED_PINCTRL_PIN(AB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) ASPEED_PINCTRL_PIN(AB8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) ASPEED_PINCTRL_PIN(AB9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) ASPEED_PINCTRL_PIN(AC10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ASPEED_PINCTRL_PIN(AC11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) ASPEED_PINCTRL_PIN(AC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) ASPEED_PINCTRL_PIN(AC15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) ASPEED_PINCTRL_PIN(AC16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ASPEED_PINCTRL_PIN(AC17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ASPEED_PINCTRL_PIN(AC18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ASPEED_PINCTRL_PIN(AC19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) ASPEED_PINCTRL_PIN(AC22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) ASPEED_PINCTRL_PIN(AC23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) ASPEED_PINCTRL_PIN(AC24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) ASPEED_PINCTRL_PIN(AC26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) ASPEED_PINCTRL_PIN(AC4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) ASPEED_PINCTRL_PIN(AC5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ASPEED_PINCTRL_PIN(AC7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) ASPEED_PINCTRL_PIN(AC8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) ASPEED_PINCTRL_PIN(AC9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) ASPEED_PINCTRL_PIN(AD10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) ASPEED_PINCTRL_PIN(AD11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) ASPEED_PINCTRL_PIN(AD12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) ASPEED_PINCTRL_PIN(AD14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) ASPEED_PINCTRL_PIN(AD15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) ASPEED_PINCTRL_PIN(AD16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) ASPEED_PINCTRL_PIN(AD19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ASPEED_PINCTRL_PIN(AD20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ASPEED_PINCTRL_PIN(AD22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) ASPEED_PINCTRL_PIN(AD23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) ASPEED_PINCTRL_PIN(AD24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) ASPEED_PINCTRL_PIN(AD25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) ASPEED_PINCTRL_PIN(AD26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) ASPEED_PINCTRL_PIN(AD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) ASPEED_PINCTRL_PIN(AD8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) ASPEED_PINCTRL_PIN(AD9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) ASPEED_PINCTRL_PIN(AE10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ASPEED_PINCTRL_PIN(AE11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) ASPEED_PINCTRL_PIN(AE12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) ASPEED_PINCTRL_PIN(AE14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ASPEED_PINCTRL_PIN(AE15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) ASPEED_PINCTRL_PIN(AE16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) ASPEED_PINCTRL_PIN(AE18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ASPEED_PINCTRL_PIN(AE19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) ASPEED_PINCTRL_PIN(AE22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) ASPEED_PINCTRL_PIN(AE24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) ASPEED_PINCTRL_PIN(AE25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) ASPEED_PINCTRL_PIN(AE26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) ASPEED_PINCTRL_PIN(AE7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) ASPEED_PINCTRL_PIN(AE8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) ASPEED_PINCTRL_PIN(AF10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) ASPEED_PINCTRL_PIN(AF11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) ASPEED_PINCTRL_PIN(AF12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ASPEED_PINCTRL_PIN(AF14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) ASPEED_PINCTRL_PIN(AF15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) ASPEED_PINCTRL_PIN(AF22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) ASPEED_PINCTRL_PIN(AF23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) ASPEED_PINCTRL_PIN(AF24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) ASPEED_PINCTRL_PIN(AF25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) ASPEED_PINCTRL_PIN(AF7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) ASPEED_PINCTRL_PIN(AF8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) ASPEED_PINCTRL_PIN(AF9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) ASPEED_PINCTRL_PIN(B1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) ASPEED_PINCTRL_PIN(B12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) ASPEED_PINCTRL_PIN(B13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) ASPEED_PINCTRL_PIN(B14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) ASPEED_PINCTRL_PIN(B16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) ASPEED_PINCTRL_PIN(B17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) ASPEED_PINCTRL_PIN(B18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) ASPEED_PINCTRL_PIN(B2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) ASPEED_PINCTRL_PIN(B20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) ASPEED_PINCTRL_PIN(B21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) ASPEED_PINCTRL_PIN(B22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) ASPEED_PINCTRL_PIN(B24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) ASPEED_PINCTRL_PIN(B25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) ASPEED_PINCTRL_PIN(B26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) ASPEED_PINCTRL_PIN(B3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) ASPEED_PINCTRL_PIN(B4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) ASPEED_PINCTRL_PIN(B6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) ASPEED_PINCTRL_PIN(C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) ASPEED_PINCTRL_PIN(C11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) ASPEED_PINCTRL_PIN(C12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) ASPEED_PINCTRL_PIN(C13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) ASPEED_PINCTRL_PIN(C14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) ASPEED_PINCTRL_PIN(C15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) ASPEED_PINCTRL_PIN(C16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) ASPEED_PINCTRL_PIN(C17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) ASPEED_PINCTRL_PIN(C18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) ASPEED_PINCTRL_PIN(C19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) ASPEED_PINCTRL_PIN(C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) ASPEED_PINCTRL_PIN(C20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) ASPEED_PINCTRL_PIN(C21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) ASPEED_PINCTRL_PIN(C22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) ASPEED_PINCTRL_PIN(C23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) ASPEED_PINCTRL_PIN(C24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) ASPEED_PINCTRL_PIN(C25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) ASPEED_PINCTRL_PIN(C26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) ASPEED_PINCTRL_PIN(C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) ASPEED_PINCTRL_PIN(C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) ASPEED_PINCTRL_PIN(C6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) ASPEED_PINCTRL_PIN(D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) ASPEED_PINCTRL_PIN(D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) ASPEED_PINCTRL_PIN(D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) ASPEED_PINCTRL_PIN(D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) ASPEED_PINCTRL_PIN(D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) ASPEED_PINCTRL_PIN(D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) ASPEED_PINCTRL_PIN(D16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) ASPEED_PINCTRL_PIN(D17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) ASPEED_PINCTRL_PIN(D18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) ASPEED_PINCTRL_PIN(D19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) ASPEED_PINCTRL_PIN(D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) ASPEED_PINCTRL_PIN(D20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) ASPEED_PINCTRL_PIN(D21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) ASPEED_PINCTRL_PIN(D22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) ASPEED_PINCTRL_PIN(D23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) ASPEED_PINCTRL_PIN(D24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) ASPEED_PINCTRL_PIN(D26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) ASPEED_PINCTRL_PIN(D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) ASPEED_PINCTRL_PIN(D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) ASPEED_PINCTRL_PIN(D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) ASPEED_PINCTRL_PIN(D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) ASPEED_PINCTRL_PIN(E1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) ASPEED_PINCTRL_PIN(E11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ASPEED_PINCTRL_PIN(E12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) ASPEED_PINCTRL_PIN(E13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ASPEED_PINCTRL_PIN(E14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ASPEED_PINCTRL_PIN(E15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) ASPEED_PINCTRL_PIN(E16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ASPEED_PINCTRL_PIN(E17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ASPEED_PINCTRL_PIN(E18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) ASPEED_PINCTRL_PIN(E19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) ASPEED_PINCTRL_PIN(E2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) ASPEED_PINCTRL_PIN(E20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) ASPEED_PINCTRL_PIN(E21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) ASPEED_PINCTRL_PIN(E22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) ASPEED_PINCTRL_PIN(E23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) ASPEED_PINCTRL_PIN(E24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) ASPEED_PINCTRL_PIN(E25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) ASPEED_PINCTRL_PIN(E26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) ASPEED_PINCTRL_PIN(E3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ASPEED_PINCTRL_PIN(E4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) ASPEED_PINCTRL_PIN(E5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) ASPEED_PINCTRL_PIN(E6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) ASPEED_PINCTRL_PIN(F13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) ASPEED_PINCTRL_PIN(F15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) ASPEED_PINCTRL_PIN(F22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) ASPEED_PINCTRL_PIN(F23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ASPEED_PINCTRL_PIN(F24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) ASPEED_PINCTRL_PIN(F25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) ASPEED_PINCTRL_PIN(F26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) ASPEED_PINCTRL_PIN(F4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) ASPEED_PINCTRL_PIN(F5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) ASPEED_PINCTRL_PIN(G22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) ASPEED_PINCTRL_PIN(G23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) ASPEED_PINCTRL_PIN(G24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) ASPEED_PINCTRL_PIN(G26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) ASPEED_PINCTRL_PIN(H22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) ASPEED_PINCTRL_PIN(H23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ASPEED_PINCTRL_PIN(H24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) ASPEED_PINCTRL_PIN(H25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) ASPEED_PINCTRL_PIN(H26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) ASPEED_PINCTRL_PIN(J22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) ASPEED_PINCTRL_PIN(J23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) ASPEED_PINCTRL_PIN(J24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ASPEED_PINCTRL_PIN(J25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) ASPEED_PINCTRL_PIN(J26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) ASPEED_PINCTRL_PIN(K23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) ASPEED_PINCTRL_PIN(K24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) ASPEED_PINCTRL_PIN(K25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ASPEED_PINCTRL_PIN(K26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) ASPEED_PINCTRL_PIN(L23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) ASPEED_PINCTRL_PIN(L24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) ASPEED_PINCTRL_PIN(L26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) ASPEED_PINCTRL_PIN(M23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) ASPEED_PINCTRL_PIN(M24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) ASPEED_PINCTRL_PIN(M25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) ASPEED_PINCTRL_PIN(M26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) ASPEED_PINCTRL_PIN(N23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) ASPEED_PINCTRL_PIN(N24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) ASPEED_PINCTRL_PIN(N25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) ASPEED_PINCTRL_PIN(N26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) ASPEED_PINCTRL_PIN(P23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) ASPEED_PINCTRL_PIN(P24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) ASPEED_PINCTRL_PIN(P25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) ASPEED_PINCTRL_PIN(P26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) ASPEED_PINCTRL_PIN(R23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) ASPEED_PINCTRL_PIN(R24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ASPEED_PINCTRL_PIN(R26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) ASPEED_PINCTRL_PIN(T23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ASPEED_PINCTRL_PIN(T24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) ASPEED_PINCTRL_PIN(T25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) ASPEED_PINCTRL_PIN(T26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) ASPEED_PINCTRL_PIN(U24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ASPEED_PINCTRL_PIN(U25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) ASPEED_PINCTRL_PIN(U26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) ASPEED_PINCTRL_PIN(V24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) ASPEED_PINCTRL_PIN(V25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) ASPEED_PINCTRL_PIN(V26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) ASPEED_PINCTRL_PIN(W23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) ASPEED_PINCTRL_PIN(W24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) ASPEED_PINCTRL_PIN(W26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) ASPEED_PINCTRL_PIN(Y1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) ASPEED_PINCTRL_PIN(Y2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) ASPEED_PINCTRL_PIN(Y23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) ASPEED_PINCTRL_PIN(Y24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) ASPEED_PINCTRL_PIN(Y25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ASPEED_PINCTRL_PIN(Y26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) ASPEED_PINCTRL_PIN(Y3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) ASPEED_PINCTRL_PIN(Y4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) ASPEED_PINCTRL_PIN(Y5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static const struct aspeed_pin_group aspeed_g6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) ASPEED_PINCTRL_GROUP(ADC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) ASPEED_PINCTRL_GROUP(ADC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) ASPEED_PINCTRL_GROUP(ADC10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) ASPEED_PINCTRL_GROUP(ADC11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ASPEED_PINCTRL_GROUP(ADC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) ASPEED_PINCTRL_GROUP(ADC13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) ASPEED_PINCTRL_GROUP(ADC14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) ASPEED_PINCTRL_GROUP(ADC15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ASPEED_PINCTRL_GROUP(ADC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ASPEED_PINCTRL_GROUP(ADC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) ASPEED_PINCTRL_GROUP(ADC4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) ASPEED_PINCTRL_GROUP(ADC5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) ASPEED_PINCTRL_GROUP(ADC6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) ASPEED_PINCTRL_GROUP(ADC7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) ASPEED_PINCTRL_GROUP(ADC8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) ASPEED_PINCTRL_GROUP(ADC9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) ASPEED_PINCTRL_GROUP(BMCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ASPEED_PINCTRL_GROUP(ESPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) ASPEED_PINCTRL_GROUP(ESPIALT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) ASPEED_PINCTRL_GROUP(FSI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) ASPEED_PINCTRL_GROUP(FSI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) ASPEED_PINCTRL_GROUP(FWSPIABR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) ASPEED_PINCTRL_GROUP(FWSPID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) ASPEED_PINCTRL_GROUP(FWQSPID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) ASPEED_PINCTRL_GROUP(FWSPIWP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) ASPEED_PINCTRL_GROUP(GPIT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) ASPEED_PINCTRL_GROUP(GPIT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ASPEED_PINCTRL_GROUP(GPIT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) ASPEED_PINCTRL_GROUP(GPIT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ASPEED_PINCTRL_GROUP(GPIT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) ASPEED_PINCTRL_GROUP(GPIT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) ASPEED_PINCTRL_GROUP(GPIT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) ASPEED_PINCTRL_GROUP(GPIT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) ASPEED_PINCTRL_GROUP(GPIU0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) ASPEED_PINCTRL_GROUP(GPIU1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ASPEED_PINCTRL_GROUP(GPIU2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) ASPEED_PINCTRL_GROUP(GPIU3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ASPEED_PINCTRL_GROUP(GPIU4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) ASPEED_PINCTRL_GROUP(GPIU5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) ASPEED_PINCTRL_GROUP(GPIU6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ASPEED_PINCTRL_GROUP(GPIU7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) ASPEED_PINCTRL_GROUP(HEARTBEAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) ASPEED_PINCTRL_GROUP(HVI3C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) ASPEED_PINCTRL_GROUP(HVI3C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) ASPEED_PINCTRL_GROUP(I2C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) ASPEED_PINCTRL_GROUP(I2C10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ASPEED_PINCTRL_GROUP(I2C11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) ASPEED_PINCTRL_GROUP(I2C12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) ASPEED_PINCTRL_GROUP(I2C13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) ASPEED_PINCTRL_GROUP(I2C14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) ASPEED_PINCTRL_GROUP(I2C15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) ASPEED_PINCTRL_GROUP(I2C16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) ASPEED_PINCTRL_GROUP(I2C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) ASPEED_PINCTRL_GROUP(I2C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) ASPEED_PINCTRL_GROUP(I2C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) ASPEED_PINCTRL_GROUP(I2C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) ASPEED_PINCTRL_GROUP(I2C6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ASPEED_PINCTRL_GROUP(I2C7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) ASPEED_PINCTRL_GROUP(I2C8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) ASPEED_PINCTRL_GROUP(I2C9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) ASPEED_PINCTRL_GROUP(I3C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) ASPEED_PINCTRL_GROUP(I3C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) ASPEED_PINCTRL_GROUP(I3C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) ASPEED_PINCTRL_GROUP(I3C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) ASPEED_PINCTRL_GROUP(I3C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) ASPEED_PINCTRL_GROUP(I3C6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) ASPEED_PINCTRL_GROUP(JTAGM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) ASPEED_PINCTRL_GROUP(LHPD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) ASPEED_PINCTRL_GROUP(LHSIRQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) ASPEED_PINCTRL_GROUP(LPC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) ASPEED_PINCTRL_GROUP(LPCHC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) ASPEED_PINCTRL_GROUP(LPCPD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) ASPEED_PINCTRL_GROUP(LPCPME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) ASPEED_PINCTRL_GROUP(LPCSMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) ASPEED_PINCTRL_GROUP(LSIRQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) ASPEED_PINCTRL_GROUP(MACLINK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ASPEED_PINCTRL_GROUP(MACLINK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) ASPEED_PINCTRL_GROUP(MACLINK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) ASPEED_PINCTRL_GROUP(MACLINK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) ASPEED_PINCTRL_GROUP(MDIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ASPEED_PINCTRL_GROUP(MDIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) ASPEED_PINCTRL_GROUP(MDIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) ASPEED_PINCTRL_GROUP(MDIO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) ASPEED_PINCTRL_GROUP(NCTS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ASPEED_PINCTRL_GROUP(NCTS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) ASPEED_PINCTRL_GROUP(NCTS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) ASPEED_PINCTRL_GROUP(NCTS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) ASPEED_PINCTRL_GROUP(NDCD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) ASPEED_PINCTRL_GROUP(NDCD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) ASPEED_PINCTRL_GROUP(NDCD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) ASPEED_PINCTRL_GROUP(NDCD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ASPEED_PINCTRL_GROUP(NDSR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) ASPEED_PINCTRL_GROUP(NDSR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) ASPEED_PINCTRL_GROUP(NDSR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) ASPEED_PINCTRL_GROUP(NDSR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ASPEED_PINCTRL_GROUP(NDTR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) ASPEED_PINCTRL_GROUP(NDTR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) ASPEED_PINCTRL_GROUP(NDTR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) ASPEED_PINCTRL_GROUP(NDTR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) ASPEED_PINCTRL_GROUP(NRI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) ASPEED_PINCTRL_GROUP(NRI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) ASPEED_PINCTRL_GROUP(NRI3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) ASPEED_PINCTRL_GROUP(NRI4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ASPEED_PINCTRL_GROUP(NRTS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) ASPEED_PINCTRL_GROUP(NRTS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) ASPEED_PINCTRL_GROUP(NRTS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) ASPEED_PINCTRL_GROUP(NRTS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) ASPEED_PINCTRL_GROUP(OSCCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) ASPEED_PINCTRL_GROUP(PEWAKE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ASPEED_PINCTRL_GROUP(PWM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) ASPEED_PINCTRL_GROUP(PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) ASPEED_PINCTRL_GROUP(PWM10G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) ASPEED_PINCTRL_GROUP(PWM10G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) ASPEED_PINCTRL_GROUP(PWM11G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) ASPEED_PINCTRL_GROUP(PWM11G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) ASPEED_PINCTRL_GROUP(PWM12G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) ASPEED_PINCTRL_GROUP(PWM12G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) ASPEED_PINCTRL_GROUP(PWM13G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) ASPEED_PINCTRL_GROUP(PWM13G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) ASPEED_PINCTRL_GROUP(PWM14G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) ASPEED_PINCTRL_GROUP(PWM14G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) ASPEED_PINCTRL_GROUP(PWM15G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) ASPEED_PINCTRL_GROUP(PWM15G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) ASPEED_PINCTRL_GROUP(PWM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) ASPEED_PINCTRL_GROUP(PWM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) ASPEED_PINCTRL_GROUP(PWM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) ASPEED_PINCTRL_GROUP(PWM5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) ASPEED_PINCTRL_GROUP(PWM6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) ASPEED_PINCTRL_GROUP(PWM7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) ASPEED_PINCTRL_GROUP(PWM8G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) ASPEED_PINCTRL_GROUP(PWM8G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) ASPEED_PINCTRL_GROUP(PWM9G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) ASPEED_PINCTRL_GROUP(PWM9G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) ASPEED_PINCTRL_GROUP(QSPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) ASPEED_PINCTRL_GROUP(QSPI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) ASPEED_PINCTRL_GROUP(RGMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) ASPEED_PINCTRL_GROUP(RGMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ASPEED_PINCTRL_GROUP(RGMII3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) ASPEED_PINCTRL_GROUP(RGMII4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) ASPEED_PINCTRL_GROUP(RMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ASPEED_PINCTRL_GROUP(RMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) ASPEED_PINCTRL_GROUP(RMII3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) ASPEED_PINCTRL_GROUP(RMII4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) ASPEED_PINCTRL_GROUP(RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) ASPEED_PINCTRL_GROUP(RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) ASPEED_PINCTRL_GROUP(RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) ASPEED_PINCTRL_GROUP(RXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) ASPEED_PINCTRL_GROUP(SALT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) ASPEED_PINCTRL_GROUP(SALT10G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) ASPEED_PINCTRL_GROUP(SALT10G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) ASPEED_PINCTRL_GROUP(SALT11G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) ASPEED_PINCTRL_GROUP(SALT11G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) ASPEED_PINCTRL_GROUP(SALT12G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) ASPEED_PINCTRL_GROUP(SALT12G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) ASPEED_PINCTRL_GROUP(SALT13G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) ASPEED_PINCTRL_GROUP(SALT13G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) ASPEED_PINCTRL_GROUP(SALT14G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) ASPEED_PINCTRL_GROUP(SALT14G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) ASPEED_PINCTRL_GROUP(SALT15G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) ASPEED_PINCTRL_GROUP(SALT15G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) ASPEED_PINCTRL_GROUP(SALT16G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) ASPEED_PINCTRL_GROUP(SALT16G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) ASPEED_PINCTRL_GROUP(SALT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) ASPEED_PINCTRL_GROUP(SALT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) ASPEED_PINCTRL_GROUP(SALT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) ASPEED_PINCTRL_GROUP(SALT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ASPEED_PINCTRL_GROUP(SALT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) ASPEED_PINCTRL_GROUP(SALT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) ASPEED_PINCTRL_GROUP(SALT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) ASPEED_PINCTRL_GROUP(SALT9G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) ASPEED_PINCTRL_GROUP(SALT9G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) ASPEED_PINCTRL_GROUP(SD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) ASPEED_PINCTRL_GROUP(SD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) ASPEED_PINCTRL_GROUP(EMMCG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) ASPEED_PINCTRL_GROUP(EMMCG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) ASPEED_PINCTRL_GROUP(EMMCG8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) ASPEED_PINCTRL_GROUP(SGPM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) ASPEED_PINCTRL_GROUP(SGPS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) ASPEED_PINCTRL_GROUP(SIOONCTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) ASPEED_PINCTRL_GROUP(SIOPBI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ASPEED_PINCTRL_GROUP(SIOPBO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) ASPEED_PINCTRL_GROUP(SIOPWREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) ASPEED_PINCTRL_GROUP(SIOPWRGD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) ASPEED_PINCTRL_GROUP(SIOS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) ASPEED_PINCTRL_GROUP(SIOS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) ASPEED_PINCTRL_GROUP(SIOSCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ASPEED_PINCTRL_GROUP(SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) ASPEED_PINCTRL_GROUP(SPI1ABR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) ASPEED_PINCTRL_GROUP(SPI1CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) ASPEED_PINCTRL_GROUP(SPI1WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) ASPEED_PINCTRL_GROUP(SPI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) ASPEED_PINCTRL_GROUP(SPI2CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) ASPEED_PINCTRL_GROUP(SPI2CS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) ASPEED_PINCTRL_GROUP(TACH0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) ASPEED_PINCTRL_GROUP(TACH1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) ASPEED_PINCTRL_GROUP(TACH10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) ASPEED_PINCTRL_GROUP(TACH11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) ASPEED_PINCTRL_GROUP(TACH12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) ASPEED_PINCTRL_GROUP(TACH13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) ASPEED_PINCTRL_GROUP(TACH14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) ASPEED_PINCTRL_GROUP(TACH15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) ASPEED_PINCTRL_GROUP(TACH2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) ASPEED_PINCTRL_GROUP(TACH3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) ASPEED_PINCTRL_GROUP(TACH4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) ASPEED_PINCTRL_GROUP(TACH5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) ASPEED_PINCTRL_GROUP(TACH6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) ASPEED_PINCTRL_GROUP(TACH7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) ASPEED_PINCTRL_GROUP(TACH8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ASPEED_PINCTRL_GROUP(TACH9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) ASPEED_PINCTRL_GROUP(THRU0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) ASPEED_PINCTRL_GROUP(THRU1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) ASPEED_PINCTRL_GROUP(THRU2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ASPEED_PINCTRL_GROUP(THRU3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) ASPEED_PINCTRL_GROUP(TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) ASPEED_PINCTRL_GROUP(TXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) ASPEED_PINCTRL_GROUP(TXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) ASPEED_PINCTRL_GROUP(TXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) ASPEED_PINCTRL_GROUP(UART10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ASPEED_PINCTRL_GROUP(UART11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) ASPEED_PINCTRL_GROUP(UART12G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) ASPEED_PINCTRL_GROUP(UART12G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) ASPEED_PINCTRL_GROUP(UART13G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) ASPEED_PINCTRL_GROUP(UART13G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) ASPEED_PINCTRL_GROUP(UART6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) ASPEED_PINCTRL_GROUP(UART7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) ASPEED_PINCTRL_GROUP(UART8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) ASPEED_PINCTRL_GROUP(UART9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) ASPEED_PINCTRL_GROUP(USBA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) ASPEED_PINCTRL_GROUP(USBB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) ASPEED_PINCTRL_GROUP(VB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) ASPEED_PINCTRL_GROUP(VGAHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) ASPEED_PINCTRL_GROUP(VGAVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) ASPEED_PINCTRL_GROUP(WDTRST1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) ASPEED_PINCTRL_GROUP(WDTRST2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) ASPEED_PINCTRL_GROUP(WDTRST3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) ASPEED_PINCTRL_GROUP(WDTRST4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static const struct aspeed_pin_function aspeed_g6_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) ASPEED_PINCTRL_FUNC(ADC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) ASPEED_PINCTRL_FUNC(ADC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) ASPEED_PINCTRL_FUNC(ADC10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) ASPEED_PINCTRL_FUNC(ADC11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) ASPEED_PINCTRL_FUNC(ADC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) ASPEED_PINCTRL_FUNC(ADC13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) ASPEED_PINCTRL_FUNC(ADC14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) ASPEED_PINCTRL_FUNC(ADC15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) ASPEED_PINCTRL_FUNC(ADC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) ASPEED_PINCTRL_FUNC(ADC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) ASPEED_PINCTRL_FUNC(ADC4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) ASPEED_PINCTRL_FUNC(ADC5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) ASPEED_PINCTRL_FUNC(ADC6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) ASPEED_PINCTRL_FUNC(ADC7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) ASPEED_PINCTRL_FUNC(ADC8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) ASPEED_PINCTRL_FUNC(ADC9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) ASPEED_PINCTRL_FUNC(BMCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) ASPEED_PINCTRL_FUNC(EMMC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) ASPEED_PINCTRL_FUNC(ESPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) ASPEED_PINCTRL_FUNC(ESPIALT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) ASPEED_PINCTRL_FUNC(FSI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) ASPEED_PINCTRL_FUNC(FSI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) ASPEED_PINCTRL_FUNC(FWSPIABR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) ASPEED_PINCTRL_FUNC(FWSPID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) ASPEED_PINCTRL_FUNC(FWSPIWP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) ASPEED_PINCTRL_FUNC(GPIT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) ASPEED_PINCTRL_FUNC(GPIT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) ASPEED_PINCTRL_FUNC(GPIT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) ASPEED_PINCTRL_FUNC(GPIT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) ASPEED_PINCTRL_FUNC(GPIT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) ASPEED_PINCTRL_FUNC(GPIT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) ASPEED_PINCTRL_FUNC(GPIT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) ASPEED_PINCTRL_FUNC(GPIT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) ASPEED_PINCTRL_FUNC(GPIU0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) ASPEED_PINCTRL_FUNC(GPIU1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) ASPEED_PINCTRL_FUNC(GPIU2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) ASPEED_PINCTRL_FUNC(GPIU3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) ASPEED_PINCTRL_FUNC(GPIU4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) ASPEED_PINCTRL_FUNC(GPIU5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) ASPEED_PINCTRL_FUNC(GPIU6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) ASPEED_PINCTRL_FUNC(GPIU7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) ASPEED_PINCTRL_FUNC(HEARTBEAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) ASPEED_PINCTRL_FUNC(I2C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) ASPEED_PINCTRL_FUNC(I2C10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) ASPEED_PINCTRL_FUNC(I2C11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) ASPEED_PINCTRL_FUNC(I2C12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) ASPEED_PINCTRL_FUNC(I2C13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) ASPEED_PINCTRL_FUNC(I2C14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) ASPEED_PINCTRL_FUNC(I2C15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) ASPEED_PINCTRL_FUNC(I2C16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) ASPEED_PINCTRL_FUNC(I2C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) ASPEED_PINCTRL_FUNC(I2C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) ASPEED_PINCTRL_FUNC(I2C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) ASPEED_PINCTRL_FUNC(I2C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) ASPEED_PINCTRL_FUNC(I2C6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ASPEED_PINCTRL_FUNC(I2C7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) ASPEED_PINCTRL_FUNC(I2C8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) ASPEED_PINCTRL_FUNC(I2C9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) ASPEED_PINCTRL_FUNC(I3C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) ASPEED_PINCTRL_FUNC(I3C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) ASPEED_PINCTRL_FUNC(I3C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) ASPEED_PINCTRL_FUNC(I3C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) ASPEED_PINCTRL_FUNC(I3C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) ASPEED_PINCTRL_FUNC(I3C6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) ASPEED_PINCTRL_FUNC(JTAGM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) ASPEED_PINCTRL_FUNC(LHPD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) ASPEED_PINCTRL_FUNC(LHSIRQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) ASPEED_PINCTRL_FUNC(LPC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) ASPEED_PINCTRL_FUNC(LPCHC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) ASPEED_PINCTRL_FUNC(LPCPD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) ASPEED_PINCTRL_FUNC(LPCPME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) ASPEED_PINCTRL_FUNC(LPCSMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) ASPEED_PINCTRL_FUNC(LSIRQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) ASPEED_PINCTRL_FUNC(MACLINK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) ASPEED_PINCTRL_FUNC(MACLINK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) ASPEED_PINCTRL_FUNC(MACLINK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) ASPEED_PINCTRL_FUNC(MACLINK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) ASPEED_PINCTRL_FUNC(MDIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) ASPEED_PINCTRL_FUNC(MDIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) ASPEED_PINCTRL_FUNC(MDIO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) ASPEED_PINCTRL_FUNC(MDIO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) ASPEED_PINCTRL_FUNC(NCTS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) ASPEED_PINCTRL_FUNC(NCTS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) ASPEED_PINCTRL_FUNC(NCTS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) ASPEED_PINCTRL_FUNC(NCTS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) ASPEED_PINCTRL_FUNC(NDCD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) ASPEED_PINCTRL_FUNC(NDCD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) ASPEED_PINCTRL_FUNC(NDCD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) ASPEED_PINCTRL_FUNC(NDCD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) ASPEED_PINCTRL_FUNC(NDSR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) ASPEED_PINCTRL_FUNC(NDSR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) ASPEED_PINCTRL_FUNC(NDSR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) ASPEED_PINCTRL_FUNC(NDSR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) ASPEED_PINCTRL_FUNC(NDTR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) ASPEED_PINCTRL_FUNC(NDTR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) ASPEED_PINCTRL_FUNC(NDTR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) ASPEED_PINCTRL_FUNC(NDTR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) ASPEED_PINCTRL_FUNC(NRI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) ASPEED_PINCTRL_FUNC(NRI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) ASPEED_PINCTRL_FUNC(NRI3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) ASPEED_PINCTRL_FUNC(NRI4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) ASPEED_PINCTRL_FUNC(NRTS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) ASPEED_PINCTRL_FUNC(NRTS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) ASPEED_PINCTRL_FUNC(NRTS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) ASPEED_PINCTRL_FUNC(NRTS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) ASPEED_PINCTRL_FUNC(OSCCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) ASPEED_PINCTRL_FUNC(PEWAKE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) ASPEED_PINCTRL_FUNC(PWM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) ASPEED_PINCTRL_FUNC(PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) ASPEED_PINCTRL_FUNC(PWM10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) ASPEED_PINCTRL_FUNC(PWM11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) ASPEED_PINCTRL_FUNC(PWM12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) ASPEED_PINCTRL_FUNC(PWM13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) ASPEED_PINCTRL_FUNC(PWM14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) ASPEED_PINCTRL_FUNC(PWM15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) ASPEED_PINCTRL_FUNC(PWM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) ASPEED_PINCTRL_FUNC(PWM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) ASPEED_PINCTRL_FUNC(PWM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) ASPEED_PINCTRL_FUNC(PWM5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) ASPEED_PINCTRL_FUNC(PWM6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) ASPEED_PINCTRL_FUNC(PWM7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) ASPEED_PINCTRL_FUNC(PWM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) ASPEED_PINCTRL_FUNC(PWM9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) ASPEED_PINCTRL_FUNC(RGMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) ASPEED_PINCTRL_FUNC(RGMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) ASPEED_PINCTRL_FUNC(RGMII3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) ASPEED_PINCTRL_FUNC(RGMII4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) ASPEED_PINCTRL_FUNC(RMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) ASPEED_PINCTRL_FUNC(RMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) ASPEED_PINCTRL_FUNC(RMII3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) ASPEED_PINCTRL_FUNC(RMII4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) ASPEED_PINCTRL_FUNC(RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) ASPEED_PINCTRL_FUNC(RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) ASPEED_PINCTRL_FUNC(RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) ASPEED_PINCTRL_FUNC(RXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) ASPEED_PINCTRL_FUNC(SALT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) ASPEED_PINCTRL_FUNC(SALT10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) ASPEED_PINCTRL_FUNC(SALT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) ASPEED_PINCTRL_FUNC(SALT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) ASPEED_PINCTRL_FUNC(SALT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) ASPEED_PINCTRL_FUNC(SALT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) ASPEED_PINCTRL_FUNC(SALT15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) ASPEED_PINCTRL_FUNC(SALT16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) ASPEED_PINCTRL_FUNC(SALT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) ASPEED_PINCTRL_FUNC(SALT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) ASPEED_PINCTRL_FUNC(SALT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) ASPEED_PINCTRL_FUNC(SALT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) ASPEED_PINCTRL_FUNC(SALT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) ASPEED_PINCTRL_FUNC(SALT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) ASPEED_PINCTRL_FUNC(SALT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) ASPEED_PINCTRL_FUNC(SALT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) ASPEED_PINCTRL_FUNC(SD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) ASPEED_PINCTRL_FUNC(SD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) ASPEED_PINCTRL_FUNC(SGPM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) ASPEED_PINCTRL_FUNC(SGPS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) ASPEED_PINCTRL_FUNC(SIOONCTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) ASPEED_PINCTRL_FUNC(SIOPBI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) ASPEED_PINCTRL_FUNC(SIOPBO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) ASPEED_PINCTRL_FUNC(SIOPWREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) ASPEED_PINCTRL_FUNC(SIOPWRGD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) ASPEED_PINCTRL_FUNC(SIOS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) ASPEED_PINCTRL_FUNC(SIOS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) ASPEED_PINCTRL_FUNC(SIOSCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) ASPEED_PINCTRL_FUNC(SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) ASPEED_PINCTRL_FUNC(SPI1ABR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) ASPEED_PINCTRL_FUNC(SPI1CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) ASPEED_PINCTRL_FUNC(SPI1WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) ASPEED_PINCTRL_FUNC(SPI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) ASPEED_PINCTRL_FUNC(SPI2CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) ASPEED_PINCTRL_FUNC(SPI2CS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) ASPEED_PINCTRL_FUNC(TACH0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) ASPEED_PINCTRL_FUNC(TACH1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) ASPEED_PINCTRL_FUNC(TACH10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) ASPEED_PINCTRL_FUNC(TACH11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) ASPEED_PINCTRL_FUNC(TACH12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) ASPEED_PINCTRL_FUNC(TACH13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) ASPEED_PINCTRL_FUNC(TACH14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) ASPEED_PINCTRL_FUNC(TACH15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) ASPEED_PINCTRL_FUNC(TACH2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) ASPEED_PINCTRL_FUNC(TACH3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) ASPEED_PINCTRL_FUNC(TACH4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) ASPEED_PINCTRL_FUNC(TACH5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) ASPEED_PINCTRL_FUNC(TACH6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) ASPEED_PINCTRL_FUNC(TACH7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) ASPEED_PINCTRL_FUNC(TACH8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) ASPEED_PINCTRL_FUNC(TACH9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) ASPEED_PINCTRL_FUNC(THRU0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) ASPEED_PINCTRL_FUNC(THRU1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) ASPEED_PINCTRL_FUNC(THRU2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) ASPEED_PINCTRL_FUNC(THRU3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) ASPEED_PINCTRL_FUNC(TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) ASPEED_PINCTRL_FUNC(TXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) ASPEED_PINCTRL_FUNC(TXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) ASPEED_PINCTRL_FUNC(TXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) ASPEED_PINCTRL_FUNC(UART10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) ASPEED_PINCTRL_FUNC(UART11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) ASPEED_PINCTRL_FUNC(UART12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) ASPEED_PINCTRL_FUNC(UART13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) ASPEED_PINCTRL_FUNC(UART6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) ASPEED_PINCTRL_FUNC(UART7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) ASPEED_PINCTRL_FUNC(UART8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) ASPEED_PINCTRL_FUNC(UART9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) ASPEED_PINCTRL_FUNC(USB11BHID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) ASPEED_PINCTRL_FUNC(USB2AD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) ASPEED_PINCTRL_FUNC(USB2ADP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) ASPEED_PINCTRL_FUNC(USB2AH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) ASPEED_PINCTRL_FUNC(USB2AHP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) ASPEED_PINCTRL_FUNC(USB2BD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) ASPEED_PINCTRL_FUNC(USB2BH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) ASPEED_PINCTRL_FUNC(VB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) ASPEED_PINCTRL_FUNC(VGAHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) ASPEED_PINCTRL_FUNC(VGAVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) ASPEED_PINCTRL_FUNC(WDTRST1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) ASPEED_PINCTRL_FUNC(WDTRST2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) ASPEED_PINCTRL_FUNC(WDTRST3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) ASPEED_PINCTRL_FUNC(WDTRST4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) static struct aspeed_pin_config aspeed_g6_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) /* GPIOB7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) ASPEED_PULL_DOWN_PINCONF(J24, SCU610, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) /* GPIOB6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) ASPEED_PULL_DOWN_PINCONF(H25, SCU610, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) /* GPIOB5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) ASPEED_PULL_DOWN_PINCONF(G26, SCU610, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) /* GPIOB4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) ASPEED_PULL_DOWN_PINCONF(J23, SCU610, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) /* GPIOB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) ASPEED_PULL_DOWN_PINCONF(J25, SCU610, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) /* GPIOB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) ASPEED_PULL_DOWN_PINCONF(H26, SCU610, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) /* GPIOB1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) ASPEED_PULL_DOWN_PINCONF(K23, SCU610, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) /* GPIOB0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) ASPEED_PULL_DOWN_PINCONF(J26, SCU610, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) /* GPIOH3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) ASPEED_PULL_DOWN_PINCONF(A17, SCU614, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) /* GPIOH2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) ASPEED_PULL_DOWN_PINCONF(C18, SCU614, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) /* GPIOH1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) ASPEED_PULL_DOWN_PINCONF(B18, SCU614, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) /* GPIOH0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) ASPEED_PULL_DOWN_PINCONF(A18, SCU614, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) /* GPIOL7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) ASPEED_PULL_DOWN_PINCONF(C14, SCU618, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /* GPIOL6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) ASPEED_PULL_DOWN_PINCONF(B14, SCU618, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) /* GPIOL5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) ASPEED_PULL_DOWN_PINCONF(F15, SCU618, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) /* GPIOL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) ASPEED_PULL_DOWN_PINCONF(C15, SCU618, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) /* GPIOJ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) ASPEED_PULL_UP_PINCONF(D19, SCU618, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) /* GPIOJ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) ASPEED_PULL_UP_PINCONF(C20, SCU618, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) /* GPIOJ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) ASPEED_PULL_UP_PINCONF(A19, SCU618, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) /* GPIOJ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) ASPEED_PULL_UP_PINCONF(C19, SCU618, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) /* GPIOJ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) ASPEED_PULL_UP_PINCONF(D20, SCU618, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) /* GPIOJ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) ASPEED_PULL_UP_PINCONF(E19, SCU618, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) /* GPIOJ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) ASPEED_PULL_UP_PINCONF(A20, SCU618, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) /* GPIOJ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) ASPEED_PULL_UP_PINCONF(B20, SCU618, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) /* GPIOI7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) /* GPIOI6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) ASPEED_PULL_DOWN_PINCONF(B16, SCU618, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) /* GPIOI5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) ASPEED_PULL_DOWN_PINCONF(E16, SCU618, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) /* GPIOI4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) ASPEED_PULL_DOWN_PINCONF(C16, SCU618, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) /* GPIOI3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) ASPEED_PULL_DOWN_PINCONF(D16, SCU618, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) /* GPIOI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) ASPEED_PULL_DOWN_PINCONF(E17, SCU618, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) /* GPIOI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) ASPEED_PULL_DOWN_PINCONF(A16, SCU618, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) /* GPIOI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) ASPEED_PULL_DOWN_PINCONF(D17, SCU618, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) /* GPIOP7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) ASPEED_PULL_DOWN_PINCONF(Y23, SCU61C, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) /* GPIOP6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) ASPEED_PULL_DOWN_PINCONF(AB24, SCU61C, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) /* GPIOP5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) ASPEED_PULL_DOWN_PINCONF(AB23, SCU61C, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) /* GPIOP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) ASPEED_PULL_DOWN_PINCONF(W23, SCU61C, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) /* GPIOP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) ASPEED_PULL_DOWN_PINCONF(AA24, SCU61C, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) /* GPIOP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) ASPEED_PULL_DOWN_PINCONF(AA23, SCU61C, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) /* GPIOP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) ASPEED_PULL_DOWN_PINCONF(W24, SCU61C, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) /* GPIOP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) ASPEED_PULL_DOWN_PINCONF(AB22, SCU61C, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) /* GPIOO7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) ASPEED_PULL_DOWN_PINCONF(AC23, SCU61C, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) /* GPIOO6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) ASPEED_PULL_DOWN_PINCONF(AC24, SCU61C, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) /* GPIOO5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) ASPEED_PULL_DOWN_PINCONF(AC22, SCU61C, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) /* GPIOO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) ASPEED_PULL_DOWN_PINCONF(AD25, SCU61C, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) /* GPIOO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) ASPEED_PULL_DOWN_PINCONF(AD24, SCU61C, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) /* GPIOO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) ASPEED_PULL_DOWN_PINCONF(AD23, SCU61C, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) /* GPIOO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) ASPEED_PULL_DOWN_PINCONF(AD22, SCU61C, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) /* GPIOO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) ASPEED_PULL_DOWN_PINCONF(AD26, SCU61C, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) /* GPION7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) ASPEED_PULL_DOWN_PINCONF(M26, SCU61C, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) /* GPION6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) ASPEED_PULL_DOWN_PINCONF(N26, SCU61C, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) /* GPION5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) ASPEED_PULL_DOWN_PINCONF(M23, SCU61C, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) /* GPION4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) ASPEED_PULL_DOWN_PINCONF(P26, SCU61C, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) /* GPION3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) ASPEED_PULL_DOWN_PINCONF(N24, SCU61C, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) /* GPION2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) ASPEED_PULL_DOWN_PINCONF(N25, SCU61C, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) /* GPION1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) ASPEED_PULL_DOWN_PINCONF(N23, SCU61C, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) /* GPION0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) ASPEED_PULL_DOWN_PINCONF(P25, SCU61C, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) /* GPIOM7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) ASPEED_PULL_DOWN_PINCONF(D13, SCU61C, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) /* GPIOM6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) ASPEED_PULL_DOWN_PINCONF(C13, SCU61C, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) /* GPIOM5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) ASPEED_PULL_DOWN_PINCONF(C12, SCU61C, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) /* GPIOM4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) ASPEED_PULL_DOWN_PINCONF(B12, SCU61C, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) /* GPIOM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) ASPEED_PULL_DOWN_PINCONF(E14, SCU61C, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) /* GPIOM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) ASPEED_PULL_DOWN_PINCONF(A12, SCU61C, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) /* GPIOM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) ASPEED_PULL_DOWN_PINCONF(B13, SCU61C, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) /* GPIOM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) /* GPIOS7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) ASPEED_PULL_DOWN_PINCONF(T24, SCU620, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) /* GPIOS6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) ASPEED_PULL_DOWN_PINCONF(P23, SCU620, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) /* GPIOS5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) ASPEED_PULL_DOWN_PINCONF(P24, SCU620, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) /* GPIOS4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) ASPEED_PULL_DOWN_PINCONF(R26, SCU620, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) /* GPIOS3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) ASPEED_PULL_DOWN_PINCONF(R24, SCU620, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) /* GPIOS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) ASPEED_PULL_DOWN_PINCONF(T26, SCU620, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) /* GPIOS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) ASPEED_PULL_DOWN_PINCONF(T25, SCU620, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) /* GPIOS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) ASPEED_PULL_DOWN_PINCONF(R23, SCU620, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) /* GPIOR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) ASPEED_PULL_DOWN_PINCONF(U26, SCU620, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) /* GPIOR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) ASPEED_PULL_DOWN_PINCONF(W26, SCU620, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) /* GPIOR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) ASPEED_PULL_DOWN_PINCONF(T23, SCU620, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) /* GPIOR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) ASPEED_PULL_DOWN_PINCONF(U25, SCU620, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) /* GPIOR3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) ASPEED_PULL_DOWN_PINCONF(V26, SCU620, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) /* GPIOR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) ASPEED_PULL_DOWN_PINCONF(V24, SCU620, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) /* GPIOR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) ASPEED_PULL_DOWN_PINCONF(U24, SCU620, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) /* GPIOR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) ASPEED_PULL_DOWN_PINCONF(V25, SCU620, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) /* GPIOX7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) /* GPIOX6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) ASPEED_PULL_DOWN_PINCONF(AF9, SCU634, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) /* GPIOX5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) ASPEED_PULL_DOWN_PINCONF(AD9, SCU634, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) /* GPIOX4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) ASPEED_PULL_DOWN_PINCONF(AB9, SCU634, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) /* GPIOX3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) ASPEED_PULL_DOWN_PINCONF(AF8, SCU634, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) /* GPIOX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) ASPEED_PULL_DOWN_PINCONF(AC9, SCU634, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) /* GPIOX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) ASPEED_PULL_DOWN_PINCONF(AA9, SCU634, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) /* GPIOX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) ASPEED_PULL_DOWN_PINCONF(AE8, SCU634, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) /* GPIOV7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) ASPEED_PULL_DOWN_PINCONF(AF15, SCU634, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) /* GPIOV6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) ASPEED_PULL_DOWN_PINCONF(AD15, SCU634, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /* GPIOV5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) ASPEED_PULL_DOWN_PINCONF(AE14, SCU634, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) /* GPIOV4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) ASPEED_PULL_DOWN_PINCONF(AE15, SCU634, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) /* GPIOV3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) ASPEED_PULL_DOWN_PINCONF(AC15, SCU634, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) /* GPIOV2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) ASPEED_PULL_DOWN_PINCONF(AD14, SCU634, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* GPIOV1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) ASPEED_PULL_DOWN_PINCONF(AF14, SCU634, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) /* GPIOV0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) ASPEED_PULL_DOWN_PINCONF(AB15, SCU634, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) /* GPIOZ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) ASPEED_PULL_DOWN_PINCONF(AF10, SCU638, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) /* GPIOZ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) ASPEED_PULL_DOWN_PINCONF(AD11, SCU638, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) /* GPIOZ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) ASPEED_PULL_DOWN_PINCONF(AA11, SCU638, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) /* GPIOZ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) ASPEED_PULL_DOWN_PINCONF(AC11, SCU638, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) /* GPIOZ3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) ASPEED_PULL_DOWN_PINCONF(AB11, SCU638, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) /* GPIOZ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) ASPEED_PULL_DOWN_PINCONF(AD10, SCU638, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) /* GPIOZ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) ASPEED_PULL_DOWN_PINCONF(AC10, SCU638, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) /* GPIOY6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) ASPEED_PULL_DOWN_PINCONF(AC12, SCU638, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) /* GPIOY5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) ASPEED_PULL_DOWN_PINCONF(AF12, SCU638, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) /* GPIOY4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) ASPEED_PULL_DOWN_PINCONF(AE12, SCU638, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) /* GPIOY3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) ASPEED_PULL_DOWN_PINCONF(AA12, SCU638, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) /* GPIOY2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) ASPEED_PULL_DOWN_PINCONF(AE11, SCU638, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) /* GPIOY1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) ASPEED_PULL_DOWN_PINCONF(AD12, SCU638, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) /* GPIOY0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) ASPEED_PULL_DOWN_PINCONF(AF11, SCU638, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) /* LAD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) { PIN_CONFIG_DRIVE_STRENGTH, { AC7, AC7 }, SCU454, GENMASK(31, 30)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) /* LAD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) { PIN_CONFIG_DRIVE_STRENGTH, { AC8, AC8 }, SCU454, GENMASK(29, 28)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) /* LAD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) { PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) /* LAD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) { PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) /* MAC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) { PIN_CONFIG_POWER_SOURCE, { H24, E26 }, SCU458, BIT_MASK(4)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) { PIN_CONFIG_DRIVE_STRENGTH, { H24, E26 }, SCU458, GENMASK(1, 0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) /* MAC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) { PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) { PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) /* GPIO18E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, Y4, SCU40C, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, Y4, SCU40C, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) /* GPIO18D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AB4, AC5, SCU40C, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AB4, AC5, SCU40C, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) /* GPIO18C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E4, E1, SCU40C, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E4, E1, SCU40C, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) /* GPIO18B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D3, SCU40C, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D3, SCU40C, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) /* GPIO18A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C6, A2, SCU40C, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C6, A2, SCU40C, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) * Configure a pin's signal by applying an expression's descriptor state for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) * all descriptors in the expression.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) * @ctx: The pinmux context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) * @expr: The expression associated with the function whose signal is to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) * configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) * @enable: true to enable an function's signal through a pin's signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) * expression, false to disable the function's signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) * Return: 0 if the expression is configured as requested and a negative error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) * code otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) static int aspeed_g6_sig_expr_set(struct aspeed_pinmux_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) const struct aspeed_sig_expr *expr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) for (i = 0; i < expr->ndescs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) const struct aspeed_sig_desc *desc = &expr->descs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) u32 pattern = enable ? desc->enable : desc->disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) u32 val = (pattern << __ffs(desc->mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) bool is_strap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) if (!ctx->maps[desc->ip])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) WARN_ON(desc->ip != ASPEED_IP_SCU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) is_strap = desc->reg == SCU500 || desc->reg == SCU510;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) if (is_strap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) * The AST2600 has write protection mask registers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) * the hardware strapping in SCU508 and SCU518. Assume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) * that if the platform doesn't want the strapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) * values changed that it has set the write mask.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) * The strapping registers implement write-1-clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) * behaviour. SCU500 is paired with clear writes on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) * SCU504, likewise SCU510 is paired with SCU514.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) u32 clear = ~val & desc->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) u32 w1c = desc->reg + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) if (clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) ret = regmap_update_bits(ctx->maps[desc->ip],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) w1c, desc->mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) desc->mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) ret = aspeed_sig_expr_eval(ctx, expr, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static const struct aspeed_pin_config_map aspeed_g6_pin_config_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) { PIN_CONFIG_BIAS_PULL_UP, 0, 1, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) { PIN_CONFIG_BIAS_PULL_UP, -1, 0, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) { PIN_CONFIG_DRIVE_STRENGTH, 4, 0, GENMASK(1, 0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) { PIN_CONFIG_DRIVE_STRENGTH, 8, 1, GENMASK(1, 0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) { PIN_CONFIG_DRIVE_STRENGTH, 12, 2, GENMASK(1, 0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) { PIN_CONFIG_DRIVE_STRENGTH, 16, 3, GENMASK(1, 0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) { PIN_CONFIG_POWER_SOURCE, 3300, 0, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) { PIN_CONFIG_POWER_SOURCE, 1800, 1, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) static const struct aspeed_pinmux_ops aspeed_g5_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) .set = aspeed_g6_sig_expr_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) static struct aspeed_pinctrl_data aspeed_g6_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .pins = aspeed_g6_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .npins = ARRAY_SIZE(aspeed_g6_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .pinmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) .ops = &aspeed_g5_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .groups = aspeed_g6_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .ngroups = ARRAY_SIZE(aspeed_g6_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) .functions = aspeed_g6_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) .nfunctions = ARRAY_SIZE(aspeed_g6_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) .configs = aspeed_g6_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .nconfigs = ARRAY_SIZE(aspeed_g6_configs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .confmaps = aspeed_g6_pin_config_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .nconfmaps = ARRAY_SIZE(aspeed_g6_pin_config_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) static const struct pinmux_ops aspeed_g6_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .get_functions_count = aspeed_pinmux_get_fn_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .get_function_name = aspeed_pinmux_get_fn_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) .get_function_groups = aspeed_pinmux_get_fn_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .set_mux = aspeed_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .gpio_request_enable = aspeed_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .strict = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) static const struct pinctrl_ops aspeed_g6_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .get_groups_count = aspeed_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) .get_group_name = aspeed_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .get_group_pins = aspeed_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) .pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) static const struct pinconf_ops aspeed_g6_conf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) .pin_config_get = aspeed_pin_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) .pin_config_set = aspeed_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .pin_config_group_get = aspeed_pin_config_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .pin_config_group_set = aspeed_pin_config_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) static struct pinctrl_desc aspeed_g6_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) .name = "aspeed-g6-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) .pins = aspeed_g6_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .npins = ARRAY_SIZE(aspeed_g6_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .pctlops = &aspeed_g6_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .pmxops = &aspeed_g6_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) .confops = &aspeed_g6_conf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) static int aspeed_g6_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) for (i = 0; i < ARRAY_SIZE(aspeed_g6_pins); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) aspeed_g6_pins[i].number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) return aspeed_pinctrl_probe(pdev, &aspeed_g6_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) &aspeed_g6_pinctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) static const struct of_device_id aspeed_g6_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) { .compatible = "aspeed,ast2600-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) static struct platform_driver aspeed_g6_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .probe = aspeed_g6_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .name = "aspeed-g6-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .of_match_table = aspeed_g6_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) static int aspeed_g6_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) return platform_driver_register(&aspeed_g6_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) arch_initcall(aspeed_g6_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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