^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pinctrl-aspeed.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Wrap some of the common macros for clarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SIG_EXPR_DECL_SINGLE(sig, func, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SIG_EXPR_DECL(sig, func, func, __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * references registers by the device/offset mnemonic. The register macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * below are named the same way to ease transcription and verification (as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * reference registers beyond those dedicated to pinmux, such as the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * reset control and MAC clock configuration registers. The AST2500 goes a step
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * further and references registers in the graphics IP block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCU2C 0x2C /* Misc. Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCU3C 0x3C /* System Reset Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCU48 0x48 /* MAC Interface Clock Delay Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HW_REVISION_ID 0x7C /* Silicon revision ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCU80 0x80 /* Multi-function Pin Control #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCU84 0x84 /* Multi-function Pin Control #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCU88 0x88 /* Multi-function Pin Control #3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCU8C 0x8C /* Multi-function Pin Control #4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SCU90 0x90 /* Multi-function Pin Control #5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SCU94 0x94 /* Multi-function Pin Control #6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SCUA0 0xA0 /* Multi-function Pin Control #7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SCUA4 0xA4 /* Multi-function Pin Control #8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SCUA8 0xA8 /* Multi-function Pin Control #9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SCUAC 0xAC /* Multi-function Pin Control #10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HW_STRAP2 0xD0 /* Strapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ASPEED_G5_NR_PINS 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* LHCR0 is offset from the end of the H8S/2168-compatible registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LHCR0 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GFX064 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define B14 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define D14 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define D13 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SIG_EXPR_LIST_DECL_SINGLE(D13, SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SIG_EXPR_LIST_DECL_SINGLE(D13, TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PIN_DECL_2(D13, GPIOA2, SPI1CS1, TIMER3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FUNC_GROUP_DECL(SPI1CS1, D13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FUNC_GROUP_DECL(TIMER3, D13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define E13 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define I2C9_DESC SIG_DESC_SET(SCU90, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define C14 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SIG_EXPR_LIST_DECL_SINGLE(C14, SCL9, I2C9, I2C9_DESC, COND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SIG_EXPR_LIST_DECL_SINGLE(C14, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PIN_DECL_2(C14, GPIOA4, SCL9, TIMER5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FUNC_GROUP_DECL(TIMER5, C14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define A13 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) SIG_EXPR_LIST_DECL_SINGLE(A13, SDA9, I2C9, I2C9_DESC, COND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SIG_EXPR_LIST_DECL_SINGLE(A13, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PIN_DECL_2(A13, GPIOA5, SDA9, TIMER6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FUNC_GROUP_DECL(TIMER6, A13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FUNC_GROUP_DECL(I2C9, C14, A13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MDIO2_DESC SIG_DESC_SET(SCU90, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define C13 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) SIG_EXPR_LIST_DECL_SINGLE(C13, MDC2, MDIO2, MDIO2_DESC, COND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) SIG_EXPR_LIST_DECL_SINGLE(C13, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PIN_DECL_2(C13, GPIOA6, MDC2, TIMER7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FUNC_GROUP_DECL(TIMER7, C13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define B13 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SIG_EXPR_LIST_DECL_SINGLE(B13, MDIO2, MDIO2, MDIO2_DESC, COND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SIG_EXPR_LIST_DECL_SINGLE(B13, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PIN_DECL_2(B13, GPIOA7, MDIO2, TIMER8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FUNC_GROUP_DECL(TIMER8, B13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) FUNC_GROUP_DECL(MDIO2, C13, B13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define K19 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) GPIO_PIN_DECL(K19, GPIOB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define L19 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) GPIO_PIN_DECL(L19, GPIOB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define L18 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) GPIO_PIN_DECL(L18, GPIOB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define K18 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) GPIO_PIN_DECL(K18, GPIOB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define J20 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define H21 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define H21_DESC SIG_DESC_SET(SCU80, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SIG_EXPR_LIST_DECL_SINGLE(H21, LPCPD, LPCPD, H21_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SIG_EXPR_LIST_DECL_SINGLE(H21, LPCSMI, LPCSMI, H21_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PIN_DECL_2(H21, GPIOB5, LPCPD, LPCSMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) FUNC_GROUP_DECL(LPCPD, H21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FUNC_GROUP_DECL(LPCSMI, H21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define H22 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define H20 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) GPIO_PIN_DECL(H20, GPIOB7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SD1_DESC SIG_DESC_SET(SCU90, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define C12 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define I2C10_DESC SIG_DESC_SET(SCU90, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) SIG_EXPR_LIST_DECL_SINGLE(C12, SD1CLK, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SIG_EXPR_LIST_DECL_SINGLE(C12, SCL10, I2C10, I2C10_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PIN_DECL_2(C12, GPIOC0, SD1CLK, SCL10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define A12 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SIG_EXPR_LIST_DECL_SINGLE(A12, SD1CMD, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) SIG_EXPR_LIST_DECL_SINGLE(A12, SDA10, I2C10, I2C10_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PIN_DECL_2(A12, GPIOC1, SD1CMD, SDA10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FUNC_GROUP_DECL(I2C10, C12, A12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define B12 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define I2C11_DESC SIG_DESC_SET(SCU90, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SIG_EXPR_LIST_DECL_SINGLE(B12, SD1DAT0, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SIG_EXPR_LIST_DECL_SINGLE(B12, SCL11, I2C11, I2C11_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PIN_DECL_2(B12, GPIOC2, SD1DAT0, SCL11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define D9 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SIG_EXPR_LIST_DECL_SINGLE(D9, SD1DAT1, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SIG_EXPR_LIST_DECL_SINGLE(D9, SDA11, I2C11, I2C11_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PIN_DECL_2(D9, GPIOC3, SD1DAT1, SDA11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) FUNC_GROUP_DECL(I2C11, B12, D9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define D10 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define I2C12_DESC SIG_DESC_SET(SCU90, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SIG_EXPR_LIST_DECL_SINGLE(D10, SD1DAT2, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) SIG_EXPR_LIST_DECL_SINGLE(D10, SCL12, I2C12, I2C12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PIN_DECL_2(D10, GPIOC4, SD1DAT2, SCL12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define E12 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) SIG_EXPR_LIST_DECL_SINGLE(E12, SD1DAT3, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SIG_EXPR_LIST_DECL_SINGLE(E12, SDA12, I2C12, I2C12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PIN_DECL_2(E12, GPIOC5, SD1DAT3, SDA12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) FUNC_GROUP_DECL(I2C12, D10, E12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define C11 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define I2C13_DESC SIG_DESC_SET(SCU90, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SIG_EXPR_LIST_DECL_SINGLE(C11, SD1CD, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SIG_EXPR_LIST_DECL_SINGLE(C11, SCL13, I2C13, I2C13_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PIN_DECL_2(C11, GPIOC6, SD1CD, SCL13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define B11 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SIG_EXPR_LIST_DECL_SINGLE(B11, SD1WP, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SIG_EXPR_LIST_DECL_SINGLE(B11, SDA13, I2C13, I2C13_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PIN_DECL_2(B11, GPIOC7, SD1WP, SDA13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) FUNC_GROUP_DECL(I2C13, C11, B11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SD2_DESC SIG_DESC_SET(SCU90, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GPID0_DESC SIG_DESC_SET(SCU8C, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define F19 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SIG_EXPR_LIST_DECL_SINGLE(F19, SD2CLK, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) SIG_EXPR_LIST_DECL_DUAL(F19, GPID0IN, GPID0, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PIN_DECL_2(F19, GPIOD0, SD2CLK, GPID0IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define E21 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) SIG_EXPR_LIST_DECL_SINGLE(E21, SD2CMD, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SIG_EXPR_LIST_DECL_DUAL(E21, GPID0OUT, GPID0, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PIN_DECL_2(E21, GPIOD1, SD2CMD, GPID0OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) FUNC_GROUP_DECL(GPID0, F19, E21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define F20 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SIG_EXPR_LIST_DECL_SINGLE(F20, SD2DAT0, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SIG_EXPR_LIST_DECL_DUAL(F20, GPID2IN, GPID2, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PIN_DECL_2(F20, GPIOD2, SD2DAT0, GPID2IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define D20 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SIG_EXPR_LIST_DECL_SINGLE(D20, SD2DAT1, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) SIG_EXPR_LIST_DECL_DUAL(D20, GPID2OUT, GPID2, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PIN_DECL_2(D20, GPIOD3, SD2DAT1, GPID2OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) FUNC_GROUP_DECL(GPID2, F20, D20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define D21 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) SIG_EXPR_LIST_DECL_SINGLE(D21, SD2DAT2, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SIG_EXPR_LIST_DECL_DUAL(D21, GPID4IN, GPID4, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PIN_DECL_2(D21, GPIOD4, SD2DAT2, GPID4IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define E20 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SIG_EXPR_LIST_DECL_SINGLE(E20, SD2DAT3, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) SIG_EXPR_LIST_DECL_DUAL(E20, GPID4OUT, GPID4, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PIN_DECL_2(E20, GPIOD5, SD2DAT3, GPID4OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) FUNC_GROUP_DECL(GPID4, D21, E20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define G18 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) SIG_EXPR_LIST_DECL_SINGLE(G18, SD2CD, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) SIG_EXPR_LIST_DECL_DUAL(G18, GPID6IN, GPID6, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PIN_DECL_2(G18, GPIOD6, SD2CD, GPID6IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define C21 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) SIG_EXPR_LIST_DECL_SINGLE(C21, SD2WP, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) SIG_EXPR_LIST_DECL_DUAL(C21, GPID6OUT, GPID6, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PIN_DECL_2(C21, GPIOD7, SD2WP, GPID6OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FUNC_GROUP_DECL(GPID6, G18, C21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define B20 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) SIG_EXPR_LIST_DECL_SINGLE(B20, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SIG_EXPR_LIST_DECL_DUAL(B20, GPIE0IN, GPIE0, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PIN_DECL_2(B20, GPIOE0, NCTS3, GPIE0IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) FUNC_GROUP_DECL(NCTS3, B20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define C20 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SIG_EXPR_LIST_DECL_SINGLE(C20, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) SIG_EXPR_LIST_DECL_DUAL(C20, GPIE0OUT, GPIE0, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PIN_DECL_2(C20, GPIOE1, NDCD3, GPIE0OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) FUNC_GROUP_DECL(NDCD3, C20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) FUNC_GROUP_DECL(GPIE0, B20, C20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define F18 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) SIG_EXPR_LIST_DECL_SINGLE(F18, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) SIG_EXPR_LIST_DECL_DUAL(F18, GPIE2IN, GPIE2, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PIN_DECL_2(F18, GPIOE2, NDSR3, GPIE2IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) FUNC_GROUP_DECL(NDSR3, F18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define F17 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SIG_EXPR_LIST_DECL_SINGLE(F17, NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SIG_EXPR_LIST_DECL_DUAL(F17, GPIE2OUT, GPIE2, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PIN_DECL_2(F17, GPIOE3, NRI3, GPIE2OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) FUNC_GROUP_DECL(NRI3, F17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) FUNC_GROUP_DECL(GPIE2, F18, F17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define GPIE4_DESC SIG_DESC_SET(SCU8C, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define E18 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SIG_EXPR_LIST_DECL_SINGLE(E18, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) SIG_EXPR_LIST_DECL_DUAL(E18, GPIE4IN, GPIE4, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PIN_DECL_2(E18, GPIOE4, NDTR3, GPIE4IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) FUNC_GROUP_DECL(NDTR3, E18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define D19 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SIG_EXPR_LIST_DECL_SINGLE(D19, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SIG_EXPR_LIST_DECL_DUAL(D19, GPIE4OUT, GPIE4, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PIN_DECL_2(D19, GPIOE5, NRTS3, GPIE4OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) FUNC_GROUP_DECL(NRTS3, D19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) FUNC_GROUP_DECL(GPIE4, E18, D19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define A20 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) SIG_EXPR_LIST_DECL_SINGLE(A20, TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) SIG_EXPR_LIST_DECL_DUAL(A20, GPIE6IN, GPIE6, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PIN_DECL_2(A20, GPIOE6, TXD3, GPIE6IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) FUNC_GROUP_DECL(TXD3, A20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define B19 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) SIG_EXPR_LIST_DECL_SINGLE(B19, RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SIG_EXPR_LIST_DECL_DUAL(B19, GPIE6OUT, GPIE6, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PIN_DECL_2(B19, GPIOE7, RXD3, GPIE6OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) FUNC_GROUP_DECL(RXD3, B19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) FUNC_GROUP_DECL(GPIE6, A20, B19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define LPCHC_DESC SIG_DESC_IP_SET(ASPEED_IP_LPC, LHCR0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define J19 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) SIG_EXPR_DECL_SINGLE(LHAD0, LPCHC, LPCHC_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) SIG_EXPR_DECL_SINGLE(LHAD0, LPCPLUS, LPCPLUS_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) SIG_EXPR_LIST_DECL_DUAL(J19, LHAD0, LPCHC, LPCPLUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) SIG_EXPR_LIST_DECL_SINGLE(J19, NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PIN_DECL_2(J19, GPIOF0, LHAD0, NCTS4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) FUNC_GROUP_DECL(NCTS4, J19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define J18 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) SIG_EXPR_DECL_SINGLE(LHAD1, LPCHC, LPCHC_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) SIG_EXPR_DECL_SINGLE(LHAD1, LPCPLUS, LPCPLUS_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) SIG_EXPR_LIST_DECL_DUAL(J18, LHAD1, LPCHC, LPCPLUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) SIG_EXPR_LIST_DECL_SINGLE(J18, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PIN_DECL_2(J18, GPIOF1, LHAD1, NDCD4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) FUNC_GROUP_DECL(NDCD4, J18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define B22 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) SIG_EXPR_DECL_SINGLE(LHAD2, LPCHC, LPCHC_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) SIG_EXPR_DECL_SINGLE(LHAD2, LPCPLUS, LPCPLUS_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) SIG_EXPR_LIST_DECL_DUAL(B22, LHAD2, LPCHC, LPCPLUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) SIG_EXPR_LIST_DECL_SINGLE(B22, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PIN_DECL_2(B22, GPIOF2, LHAD2, NDSR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) FUNC_GROUP_DECL(NDSR4, B22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define B21 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) SIG_EXPR_DECL_SINGLE(LHAD3, LPCHC, LPCHC_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) SIG_EXPR_DECL_SINGLE(LHAD3, LPCPLUS, LPCPLUS_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) SIG_EXPR_LIST_DECL_DUAL(B21, LHAD3, LPCHC, LPCPLUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) SIG_EXPR_LIST_DECL_SINGLE(B21, NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PIN_DECL_2(B21, GPIOF3, LHAD3, NRI4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) FUNC_GROUP_DECL(NRI4, B21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define A21 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) SIG_EXPR_DECL_SINGLE(LHCLK, LPCHC, LPCHC_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) SIG_EXPR_DECL_SINGLE(LHCLK, LPCPLUS, LPCPLUS_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) SIG_EXPR_LIST_DECL_DUAL(A21, LHCLK, LPCHC, LPCPLUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) SIG_EXPR_LIST_DECL_SINGLE(A21, NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PIN_DECL_2(A21, GPIOF4, LHCLK, NDTR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) FUNC_GROUP_DECL(NDTR4, A21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define H19 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) SIG_EXPR_DECL_SINGLE(LHFRAME, LPCHC, LPCHC_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) SIG_EXPR_DECL_SINGLE(LHFRAME, LPCPLUS, LPCPLUS_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) SIG_EXPR_LIST_DECL_DUAL(H19, LHFRAME, LPCHC, LPCPLUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) SIG_EXPR_LIST_DECL_SINGLE(H19, NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PIN_DECL_2(H19, GPIOF5, LHFRAME, NRTS4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) FUNC_GROUP_DECL(NRTS4, H19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define G17 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SIG_EXPR_LIST_DECL_SINGLE(G17, LHSIRQ, LPCHC, LPCHC_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SIG_EXPR_LIST_DECL_SINGLE(G17, TXD4, TXD4, SIG_DESC_SET(SCU80, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PIN_DECL_2(G17, GPIOF6, LHSIRQ, TXD4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) FUNC_GROUP_DECL(TXD4, G17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define H18 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) SIG_EXPR_DECL_SINGLE(LHRST, LPCHC, LPCHC_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) SIG_EXPR_DECL_SINGLE(LHRST, LPCPLUS, LPCPLUS_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) SIG_EXPR_LIST_DECL_DUAL(H18, LHRST, LPCHC, LPCPLUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) SIG_EXPR_LIST_DECL_SINGLE(H18, RXD4, RXD4, SIG_DESC_SET(SCU80, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PIN_DECL_2(H18, GPIOF7, LHRST, RXD4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) FUNC_GROUP_DECL(RXD4, H18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define A19 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) SIG_EXPR_LIST_DECL_SINGLE(A19, SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PIN_DECL_1(A19, GPIOG0, SGPS1CK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define E19 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) SIG_EXPR_LIST_DECL_SINGLE(E19, SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PIN_DECL_1(E19, GPIOG1, SGPS1LD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define C19 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) SIG_EXPR_LIST_DECL_SINGLE(C19, SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PIN_DECL_1(C19, GPIOG2, SGPS1I0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define E16 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) SIG_EXPR_LIST_DECL_SINGLE(E16, SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PIN_DECL_1(E16, GPIOG3, SGPS1I1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SGPS2_DESC SIG_DESC_SET(SCU94, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define E17 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) SIG_EXPR_LIST_DECL_SINGLE(E17, SGPS2CK, SGPS2, COND1, SGPS2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) SIG_EXPR_LIST_DECL_SINGLE(E17, SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PIN_DECL_2(E17, GPIOG4, SGPS2CK, SALT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) FUNC_GROUP_DECL(SALT1, E17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define D16 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) SIG_EXPR_LIST_DECL_SINGLE(D16, SGPS2LD, SGPS2, COND1, SGPS2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) SIG_EXPR_LIST_DECL_SINGLE(D16, SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PIN_DECL_2(D16, GPIOG5, SGPS2LD, SALT2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) FUNC_GROUP_DECL(SALT2, D16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define D15 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) SIG_EXPR_LIST_DECL_SINGLE(D15, SGPS2I0, SGPS2, COND1, SGPS2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SIG_EXPR_LIST_DECL_SINGLE(D15, SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PIN_DECL_2(D15, GPIOG6, SGPS2I0, SALT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) FUNC_GROUP_DECL(SALT3, D15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define E14 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) SIG_EXPR_LIST_DECL_SINGLE(E14, SGPS2I1, SGPS2, COND1, SGPS2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SIG_EXPR_LIST_DECL_SINGLE(E14, SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PIN_DECL_2(E14, GPIOG7, SGPS2I1, SALT4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) FUNC_GROUP_DECL(SALT4, E14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define UART6_DESC SIG_DESC_SET(SCU90, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define A18 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) SIG_EXPR_LIST_DECL_SINGLE(A18, DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, UART6, COND1, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PIN_DECL_2(A18, GPIOH0, DASHA18, NCTS6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define B18 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) SIG_EXPR_LIST_DECL_SINGLE(B18, DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) SIG_EXPR_LIST_DECL_SINGLE(B18, NDCD6, UART6, COND1, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PIN_DECL_2(B18, GPIOH1, DASHB18, NDCD6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define D17 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SIG_EXPR_LIST_DECL_SINGLE(D17, DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) SIG_EXPR_LIST_DECL_SINGLE(D17, NDSR6, UART6, COND1, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PIN_DECL_2(D17, GPIOH2, DASHD17, NDSR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define C17 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) SIG_EXPR_LIST_DECL_SINGLE(C17, DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) SIG_EXPR_LIST_DECL_SINGLE(C17, NRI6, UART6, COND1, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PIN_DECL_2(C17, GPIOH3, DASHC17, NRI6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define A17 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) SIG_EXPR_LIST_DECL_SINGLE(A17, DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) SIG_EXPR_LIST_DECL_SINGLE(A17, NDTR6, UART6, COND1, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PIN_DECL_2(A17, GPIOH4, DASHA17, NDTR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define B17 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SIG_EXPR_LIST_DECL_SINGLE(B17, DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) SIG_EXPR_LIST_DECL_SINGLE(B17, NRTS6, UART6, COND1, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PIN_DECL_2(B17, GPIOH5, DASHB17, NRTS6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define A16 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) SIG_EXPR_LIST_DECL_SINGLE(A16, TXD6, UART6, COND1, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PIN_DECL_1(A16, GPIOH6, TXD6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define D18 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SIG_EXPR_LIST_DECL_SINGLE(D18, RXD6, UART6, COND1, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PIN_DECL_1(D18, GPIOH7, RXD6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define SPI1_DESC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SPI1DEBUG_DESC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SPI1PASSTHRU_DESC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define C18 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) SIG_EXPR_LIST_DECL_DUAL(C18, SYSCS, SPI1DEBUG, SPI1PASSTHRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PIN_DECL_1(C18, GPIOI0, SYSCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define E15 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) SIG_EXPR_LIST_DECL_DUAL(E15, SYSCK, SPI1DEBUG, SPI1PASSTHRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PIN_DECL_1(E15, GPIOI1, SYSCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define B16 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) SIG_EXPR_LIST_DECL_DUAL(B16, SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PIN_DECL_1(B16, GPIOI2, SYSMOSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define C16 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) SIG_EXPR_LIST_DECL_DUAL(C16, SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PIN_DECL_1(C16, GPIOI3, SYSMISO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define B15 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, COND1, SPI1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SIG_EXPR_LIST_DECL(SPI1CS0, SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) SIG_EXPR_PTR(SPI1CS0, SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) SIG_EXPR_LIST_ALIAS(B15, SPI1CS0, SPI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) SIG_EXPR_LIST_DECL_SINGLE(B15, VBCS, VGABIOSROM, COND1, VB_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PIN_DECL_2(B15, GPIOI4, SPI1CS0, VBCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define C15 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, COND1, SPI1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) SIG_EXPR_LIST_DECL(SPI1CK, SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) SIG_EXPR_PTR(SPI1CK, SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) SIG_EXPR_LIST_ALIAS(C15, SPI1CK, SPI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) SIG_EXPR_LIST_DECL_SINGLE(C15, VBCK, VGABIOSROM, COND1, VB_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PIN_DECL_2(C15, GPIOI5, SPI1CK, VBCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define A14 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1, COND1, SPI1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) SIG_EXPR_LIST_DECL(SPI1MOSI, SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) SIG_EXPR_PTR(SPI1MOSI, SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) SIG_EXPR_LIST_ALIAS(A14, SPI1MOSI, SPI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) SIG_EXPR_LIST_DECL_SINGLE(A14, VBMOSI, VGABIOSROM, COND1, VB_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PIN_DECL_2(A14, GPIOI6, SPI1MOSI, VBMOSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define A15 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1, COND1, SPI1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) SIG_EXPR_LIST_DECL(SPI1MISO, SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) SIG_EXPR_PTR(SPI1MISO, SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) SIG_EXPR_LIST_ALIAS(A15, SPI1MISO, SPI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) SIG_EXPR_LIST_DECL_SINGLE(A15, VBMISO, VGABIOSROM, COND1, VB_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PIN_DECL_2(A15, GPIOI7, SPI1MISO, VBMISO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define R2 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) SIG_EXPR_LIST_DECL_SINGLE(R2, SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PIN_DECL_1(R2, GPIOJ0, SGPMCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define L2 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) SIG_EXPR_LIST_DECL_SINGLE(L2, SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PIN_DECL_1(L2, GPIOJ1, SGPMLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define N3 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) SIG_EXPR_LIST_DECL_SINGLE(N3, SGPMO, SGPM, SIG_DESC_SET(SCU84, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PIN_DECL_1(N3, GPIOJ2, SGPMO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define N4 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) SIG_EXPR_LIST_DECL_SINGLE(N4, SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PIN_DECL_1(N4, GPIOJ3, SGPMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define N5 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) SIG_EXPR_LIST_DECL_SINGLE(N5, VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) SIG_EXPR_LIST_DECL_SINGLE(N5, DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PIN_DECL_2(N5, GPIOJ4, VGAHS, DASHN5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) FUNC_GROUP_DECL(VGAHS, N5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define R4 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) SIG_EXPR_LIST_DECL_SINGLE(R4, VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) SIG_EXPR_LIST_DECL_SINGLE(R4, DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PIN_DECL_2(R4, GPIOJ5, VGAVS, DASHR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) FUNC_GROUP_DECL(VGAVS, R4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define R3 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) SIG_EXPR_LIST_DECL_SINGLE(R3, DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) SIG_EXPR_LIST_DECL_SINGLE(R3, DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PIN_DECL_2(R3, GPIOJ6, DDCCLK, DASHR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) FUNC_GROUP_DECL(DDCCLK, R3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define T3 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) SIG_EXPR_LIST_DECL_SINGLE(T3, DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) SIG_EXPR_LIST_DECL_SINGLE(T3, DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PIN_DECL_2(T3, GPIOJ7, DDCDAT, DASHT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) FUNC_GROUP_DECL(DDCDAT, T3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define I2C5_DESC SIG_DESC_SET(SCU90, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define L3 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) SIG_EXPR_LIST_DECL_SINGLE(L3, SCL5, I2C5, I2C5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PIN_DECL_1(L3, GPIOK0, SCL5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define L4 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) SIG_EXPR_LIST_DECL_SINGLE(L4, SDA5, I2C5, I2C5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PIN_DECL_1(L4, GPIOK1, SDA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) FUNC_GROUP_DECL(I2C5, L3, L4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define I2C6_DESC SIG_DESC_SET(SCU90, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define L1 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SIG_EXPR_LIST_DECL_SINGLE(L1, SCL6, I2C6, I2C6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PIN_DECL_1(L1, GPIOK2, SCL6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define N2 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) SIG_EXPR_LIST_DECL_SINGLE(N2, SDA6, I2C6, I2C6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PIN_DECL_1(N2, GPIOK3, SDA6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) FUNC_GROUP_DECL(I2C6, L1, N2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define I2C7_DESC SIG_DESC_SET(SCU90, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define N1 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) SIG_EXPR_LIST_DECL_SINGLE(N1, SCL7, I2C7, I2C7_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PIN_DECL_1(N1, GPIOK4, SCL7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define P1 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) SIG_EXPR_LIST_DECL_SINGLE(P1, SDA7, I2C7, I2C7_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PIN_DECL_1(P1, GPIOK5, SDA7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) FUNC_GROUP_DECL(I2C7, N1, P1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define I2C8_DESC SIG_DESC_SET(SCU90, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define P2 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) SIG_EXPR_LIST_DECL_SINGLE(P2, SCL8, I2C8, I2C8_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PIN_DECL_1(P2, GPIOK6, SCL8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define R1 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) SIG_EXPR_LIST_DECL_SINGLE(R1, SDA8, I2C8, I2C8_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PIN_DECL_1(R1, GPIOK7, SDA8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) FUNC_GROUP_DECL(I2C8, P2, R1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define T2 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define VPI_24_RSVD_DESC SIG_DESC_SET(SCU90, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define T1 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define T1_DESC SIG_DESC_SET(SCU84, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) SIG_EXPR_LIST_DECL_SINGLE(T1, VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) SIG_EXPR_LIST_DECL_SINGLE(T1, NDCD1, NDCD1, T1_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PIN_DECL_2(T1, GPIOL1, VPIDE, NDCD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) FUNC_GROUP_DECL(NDCD1, T1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define U1 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define U1_DESC SIG_DESC_SET(SCU84, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) SIG_EXPR_LIST_DECL_SINGLE(U1, DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) SIG_EXPR_LIST_DECL_SINGLE(U1, NDSR1, NDSR1, U1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PIN_DECL_2(U1, GPIOL2, DASHU1, NDSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) FUNC_GROUP_DECL(NDSR1, U1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define U2 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define U2_DESC SIG_DESC_SET(SCU84, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) SIG_EXPR_LIST_DECL_SINGLE(U2, VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) SIG_EXPR_LIST_DECL_SINGLE(U2, NRI1, NRI1, U2_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PIN_DECL_2(U2, GPIOL3, VPIHS, NRI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) FUNC_GROUP_DECL(NRI1, U2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define P4 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define P4_DESC SIG_DESC_SET(SCU84, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) SIG_EXPR_LIST_DECL_SINGLE(P4, VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) SIG_EXPR_LIST_DECL_SINGLE(P4, NDTR1, NDTR1, P4_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PIN_DECL_2(P4, GPIOL4, VPIVS, NDTR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) FUNC_GROUP_DECL(NDTR1, P4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define P3 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define P3_DESC SIG_DESC_SET(SCU84, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) SIG_EXPR_LIST_DECL_SINGLE(P3, VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) SIG_EXPR_LIST_DECL_SINGLE(P3, NRTS1, NRTS1, P3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PIN_DECL_2(P3, GPIOL5, VPICLK, NRTS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) FUNC_GROUP_DECL(NRTS1, P3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define V1 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define V1_DESC SIG_DESC_SET(SCU84, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) SIG_EXPR_LIST_DECL_SINGLE(V1, DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) SIG_EXPR_LIST_DECL_SINGLE(V1, TXD1, TXD1, V1_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PIN_DECL_2(V1, GPIOL6, DASHV1, TXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) FUNC_GROUP_DECL(TXD1, V1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define W1 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define W1_DESC SIG_DESC_SET(SCU84, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) SIG_EXPR_LIST_DECL_SINGLE(W1, DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) SIG_EXPR_LIST_DECL_SINGLE(W1, RXD1, RXD1, W1_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PIN_DECL_2(W1, GPIOL7, DASHW1, RXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) FUNC_GROUP_DECL(RXD1, W1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define Y1 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define Y1_DESC SIG_DESC_SET(SCU84, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) SIG_EXPR_LIST_DECL_SINGLE(Y1, VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) SIG_EXPR_LIST_DECL_SINGLE(Y1, NCTS2, NCTS2, Y1_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PIN_DECL_2(Y1, GPIOM0, VPIB2, NCTS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) FUNC_GROUP_DECL(NCTS2, Y1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define AB2 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #define AB2_DESC SIG_DESC_SET(SCU84, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) SIG_EXPR_LIST_DECL_SINGLE(AB2, NDCD2, NDCD2, AB2_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PIN_DECL_2(AB2, GPIOM1, VPIB3, NDCD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) FUNC_GROUP_DECL(NDCD2, AB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define AA1 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define AA1_DESC SIG_DESC_SET(SCU84, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) SIG_EXPR_LIST_DECL_SINGLE(AA1, VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) SIG_EXPR_LIST_DECL_SINGLE(AA1, NDSR2, NDSR2, AA1_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PIN_DECL_2(AA1, GPIOM2, VPIB4, NDSR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) FUNC_GROUP_DECL(NDSR2, AA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define Y2 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define Y2_DESC SIG_DESC_SET(SCU84, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) SIG_EXPR_LIST_DECL_SINGLE(Y2, VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) SIG_EXPR_LIST_DECL_SINGLE(Y2, NRI2, NRI2, Y2_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PIN_DECL_2(Y2, GPIOM3, VPIB5, NRI2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) FUNC_GROUP_DECL(NRI2, Y2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define AA2 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define AA2_DESC SIG_DESC_SET(SCU84, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) SIG_EXPR_LIST_DECL_SINGLE(AA2, VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) SIG_EXPR_LIST_DECL_SINGLE(AA2, NDTR2, NDTR2, AA2_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) PIN_DECL_2(AA2, GPIOM4, VPIB6, NDTR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) FUNC_GROUP_DECL(NDTR2, AA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define P5 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define P5_DESC SIG_DESC_SET(SCU84, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) SIG_EXPR_LIST_DECL_SINGLE(P5, VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) SIG_EXPR_LIST_DECL_SINGLE(P5, NRTS2, NRTS2, P5_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) PIN_DECL_2(P5, GPIOM5, VPIB7, NRTS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) FUNC_GROUP_DECL(NRTS2, P5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define R5 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define R5_DESC SIG_DESC_SET(SCU84, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) SIG_EXPR_LIST_DECL_SINGLE(R5, VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) SIG_EXPR_LIST_DECL_SINGLE(R5, TXD2, TXD2, R5_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) PIN_DECL_2(R5, GPIOM6, VPIB8, TXD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) FUNC_GROUP_DECL(TXD2, R5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define T5 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define T5_DESC SIG_DESC_SET(SCU84, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) SIG_EXPR_LIST_DECL_SINGLE(T5, VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) SIG_EXPR_LIST_DECL_SINGLE(T5, RXD2, RXD2, T5_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) PIN_DECL_2(T5, GPIOM7, VPIB9, RXD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) FUNC_GROUP_DECL(RXD2, T5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define V2 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define V2_DESC SIG_DESC_SET(SCU88, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) SIG_EXPR_LIST_DECL_SINGLE(V2, DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) SIG_EXPR_LIST_DECL_SINGLE(V2, PWM0, PWM0, V2_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PIN_DECL_2(V2, GPION0, DASHN0, PWM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) FUNC_GROUP_DECL(PWM0, V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define W2 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define W2_DESC SIG_DESC_SET(SCU88, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) SIG_EXPR_LIST_DECL_SINGLE(W2, DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) SIG_EXPR_LIST_DECL_SINGLE(W2, PWM1, PWM1, W2_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PIN_DECL_2(W2, GPION1, DASHN1, PWM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) FUNC_GROUP_DECL(PWM1, W2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define V3 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define V3_DESC SIG_DESC_SET(SCU88, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) SIG_EXPR_DECL_SINGLE(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) SIG_EXPR_LIST_DECL_DUAL(V3, VPIG2, VPI24, VPIRSVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) SIG_EXPR_LIST_DECL_SINGLE(V3, PWM2, PWM2, V3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PIN_DECL_2(V3, GPION2, VPIG2, PWM2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) FUNC_GROUP_DECL(PWM2, V3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define U3 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define U3_DESC SIG_DESC_SET(SCU88, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) SIG_EXPR_DECL_SINGLE(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) SIG_EXPR_LIST_DECL_DUAL(U3, VPIG3, VPI24, VPIRSVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) SIG_EXPR_LIST_DECL_SINGLE(U3, PWM3, PWM3, U3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) PIN_DECL_2(U3, GPION3, VPIG3, PWM3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) FUNC_GROUP_DECL(PWM3, U3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define W3 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define W3_DESC SIG_DESC_SET(SCU88, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) SIG_EXPR_DECL_SINGLE(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) SIG_EXPR_LIST_DECL_DUAL(W3, VPIG4, VPI24, VPIRSVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) SIG_EXPR_LIST_DECL_SINGLE(W3, PWM4, PWM4, W3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) PIN_DECL_2(W3, GPION4, VPIG4, PWM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) FUNC_GROUP_DECL(PWM4, W3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define AA3 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define AA3_DESC SIG_DESC_SET(SCU88, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) SIG_EXPR_DECL_SINGLE(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) SIG_EXPR_LIST_DECL_DUAL(AA3, VPIG5, VPI24, VPIRSVD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM5, PWM5, AA3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PIN_DECL_2(AA3, GPION5, VPIG5, PWM5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) FUNC_GROUP_DECL(PWM5, AA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define Y3 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define Y3_DESC SIG_DESC_SET(SCU88, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG6, VPI24, VPI24_DESC, Y3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM6, PWM6, Y3_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) PIN_DECL_2(Y3, GPION6, VPIG6, PWM6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) FUNC_GROUP_DECL(PWM6, Y3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define T4 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define T4_DESC SIG_DESC_SET(SCU88, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) SIG_EXPR_LIST_DECL_SINGLE(T4, VPIG7, VPI24, VPI24_DESC, T4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) SIG_EXPR_LIST_DECL_SINGLE(T4, PWM7, PWM7, T4_DESC, COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) PIN_DECL_2(T4, GPION7, VPIG7, PWM7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) FUNC_GROUP_DECL(PWM7, T4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define U5 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) SIG_EXPR_LIST_DECL_SINGLE(U5, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PIN_DECL_1(U5, GPIOO0, VPIG8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define U4 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) SIG_EXPR_LIST_DECL_SINGLE(U4, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) PIN_DECL_1(U4, GPIOO1, VPIG9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define V5 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) SIG_EXPR_LIST_DECL_SINGLE(V5, DASHV5, DASHV5, VPI_24_RSVD_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) SIG_DESC_SET(SCU88, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) PIN_DECL_1(V5, GPIOO2, DASHV5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define AB4 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) SIG_EXPR_LIST_DECL_SINGLE(AB4, DASHAB4, DASHAB4, VPI_24_RSVD_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) SIG_DESC_SET(SCU88, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PIN_DECL_1(AB4, GPIOO3, DASHAB4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define AB3 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR2, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) SIG_DESC_SET(SCU88, 12), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PIN_DECL_1(AB3, GPIOO4, VPIR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define Y4 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) SIG_EXPR_LIST_DECL_SINGLE(Y4, VPIR3, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) SIG_DESC_SET(SCU88, 13), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) PIN_DECL_1(Y4, GPIOO5, VPIR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define AA4 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR4, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) SIG_DESC_SET(SCU88, 14), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PIN_DECL_1(AA4, GPIOO6, VPIR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define W4 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) SIG_EXPR_LIST_DECL_SINGLE(W4, VPIR5, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) SIG_DESC_SET(SCU88, 15), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PIN_DECL_1(W4, GPIOO7, VPIR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define V4 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) SIG_EXPR_LIST_DECL_SINGLE(V4, VPIR6, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) SIG_DESC_SET(SCU88, 16), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PIN_DECL_1(V4, GPIOP0, VPIR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define W5 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) SIG_EXPR_LIST_DECL_SINGLE(W5, VPIR7, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) SIG_DESC_SET(SCU88, 17), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PIN_DECL_1(W5, GPIOP1, VPIR7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define AA5 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR8, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) SIG_DESC_SET(SCU88, 18), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PIN_DECL_1(AA5, GPIOP2, VPIR8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define AB5 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR9, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) SIG_DESC_SET(SCU88, 19), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PIN_DECL_1(AB5, GPIOP3, VPIR9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) AB5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define Y6 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) SIG_EXPR_LIST_DECL_SINGLE(Y6, DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) SIG_DESC_SET(SCU88, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PIN_DECL_1(Y6, GPIOP4, DASHY6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define Y5 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) SIG_EXPR_LIST_DECL_SINGLE(Y5, DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) SIG_DESC_SET(SCU88, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PIN_DECL_1(Y5, GPIOP5, DASHY5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define W6 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) SIG_EXPR_LIST_DECL_SINGLE(W6, DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) SIG_DESC_SET(SCU88, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) PIN_DECL_1(W6, GPIOP6, DASHW6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define V6 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) SIG_EXPR_LIST_DECL_SINGLE(V6, DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) SIG_DESC_SET(SCU88, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PIN_DECL_1(V6, GPIOP7, DASHV6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define I2C3_DESC SIG_DESC_SET(SCU90, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define A11 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) SIG_EXPR_LIST_DECL_SINGLE(A11, SCL3, I2C3, I2C3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PIN_DECL_1(A11, GPIOQ0, SCL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define A10 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) SIG_EXPR_LIST_DECL_SINGLE(A10, SDA3, I2C3, I2C3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PIN_DECL_1(A10, GPIOQ1, SDA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) FUNC_GROUP_DECL(I2C3, A11, A10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define I2C4_DESC SIG_DESC_SET(SCU90, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define A9 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) SIG_EXPR_LIST_DECL_SINGLE(A9, SCL4, I2C4, I2C4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PIN_DECL_1(A9, GPIOQ2, SCL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define B9 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) SIG_EXPR_LIST_DECL_SINGLE(B9, SDA4, I2C4, I2C4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) PIN_DECL_1(B9, GPIOQ3, SDA4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) FUNC_GROUP_DECL(I2C4, A9, B9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #define I2C14_DESC SIG_DESC_SET(SCU90, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define N21 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) SIG_EXPR_LIST_DECL_SINGLE(N21, SCL14, I2C14, I2C14_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PIN_DECL_1(N21, GPIOQ4, SCL14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define N22 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) SIG_EXPR_LIST_DECL_SINGLE(N22, SDA14, I2C14, I2C14_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PIN_DECL_1(N22, GPIOQ5, SDA14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) FUNC_GROUP_DECL(I2C14, N21, N22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define B10 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define N20 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define AA19 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define T19 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define T17 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define Y19 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define W19 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define V19 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define D8 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) SIG_EXPR_LIST_DECL_SINGLE(D8, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PIN_DECL_1(D8, GPIOR6, MDC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define E10 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) SIG_EXPR_LIST_DECL_SINGLE(E10, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PIN_DECL_1(E10, GPIOR7, MDIO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) FUNC_GROUP_DECL(MDIO1, D8, E10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define CRT_DVO_EN_DESC SIG_DESC_IP_SET(ASPEED_IP_GFX, GFX064, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define V20 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define V20_DESC SIG_DESC_SET(SCU8C, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) SIG_EXPR_DECL_SINGLE(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) SIG_EXPR_LIST_DECL(VPOB2, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) SIG_EXPR_PTR(VPOB2, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) SIG_EXPR_PTR(VPOB2, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) SIG_EXPR_PTR(VPOB2, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) SIG_EXPR_LIST_ALIAS(V20, VPOB2, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) SIG_EXPR_LIST_DECL_SINGLE(V20, SPI2CS1, SPI2CS1, V20_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PIN_DECL_2(V20, GPIOS0, VPOB2, SPI2CS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) FUNC_GROUP_DECL(SPI2CS1, V20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define U19 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define U19_DESC SIG_DESC_SET(SCU8C, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) SIG_EXPR_DECL_SINGLE(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) SIG_EXPR_LIST_DECL(VPOB3, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) SIG_EXPR_PTR(VPOB3, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) SIG_EXPR_PTR(VPOB3, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) SIG_EXPR_PTR(VPOB3, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) SIG_EXPR_LIST_ALIAS(U19, VPOB3, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) SIG_EXPR_LIST_DECL_SINGLE(U19, BMCINT, BMCINT, U19_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PIN_DECL_2(U19, GPIOS1, VPOB3, BMCINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) FUNC_GROUP_DECL(BMCINT, U19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define R18 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define R18_DESC SIG_DESC_SET(SCU8C, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) SIG_EXPR_DECL_SINGLE(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) SIG_EXPR_LIST_DECL(VPOB4, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) SIG_EXPR_PTR(VPOB4, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) SIG_EXPR_PTR(VPOB4, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) SIG_EXPR_PTR(VPOB4, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) SIG_EXPR_LIST_ALIAS(R18, VPOB4, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) SIG_EXPR_LIST_DECL_SINGLE(R18, SALT5, SALT5, R18_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PIN_DECL_2(R18, GPIOS2, VPOB4, SALT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) FUNC_GROUP_DECL(SALT5, R18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define P18 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define P18_DESC SIG_DESC_SET(SCU8C, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) SIG_EXPR_DECL_SINGLE(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) SIG_EXPR_LIST_DECL(VPOB5, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) SIG_EXPR_PTR(VPOB5, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) SIG_EXPR_PTR(VPOB5, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) SIG_EXPR_PTR(VPOB5, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) SIG_EXPR_LIST_ALIAS(P18, VPOB5, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) SIG_EXPR_LIST_DECL_SINGLE(P18, SALT6, SALT6, P18_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PIN_DECL_2(P18, GPIOS3, VPOB5, SALT6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) FUNC_GROUP_DECL(SALT6, P18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define R19 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define R19_DESC SIG_DESC_SET(SCU8C, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) SIG_EXPR_DECL_SINGLE(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) SIG_EXPR_LIST_DECL(VPOB6, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) SIG_EXPR_PTR(VPOB6, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) SIG_EXPR_PTR(VPOB6, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) SIG_EXPR_PTR(VPOB6, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) SIG_EXPR_LIST_ALIAS(R19, VPOB6, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PIN_DECL_1(R19, GPIOS4, VPOB6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define W20 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define W20_DESC SIG_DESC_SET(SCU8C, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) SIG_EXPR_DECL_SINGLE(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) SIG_EXPR_LIST_DECL(VPOB7, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) SIG_EXPR_PTR(VPOB7, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) SIG_EXPR_PTR(VPOB7, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) SIG_EXPR_PTR(VPOB7, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) SIG_EXPR_LIST_ALIAS(W20, VPOB7, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PIN_DECL_1(W20, GPIOS5, VPOB7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define U20 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define U20_DESC SIG_DESC_SET(SCU8C, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) SIG_EXPR_DECL_SINGLE(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) SIG_EXPR_LIST_DECL(VPOB8, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) SIG_EXPR_PTR(VPOB8, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) SIG_EXPR_PTR(VPOB8, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) SIG_EXPR_PTR(VPOB8, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) SIG_EXPR_LIST_ALIAS(U20, VPOB8, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) PIN_DECL_1(U20, GPIOS6, VPOB8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define AA20 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define AA20_DESC SIG_DESC_SET(SCU8C, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) SIG_EXPR_DECL_SINGLE(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) SIG_EXPR_LIST_DECL(VPOB9, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) SIG_EXPR_PTR(VPOB9, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) SIG_EXPR_PTR(VPOB9, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) SIG_EXPR_PTR(VPOB9, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) SIG_EXPR_LIST_ALIAS(AA20, VPOB9, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PIN_DECL_1(AA20, GPIOS7, VPOB9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* RGMII1/RMII1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define B5 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) SIG_EXPR_LIST_DECL_SINGLE(B5, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) SIG_EXPR_LIST_DECL_SINGLE(B5, RMII1RCLKO, RMII1, RMII1_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) SIG_DESC_SET(SCU48, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) SIG_EXPR_LIST_DECL_SINGLE(B5, RGMII1TXCK, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PIN_DECL_(B5, SIG_EXPR_LIST_PTR(B5, GPIOT0), SIG_EXPR_LIST_PTR(B5, RMII1RCLKO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) SIG_EXPR_LIST_PTR(B5, RGMII1TXCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) #define E9 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) SIG_EXPR_LIST_DECL_SINGLE(E9, RMII1TXEN, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII1TXCTL, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT1), SIG_EXPR_LIST_PTR(E9, RMII1TXEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) SIG_EXPR_LIST_PTR(E9, RGMII1TXCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define F9 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) SIG_EXPR_LIST_DECL_SINGLE(F9, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) SIG_EXPR_LIST_DECL_SINGLE(F9, RMII1TXD0, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) SIG_EXPR_LIST_DECL_SINGLE(F9, RGMII1TXD0, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PIN_DECL_(F9, SIG_EXPR_LIST_PTR(F9, GPIOT2), SIG_EXPR_LIST_PTR(F9, RMII1TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) SIG_EXPR_LIST_PTR(F9, RGMII1TXD0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define A5 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) SIG_EXPR_LIST_DECL_SINGLE(A5, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) SIG_EXPR_LIST_DECL_SINGLE(A5, RMII1TXD1, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) SIG_EXPR_LIST_DECL_SINGLE(A5, RGMII1TXD1, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PIN_DECL_(A5, SIG_EXPR_LIST_PTR(A5, GPIOT3), SIG_EXPR_LIST_PTR(A5, RMII1TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) SIG_EXPR_LIST_PTR(A5, RGMII1TXD1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define E7 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) SIG_EXPR_LIST_DECL_SINGLE(E7, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) SIG_EXPR_LIST_DECL_SINGLE(E7, RMII1DASH0, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) SIG_EXPR_LIST_DECL_SINGLE(E7, RGMII1TXD2, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PIN_DECL_(E7, SIG_EXPR_LIST_PTR(E7, GPIOT4), SIG_EXPR_LIST_PTR(E7, RMII1DASH0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) SIG_EXPR_LIST_PTR(E7, RGMII1TXD2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define D7 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) SIG_EXPR_LIST_DECL_SINGLE(D7, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) SIG_EXPR_LIST_DECL_SINGLE(D7, RMII1DASH1, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) SIG_EXPR_LIST_DECL_SINGLE(D7, RGMII1TXD3, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, GPIOT5), SIG_EXPR_LIST_PTR(D7, RMII1DASH1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) SIG_EXPR_LIST_PTR(D7, RGMII1TXD3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define B2 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) SIG_EXPR_LIST_DECL_SINGLE(B2, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) SIG_EXPR_LIST_DECL_SINGLE(B2, RMII2RCLKO, RMII2, RMII2_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) SIG_DESC_SET(SCU48, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) SIG_EXPR_LIST_DECL_SINGLE(B2, RGMII2TXCK, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PIN_DECL_(B2, SIG_EXPR_LIST_PTR(B2, GPIOT6), SIG_EXPR_LIST_PTR(B2, RMII2RCLKO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) SIG_EXPR_LIST_PTR(B2, RGMII2TXCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define B1 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) SIG_EXPR_LIST_DECL_SINGLE(B1, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) SIG_EXPR_LIST_DECL_SINGLE(B1, RMII2TXEN, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) SIG_EXPR_LIST_DECL_SINGLE(B1, RGMII2TXCTL, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PIN_DECL_(B1, SIG_EXPR_LIST_PTR(B1, GPIOT7), SIG_EXPR_LIST_PTR(B1, RMII2TXEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) SIG_EXPR_LIST_PTR(B1, RGMII2TXCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define A2 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) SIG_EXPR_LIST_DECL_SINGLE(A2, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) SIG_EXPR_LIST_DECL_SINGLE(A2, RMII2TXD0, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) SIG_EXPR_LIST_DECL_SINGLE(A2, RGMII2TXD0, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PIN_DECL_(A2, SIG_EXPR_LIST_PTR(A2, GPIOU0), SIG_EXPR_LIST_PTR(A2, RMII2TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) SIG_EXPR_LIST_PTR(A2, RGMII2TXD0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define B3 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) SIG_EXPR_LIST_DECL_SINGLE(B3, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) SIG_EXPR_LIST_DECL_SINGLE(B3, RMII2TXD1, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) SIG_EXPR_LIST_DECL_SINGLE(B3, RGMII2TXD1, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PIN_DECL_(B3, SIG_EXPR_LIST_PTR(B3, GPIOU1), SIG_EXPR_LIST_PTR(B3, RMII2TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) SIG_EXPR_LIST_PTR(B3, RGMII2TXD1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define D5 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) SIG_EXPR_LIST_DECL_SINGLE(D5, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) SIG_EXPR_LIST_DECL_SINGLE(D5, RMII2DASH0, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) SIG_EXPR_LIST_DECL_SINGLE(D5, RGMII2TXD2, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PIN_DECL_(D5, SIG_EXPR_LIST_PTR(D5, GPIOU2), SIG_EXPR_LIST_PTR(D5, RMII2DASH0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) SIG_EXPR_LIST_PTR(D5, RGMII2TXD2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define D4 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) SIG_EXPR_LIST_DECL_SINGLE(D4, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) SIG_EXPR_LIST_DECL_SINGLE(D4, RMII2DASH1, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) SIG_EXPR_LIST_DECL_SINGLE(D4, RGMII2TXD3, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PIN_DECL_(D4, SIG_EXPR_LIST_PTR(D4, GPIOU3), SIG_EXPR_LIST_PTR(D4, RMII2DASH1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) SIG_EXPR_LIST_PTR(D4, RGMII2TXD3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define B4 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) SIG_EXPR_LIST_DECL_SINGLE(B4, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) SIG_EXPR_LIST_DECL_SINGLE(B4, RMII1RCLKI, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) SIG_EXPR_LIST_DECL_SINGLE(B4, RGMII1RXCK, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, GPIOU4), SIG_EXPR_LIST_PTR(B4, RMII1RCLKI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) SIG_EXPR_LIST_PTR(B4, RGMII1RXCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define A4 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) SIG_EXPR_LIST_DECL_SINGLE(A4, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) SIG_EXPR_LIST_DECL_SINGLE(A4, RMII1DASH2, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) SIG_EXPR_LIST_DECL_SINGLE(A4, RGMII1RXCTL, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, GPIOU5), SIG_EXPR_LIST_PTR(A4, RMII1DASH2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) SIG_EXPR_LIST_PTR(A4, RGMII1RXCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define A3 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) SIG_EXPR_LIST_DECL_SINGLE(A3, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) SIG_EXPR_LIST_DECL_SINGLE(A3, RMII1RXD0, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) SIG_EXPR_LIST_DECL_SINGLE(A3, RGMII1RXD0, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PIN_DECL_(A3, SIG_EXPR_LIST_PTR(A3, GPIOU6), SIG_EXPR_LIST_PTR(A3, RMII1RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) SIG_EXPR_LIST_PTR(A3, RGMII1RXD0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define D6 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) SIG_EXPR_LIST_DECL_SINGLE(D6, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) SIG_EXPR_LIST_DECL_SINGLE(D6, RMII1RXD1, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) SIG_EXPR_LIST_DECL_SINGLE(D6, RGMII1RXD1, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PIN_DECL_(D6, SIG_EXPR_LIST_PTR(D6, GPIOU7), SIG_EXPR_LIST_PTR(D6, RMII1RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) SIG_EXPR_LIST_PTR(D6, RGMII1RXD1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define C5 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) SIG_EXPR_LIST_DECL_SINGLE(C5, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) SIG_EXPR_LIST_DECL_SINGLE(C5, RMII1CRSDV, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) SIG_EXPR_LIST_DECL_SINGLE(C5, RGMII1RXD2, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PIN_DECL_(C5, SIG_EXPR_LIST_PTR(C5, GPIOV0), SIG_EXPR_LIST_PTR(C5, RMII1CRSDV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) SIG_EXPR_LIST_PTR(C5, RGMII1RXD2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define C4 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) SIG_EXPR_LIST_DECL_SINGLE(C4, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) SIG_EXPR_LIST_DECL_SINGLE(C4, RMII1RXER, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) SIG_EXPR_LIST_DECL_SINGLE(C4, RGMII1RXD3, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PIN_DECL_(C4, SIG_EXPR_LIST_PTR(C4, GPIOV1), SIG_EXPR_LIST_PTR(C4, RMII1RXER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) SIG_EXPR_LIST_PTR(C4, RGMII1RXD3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define C2 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) SIG_EXPR_LIST_DECL_SINGLE(C2, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) SIG_EXPR_LIST_DECL_SINGLE(C2, RMII2RCLKI, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) SIG_EXPR_LIST_DECL_SINGLE(C2, RGMII2RXCK, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) PIN_DECL_(C2, SIG_EXPR_LIST_PTR(C2, GPIOV2), SIG_EXPR_LIST_PTR(C2, RMII2RCLKI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) SIG_EXPR_LIST_PTR(C2, RGMII2RXCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define C1 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) SIG_EXPR_LIST_DECL_SINGLE(C1, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) SIG_EXPR_LIST_DECL_SINGLE(C1, RMII2DASH2, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) SIG_EXPR_LIST_DECL_SINGLE(C1, RGMII2RXCTL, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PIN_DECL_(C1, SIG_EXPR_LIST_PTR(C1, GPIOV3), SIG_EXPR_LIST_PTR(C1, RMII2DASH2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) SIG_EXPR_LIST_PTR(C1, RGMII2RXCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define C3 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) SIG_EXPR_LIST_DECL_SINGLE(C3, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) SIG_EXPR_LIST_DECL_SINGLE(C3, RMII2RXD0, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) SIG_EXPR_LIST_DECL_SINGLE(C3, RGMII2RXD0, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) PIN_DECL_(C3, SIG_EXPR_LIST_PTR(C3, GPIOV4), SIG_EXPR_LIST_PTR(C3, RMII2RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) SIG_EXPR_LIST_PTR(C3, RGMII2RXD0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define D1 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) SIG_EXPR_LIST_DECL_SINGLE(D1, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) SIG_EXPR_LIST_DECL_SINGLE(D1, RMII2RXD1, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) SIG_EXPR_LIST_DECL_SINGLE(D1, RGMII2RXD1, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) PIN_DECL_(D1, SIG_EXPR_LIST_PTR(D1, GPIOV5), SIG_EXPR_LIST_PTR(D1, RMII2RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) SIG_EXPR_LIST_PTR(D1, RGMII2RXD1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define D2 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) SIG_EXPR_LIST_DECL_SINGLE(D2, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) SIG_EXPR_LIST_DECL_SINGLE(D2, RMII2CRSDV, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) SIG_EXPR_LIST_DECL_SINGLE(D2, RGMII2RXD2, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) PIN_DECL_(D2, SIG_EXPR_LIST_PTR(D2, GPIOV6), SIG_EXPR_LIST_PTR(D2, RMII2CRSDV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) SIG_EXPR_LIST_PTR(D2, RGMII2RXD2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define E6 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) SIG_EXPR_LIST_DECL_SINGLE(E6, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) SIG_EXPR_LIST_DECL_SINGLE(E6, RMII2RXER, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) SIG_EXPR_LIST_DECL_SINGLE(E6, RGMII2RXD3, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) PIN_DECL_(E6, SIG_EXPR_LIST_PTR(E6, GPIOV7), SIG_EXPR_LIST_PTR(E6, RMII2RXER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) SIG_EXPR_LIST_PTR(E6, RGMII2RXD3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define F4 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) SIG_EXPR_LIST_DECL_SINGLE(F4, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) SIG_EXPR_LIST_DECL_SINGLE(F4, ADC0, ADC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PIN_DECL_(F4, SIG_EXPR_LIST_PTR(F4, GPIOW0), SIG_EXPR_LIST_PTR(F4, ADC0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) FUNC_GROUP_DECL(ADC0, F4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define F5 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) SIG_EXPR_LIST_DECL_SINGLE(F5, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) SIG_EXPR_LIST_DECL_SINGLE(F5, ADC1, ADC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) PIN_DECL_(F5, SIG_EXPR_LIST_PTR(F5, GPIOW1), SIG_EXPR_LIST_PTR(F5, ADC1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) FUNC_GROUP_DECL(ADC1, F5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define E2 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) SIG_EXPR_LIST_DECL_SINGLE(E2, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) SIG_EXPR_LIST_DECL_SINGLE(E2, ADC2, ADC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) PIN_DECL_(E2, SIG_EXPR_LIST_PTR(E2, GPIOW2), SIG_EXPR_LIST_PTR(E2, ADC2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) FUNC_GROUP_DECL(ADC2, E2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define E1 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) SIG_EXPR_LIST_DECL_SINGLE(E1, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) SIG_EXPR_LIST_DECL_SINGLE(E1, ADC3, ADC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) PIN_DECL_(E1, SIG_EXPR_LIST_PTR(E1, GPIOW3), SIG_EXPR_LIST_PTR(E1, ADC3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) FUNC_GROUP_DECL(ADC3, E1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define F3 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) SIG_EXPR_LIST_DECL_SINGLE(F3, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) SIG_EXPR_LIST_DECL_SINGLE(F3, ADC4, ADC4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PIN_DECL_(F3, SIG_EXPR_LIST_PTR(F3, GPIOW4), SIG_EXPR_LIST_PTR(F3, ADC4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) FUNC_GROUP_DECL(ADC4, F3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define E3 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) SIG_EXPR_LIST_DECL_SINGLE(E3, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) SIG_EXPR_LIST_DECL_SINGLE(E3, ADC5, ADC5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PIN_DECL_(E3, SIG_EXPR_LIST_PTR(E3, GPIOW5), SIG_EXPR_LIST_PTR(E3, ADC5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) FUNC_GROUP_DECL(ADC5, E3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define G5 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) SIG_EXPR_LIST_DECL_SINGLE(G5, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) SIG_EXPR_LIST_DECL_SINGLE(G5, ADC6, ADC6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) PIN_DECL_(G5, SIG_EXPR_LIST_PTR(G5, GPIOW6), SIG_EXPR_LIST_PTR(G5, ADC6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) FUNC_GROUP_DECL(ADC6, G5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define G4 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) SIG_EXPR_LIST_DECL_SINGLE(G4, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) SIG_EXPR_LIST_DECL_SINGLE(G4, ADC7, ADC7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PIN_DECL_(G4, SIG_EXPR_LIST_PTR(G4, GPIOW7), SIG_EXPR_LIST_PTR(G4, ADC7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) FUNC_GROUP_DECL(ADC7, G4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define F2 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) SIG_EXPR_LIST_DECL_SINGLE(F2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) SIG_EXPR_LIST_DECL_SINGLE(F2, ADC8, ADC8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PIN_DECL_(F2, SIG_EXPR_LIST_PTR(F2, GPIOX0), SIG_EXPR_LIST_PTR(F2, ADC8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) FUNC_GROUP_DECL(ADC8, F2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define G3 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) SIG_EXPR_LIST_DECL_SINGLE(G3, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) SIG_EXPR_LIST_DECL_SINGLE(G3, ADC9, ADC9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) PIN_DECL_(G3, SIG_EXPR_LIST_PTR(G3, GPIOX1), SIG_EXPR_LIST_PTR(G3, ADC9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) FUNC_GROUP_DECL(ADC9, G3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define G2 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) SIG_EXPR_LIST_DECL_SINGLE(G2, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) SIG_EXPR_LIST_DECL_SINGLE(G2, ADC10, ADC10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) PIN_DECL_(G2, SIG_EXPR_LIST_PTR(G2, GPIOX2), SIG_EXPR_LIST_PTR(G2, ADC10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) FUNC_GROUP_DECL(ADC10, G2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define F1 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) SIG_EXPR_LIST_DECL_SINGLE(F1, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) SIG_EXPR_LIST_DECL_SINGLE(F1, ADC11, ADC11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PIN_DECL_(F1, SIG_EXPR_LIST_PTR(F1, GPIOX3), SIG_EXPR_LIST_PTR(F1, ADC11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) FUNC_GROUP_DECL(ADC11, F1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define H5 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) SIG_EXPR_LIST_DECL_SINGLE(H5, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) SIG_EXPR_LIST_DECL_SINGLE(H5, ADC12, ADC12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PIN_DECL_(H5, SIG_EXPR_LIST_PTR(H5, GPIOX4), SIG_EXPR_LIST_PTR(H5, ADC12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) FUNC_GROUP_DECL(ADC12, H5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define G1 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) SIG_EXPR_LIST_DECL_SINGLE(G1, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) SIG_EXPR_LIST_DECL_SINGLE(G1, ADC13, ADC13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) PIN_DECL_(G1, SIG_EXPR_LIST_PTR(G1, GPIOX5), SIG_EXPR_LIST_PTR(G1, ADC13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) FUNC_GROUP_DECL(ADC13, G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define H3 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) SIG_EXPR_LIST_DECL_SINGLE(H3, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) SIG_EXPR_LIST_DECL_SINGLE(H3, ADC14, ADC14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) PIN_DECL_(H3, SIG_EXPR_LIST_PTR(H3, GPIOX6), SIG_EXPR_LIST_PTR(H3, ADC14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) FUNC_GROUP_DECL(ADC14, H3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define H4 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) SIG_EXPR_LIST_DECL_SINGLE(H4, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) SIG_EXPR_LIST_DECL_SINGLE(H4, ADC15, ADC15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) PIN_DECL_(H4, SIG_EXPR_LIST_PTR(H4, GPIOX7), SIG_EXPR_LIST_PTR(H4, ADC15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) FUNC_GROUP_DECL(ADC15, H4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define R22 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) SIG_EXPR_LIST_DECL_DUAL(R22, SIOS3, SIOS3, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) SIG_EXPR_LIST_DECL_SINGLE(R22, DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) PIN_DECL_2(R22, GPIOY0, SIOS3, DASHR22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) FUNC_GROUP_DECL(SIOS3, R22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define R21 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) SIG_EXPR_LIST_DECL_DUAL(R21, SIOS5, SIOS5, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) SIG_EXPR_LIST_DECL_SINGLE(R21, DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) PIN_DECL_2(R21, GPIOY1, SIOS5, DASHR21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) FUNC_GROUP_DECL(SIOS5, R21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define P22 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) SIG_EXPR_LIST_DECL_DUAL(P22, SIOPWREQ, SIOPWREQ, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) SIG_EXPR_LIST_DECL_SINGLE(P22, DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) PIN_DECL_2(P22, GPIOY2, SIOPWREQ, DASHP22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) FUNC_GROUP_DECL(SIOPWREQ, P22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define P21 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) SIG_EXPR_LIST_DECL_DUAL(P21, SIOONCTRL, SIOONCTRL, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) SIG_EXPR_LIST_DECL_SINGLE(P21, DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) PIN_DECL_2(P21, GPIOY3, SIOONCTRL, DASHP21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) FUNC_GROUP_DECL(SIOONCTRL, P21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) #define M18 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define M19 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #define M20 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define P20 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) #define PNOR_DESC SIG_DESC_SET(SCU90, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #define Y20 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define Y20_DESC SIG_DESC_SET(SCUA4, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) SIG_EXPR_DECL_SINGLE(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) SIG_EXPR_LIST_DECL(VPOG2, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) SIG_EXPR_PTR(VPOG2, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) SIG_EXPR_PTR(VPOG2, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) SIG_EXPR_PTR(VPOG2, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) SIG_EXPR_LIST_ALIAS(Y20, VPOG2, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, Y20_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, Y20_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) SIG_EXPR_LIST_DECL_DUAL(Y20, SIOPBI, SIOPBI, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) SIG_EXPR_LIST_DECL_SINGLE(Y20, NORA0, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) SIG_EXPR_LIST_DECL_SINGLE(Y20, GPIOZ0, GPIOZ0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(Y20, VPOG2), SIG_EXPR_LIST_PTR(Y20, SIOPBI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) SIG_EXPR_LIST_PTR(Y20, NORA0), SIG_EXPR_LIST_PTR(Y20, GPIOZ0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) FUNC_GROUP_DECL(SIOPBI, Y20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define AB20 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define AB20_DESC SIG_DESC_SET(SCUA4, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) SIG_EXPR_DECL_SINGLE(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) SIG_EXPR_LIST_DECL(VPOG3, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) SIG_EXPR_PTR(VPOG3, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) SIG_EXPR_PTR(VPOG3, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) SIG_EXPR_PTR(VPOG3, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) SIG_EXPR_LIST_ALIAS(AB20, VPOG3, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, AB20_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, AB20_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) SIG_EXPR_LIST_DECL_DUAL(AB20, SIOPWRGD, SIOPWRGD, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) SIG_EXPR_LIST_DECL_SINGLE(AB20, NORA1, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) SIG_EXPR_LIST_DECL_SINGLE(AB20, GPIOZ1, GPIOZ1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, VPOG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) SIG_EXPR_LIST_PTR(AB20, SIOPWRGD), SIG_EXPR_LIST_PTR(AB20, NORA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) SIG_EXPR_LIST_PTR(AB20, GPIOZ1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) FUNC_GROUP_DECL(SIOPWRGD, AB20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #define AB21 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define AB21_DESC SIG_DESC_SET(SCUA4, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) SIG_EXPR_DECL_SINGLE(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) SIG_EXPR_LIST_DECL(VPOG4, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) SIG_EXPR_PTR(VPOG4, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) SIG_EXPR_PTR(VPOG4, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) SIG_EXPR_PTR(VPOG4, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) SIG_EXPR_LIST_ALIAS(AB21, VPOG4, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, AB21_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, AB21_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) SIG_EXPR_LIST_DECL_DUAL(AB21, SIOPBO, SIOPBO, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) SIG_EXPR_LIST_DECL_SINGLE(AB21, NORA2, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) SIG_EXPR_LIST_DECL_SINGLE(AB21, GPIOZ2, GPIOZ2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, VPOG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) SIG_EXPR_LIST_PTR(AB21, SIOPBO), SIG_EXPR_LIST_PTR(AB21, NORA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) SIG_EXPR_LIST_PTR(AB21, GPIOZ2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) FUNC_GROUP_DECL(SIOPBO, AB21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define AA21 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define AA21_DESC SIG_DESC_SET(SCUA4, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) SIG_EXPR_DECL_SINGLE(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) SIG_EXPR_LIST_DECL(VPOG5, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) SIG_EXPR_PTR(VPOG5, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) SIG_EXPR_PTR(VPOG5, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) SIG_EXPR_PTR(VPOG5, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) SIG_EXPR_LIST_ALIAS(AA21, VPOG5, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, AA21_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, AA21_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) SIG_EXPR_LIST_DECL_DUAL(AA21, SIOSCI, SIOSCI, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) SIG_EXPR_LIST_DECL_SINGLE(AA21, NORA3, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) SIG_EXPR_LIST_DECL_SINGLE(AA21, GPIOZ3, GPIOZ3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(AA21, VPOG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) SIG_EXPR_LIST_PTR(AA21, SIOSCI), SIG_EXPR_LIST_PTR(AA21, NORA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) SIG_EXPR_LIST_PTR(AA21, GPIOZ3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) FUNC_GROUP_DECL(SIOSCI, AA21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /* CRT DVO disabled, configured for single-edge mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /* CRT DVO disabled, configured for dual-edge mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /* CRT DVO enabled, configured for single-edge mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) #define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /* CRT DVO enabled, configured for dual-edge mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define U21 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define U21_DESC SIG_DESC_SET(SCUA4, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) SIG_EXPR_DECL_SINGLE(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) SIG_EXPR_LIST_DECL(VPOG6, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) SIG_EXPR_PTR(VPOG6, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) SIG_EXPR_PTR(VPOG6, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) SIG_EXPR_PTR(VPOG6, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) SIG_EXPR_LIST_ALIAS(U21, VPOG6, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) SIG_EXPR_LIST_DECL_SINGLE(U21, NORA4, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) PIN_DECL_2(U21, GPIOZ4, VPOG6, NORA4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) #define W22 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) #define W22_DESC SIG_DESC_SET(SCUA4, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) SIG_EXPR_DECL_SINGLE(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) SIG_EXPR_LIST_DECL(VPOG7, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) SIG_EXPR_PTR(VPOG7, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) SIG_EXPR_PTR(VPOG7, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) SIG_EXPR_PTR(VPOG7, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) SIG_EXPR_LIST_ALIAS(W22, VPOG7, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) SIG_EXPR_LIST_DECL_SINGLE(W22, NORA5, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) PIN_DECL_2(W22, GPIOZ5, VPOG7, NORA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) #define V22 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #define V22_DESC SIG_DESC_SET(SCUA4, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) SIG_EXPR_DECL_SINGLE(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) SIG_EXPR_LIST_DECL(VPOG8, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) SIG_EXPR_PTR(VPOG8, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) SIG_EXPR_PTR(VPOG8, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) SIG_EXPR_PTR(VPOG8, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) SIG_EXPR_LIST_ALIAS(V22, VPOG8, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) SIG_EXPR_LIST_DECL_SINGLE(V22, NORA6, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) PIN_DECL_2(V22, GPIOZ6, VPOG8, NORA6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define W21 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define W21_DESC SIG_DESC_SET(SCUA4, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) SIG_EXPR_DECL_SINGLE(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) SIG_EXPR_LIST_DECL(VPOG9, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) SIG_EXPR_PTR(VPOG9, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) SIG_EXPR_PTR(VPOG9, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) SIG_EXPR_PTR(VPOG9, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) SIG_EXPR_LIST_ALIAS(W21, VPOG9, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) SIG_EXPR_LIST_DECL_SINGLE(W21, NORA7, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) PIN_DECL_2(W21, GPIOZ7, VPOG9, NORA7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define Y21 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #define Y21_DESC SIG_DESC_SET(SCUA4, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) SIG_EXPR_DECL_SINGLE(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) SIG_EXPR_LIST_DECL(VPOR2, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) SIG_EXPR_PTR(VPOR2, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) SIG_EXPR_PTR(VPOR2, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) SIG_EXPR_PTR(VPOR2, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) SIG_EXPR_LIST_ALIAS(Y21, VPOR2, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) SIG_EXPR_LIST_DECL_SINGLE(Y21, SALT7, SALT7, Y21_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) SIG_EXPR_LIST_DECL_SINGLE(Y21, NORD0, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) SIG_EXPR_LIST_DECL_SINGLE(Y21, GPIOAA0, GPIOAA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(Y21, VPOR2), SIG_EXPR_LIST_PTR(Y21, SALT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) SIG_EXPR_LIST_PTR(Y21, NORD0), SIG_EXPR_LIST_PTR(Y21, GPIOAA0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) FUNC_GROUP_DECL(SALT7, Y21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define V21 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #define V21_DESC SIG_DESC_SET(SCUA4, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) SIG_EXPR_DECL_SINGLE(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) SIG_EXPR_LIST_DECL(VPOR3, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) SIG_EXPR_PTR(VPOR3, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) SIG_EXPR_PTR(VPOR3, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) SIG_EXPR_PTR(VPOR3, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) SIG_EXPR_LIST_ALIAS(V21, VPOR3, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) SIG_EXPR_LIST_DECL_SINGLE(V21, SALT8, SALT8, V21_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) SIG_EXPR_LIST_DECL_SINGLE(V21, NORD1, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) SIG_EXPR_LIST_DECL_SINGLE(V21, GPIOAA1, GPIOAA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) PIN_DECL_(V21, SIG_EXPR_LIST_PTR(V21, VPOR3), SIG_EXPR_LIST_PTR(V21, SALT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) SIG_EXPR_LIST_PTR(V21, NORD1), SIG_EXPR_LIST_PTR(V21, GPIOAA1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) FUNC_GROUP_DECL(SALT8, V21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) #define Y22 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #define Y22_DESC SIG_DESC_SET(SCUA4, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) SIG_EXPR_DECL_SINGLE(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) SIG_EXPR_LIST_DECL(VPOR4, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) SIG_EXPR_PTR(VPOR4, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) SIG_EXPR_PTR(VPOR4, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) SIG_EXPR_PTR(VPOR4, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) SIG_EXPR_LIST_ALIAS(Y22, VPOR4, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) SIG_EXPR_LIST_DECL_SINGLE(Y22, SALT9, SALT9, Y22_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) SIG_EXPR_LIST_DECL_SINGLE(Y22, NORD2, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) SIG_EXPR_LIST_DECL_SINGLE(Y22, GPIOAA2, GPIOAA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(Y22, VPOR4), SIG_EXPR_LIST_PTR(Y22, SALT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) SIG_EXPR_LIST_PTR(Y22, NORD2), SIG_EXPR_LIST_PTR(Y22, GPIOAA2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) FUNC_GROUP_DECL(SALT9, Y22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define AA22 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #define AA22_DESC SIG_DESC_SET(SCUA4, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) SIG_EXPR_DECL_SINGLE(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) SIG_EXPR_LIST_DECL(VPOR5, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) SIG_EXPR_PTR(VPOR5, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) SIG_EXPR_PTR(VPOR5, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) SIG_EXPR_PTR(VPOR5, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) SIG_EXPR_LIST_ALIAS(AA22, VPOR5, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) SIG_EXPR_LIST_DECL_SINGLE(AA22, SALT10, SALT10, AA22_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) SIG_EXPR_LIST_DECL_SINGLE(AA22, NORD3, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) SIG_EXPR_LIST_DECL_SINGLE(AA22, GPIOAA3, GPIOAA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(AA22, VPOR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) SIG_EXPR_LIST_PTR(AA22, SALT10), SIG_EXPR_LIST_PTR(AA22, NORD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) SIG_EXPR_LIST_PTR(AA22, GPIOAA3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) FUNC_GROUP_DECL(SALT10, AA22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) #define U22 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define U22_DESC SIG_DESC_SET(SCUA4, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) SIG_EXPR_DECL_SINGLE(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) SIG_EXPR_LIST_DECL(VPOR6, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) SIG_EXPR_PTR(VPOR6, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) SIG_EXPR_PTR(VPOR6, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) SIG_EXPR_PTR(VPOR6, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) SIG_EXPR_LIST_ALIAS(U22, VPOR6, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) SIG_EXPR_LIST_DECL_SINGLE(U22, SALT11, SALT11, U22_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) SIG_EXPR_LIST_DECL_SINGLE(U22, NORD4, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) SIG_EXPR_LIST_DECL_SINGLE(U22, GPIOAA4, GPIOAA4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) PIN_DECL_(U22, SIG_EXPR_LIST_PTR(U22, VPOR6), SIG_EXPR_LIST_PTR(U22, SALT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) SIG_EXPR_LIST_PTR(U22, NORD4), SIG_EXPR_LIST_PTR(U22, GPIOAA4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) FUNC_GROUP_DECL(SALT11, U22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) #define T20 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #define T20_DESC SIG_DESC_SET(SCUA4, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) SIG_EXPR_DECL_SINGLE(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) SIG_EXPR_LIST_DECL(VPOR7, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) SIG_EXPR_PTR(VPOR7, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) SIG_EXPR_PTR(VPOR7, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) SIG_EXPR_PTR(VPOR7, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) SIG_EXPR_LIST_ALIAS(T20, VPOR7, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) SIG_EXPR_LIST_DECL_SINGLE(T20, SALT12, SALT12, T20_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) SIG_EXPR_LIST_DECL_SINGLE(T20, NORD5, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) SIG_EXPR_LIST_DECL_SINGLE(T20, GPIOAA5, GPIOAA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) PIN_DECL_(T20, SIG_EXPR_LIST_PTR(T20, VPOR7), SIG_EXPR_LIST_PTR(T20, SALT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) SIG_EXPR_LIST_PTR(T20, NORD5), SIG_EXPR_LIST_PTR(T20, GPIOAA5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) FUNC_GROUP_DECL(SALT12, T20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #define N18 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) #define N18_DESC SIG_DESC_SET(SCUA4, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) SIG_EXPR_DECL_SINGLE(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) SIG_EXPR_LIST_DECL(VPOR8, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) SIG_EXPR_PTR(VPOR8, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) SIG_EXPR_PTR(VPOR8, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) SIG_EXPR_PTR(VPOR8, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) SIG_EXPR_LIST_ALIAS(N18, VPOR8, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) SIG_EXPR_LIST_DECL_SINGLE(N18, SALT13, SALT13, N18_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) SIG_EXPR_LIST_DECL_SINGLE(N18, NORD6, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) SIG_EXPR_LIST_DECL_SINGLE(N18, GPIOAA6, GPIOAA6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) PIN_DECL_(N18, SIG_EXPR_LIST_PTR(N18, VPOR8), SIG_EXPR_LIST_PTR(N18, SALT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) SIG_EXPR_LIST_PTR(N18, NORD6), SIG_EXPR_LIST_PTR(N18, GPIOAA6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) FUNC_GROUP_DECL(SALT13, N18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) #define P19 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #define P19_DESC SIG_DESC_SET(SCUA4, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) SIG_EXPR_DECL_SINGLE(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) SIG_EXPR_LIST_DECL(VPOR9, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) SIG_EXPR_PTR(VPOR9, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) SIG_EXPR_PTR(VPOR9, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) SIG_EXPR_PTR(VPOR9, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) SIG_EXPR_LIST_ALIAS(P19, VPOR9, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) SIG_EXPR_LIST_DECL_SINGLE(P19, SALT14, SALT14, P19_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) SIG_EXPR_LIST_DECL_SINGLE(P19, NORD7, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) SIG_EXPR_LIST_DECL_SINGLE(P19, GPIOAA7, GPIOAA7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) PIN_DECL_(P19, SIG_EXPR_LIST_PTR(P19, VPOR9), SIG_EXPR_LIST_PTR(P19, SALT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) SIG_EXPR_LIST_PTR(P19, NORD7), SIG_EXPR_LIST_PTR(P19, GPIOAA7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) FUNC_GROUP_DECL(SALT14, P19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #define N19 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #define N19_DESC SIG_DESC_SET(SCUA8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) SIG_EXPR_DECL_SINGLE(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) SIG_EXPR_LIST_DECL(VPODE, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) SIG_EXPR_PTR(VPODE, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) SIG_EXPR_PTR(VPODE, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) SIG_EXPR_PTR(VPODE, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) SIG_EXPR_LIST_ALIAS(N19, VPODE, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) SIG_EXPR_LIST_DECL_SINGLE(N19, NOROE, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) PIN_DECL_2(N19, GPIOAB0, VPODE, NOROE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define T21 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define T21_DESC SIG_DESC_SET(SCUA8, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) SIG_EXPR_DECL_SINGLE(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) SIG_EXPR_LIST_DECL(VPOHS, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) SIG_EXPR_PTR(VPOHS, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) SIG_EXPR_PTR(VPOHS, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) SIG_EXPR_PTR(VPOHS, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) SIG_EXPR_LIST_ALIAS(T21, VPOHS, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) SIG_EXPR_LIST_DECL_SINGLE(T21, NORWE, PNOR, PNOR_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) PIN_DECL_2(T21, GPIOAB1, VPOHS, NORWE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) AA22, U22, T20, N18, P19, N19, T21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define T22 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define T22_DESC SIG_DESC_SET(SCUA8, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) SIG_EXPR_DECL_SINGLE(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) SIG_EXPR_LIST_DECL(VPOVS, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) SIG_EXPR_PTR(VPOVS, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) SIG_EXPR_PTR(VPOVS, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) SIG_EXPR_PTR(VPOVS, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) SIG_EXPR_LIST_ALIAS(T22, VPOVS, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) SIG_EXPR_LIST_DECL_SINGLE(T22, WDTRST1, WDTRST1, T22_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) PIN_DECL_2(T22, GPIOAB2, VPOVS, WDTRST1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) FUNC_GROUP_DECL(WDTRST1, T22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) #define R20 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #define R20_DESC SIG_DESC_SET(SCUA8, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) SIG_EXPR_DECL_SINGLE(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) SIG_EXPR_LIST_DECL(VPOCLK, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) SIG_EXPR_PTR(VPOCLK, VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) SIG_EXPR_PTR(VPOCLK, VPOOFF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) SIG_EXPR_PTR(VPOCLK, VPOOFF2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) SIG_EXPR_LIST_ALIAS(R20, VPOCLK, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) SIG_EXPR_LIST_DECL_SINGLE(R20, WDTRST2, WDTRST2, R20_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) PIN_DECL_2(R20, GPIOAB3, VPOCLK, WDTRST2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) FUNC_GROUP_DECL(WDTRST2, R20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) N18, P19, N19, T21, T22, R20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) #define G21 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) SIG_EXPR_LIST_DECL_SINGLE(G21, ESPID0, ESPI, ESPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) SIG_EXPR_LIST_DECL_SINGLE(G21, LAD0, LAD0, SIG_DESC_SET(SCUAC, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) PIN_DECL_2(G21, GPIOAC0, ESPID0, LAD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) FUNC_GROUP_DECL(LAD0, G21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #define G20 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) SIG_EXPR_LIST_DECL_SINGLE(G20, ESPID1, ESPI, ESPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) SIG_EXPR_LIST_DECL_SINGLE(G20, LAD1, LAD1, SIG_DESC_SET(SCUAC, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) PIN_DECL_2(G20, GPIOAC1, ESPID1, LAD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) FUNC_GROUP_DECL(LAD1, G20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #define D22 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) SIG_EXPR_LIST_DECL_SINGLE(D22, ESPID2, ESPI, ESPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) SIG_EXPR_LIST_DECL_SINGLE(D22, LAD2, LAD2, SIG_DESC_SET(SCUAC, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) PIN_DECL_2(D22, GPIOAC2, ESPID2, LAD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) FUNC_GROUP_DECL(LAD2, D22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) #define E22 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) SIG_EXPR_LIST_DECL_SINGLE(E22, ESPID3, ESPI, ESPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) SIG_EXPR_LIST_DECL_SINGLE(E22, LAD3, LAD3, SIG_DESC_SET(SCUAC, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) PIN_DECL_2(E22, GPIOAC3, ESPID3, LAD3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) FUNC_GROUP_DECL(LAD3, E22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #define C22 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) SIG_EXPR_LIST_DECL_SINGLE(C22, ESPICK, ESPI, ESPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) SIG_EXPR_LIST_DECL_SINGLE(C22, LCLK, LCLK, SIG_DESC_SET(SCUAC, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) PIN_DECL_2(C22, GPIOAC4, ESPICK, LCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) FUNC_GROUP_DECL(LCLK, C22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) #define F21 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) SIG_EXPR_LIST_DECL_SINGLE(F21, ESPICS, ESPI, ESPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) SIG_EXPR_LIST_DECL_SINGLE(F21, LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) PIN_DECL_2(F21, GPIOAC5, ESPICS, LFRAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) FUNC_GROUP_DECL(LFRAME, F21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define F22 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) SIG_EXPR_LIST_DECL_SINGLE(F22, ESPIALT, ESPI, ESPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) SIG_EXPR_LIST_DECL_SINGLE(F22, LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) PIN_DECL_2(F22, GPIOAC6, ESPIALT, LSIRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) FUNC_GROUP_DECL(LSIRQ, F22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define G22 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) SIG_EXPR_LIST_DECL_SINGLE(G22, ESPIRST, ESPI, ESPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) SIG_EXPR_LIST_DECL_SINGLE(G22, LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) PIN_DECL_2(G22, GPIOAC7, ESPIRST, LPCRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) FUNC_GROUP_DECL(LPCRST, G22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #define A7 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) SIG_EXPR_LIST_DECL_SINGLE(A7, USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) SIG_EXPR_LIST_DECL_SINGLE(A7, USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) PIN_DECL_(A7, SIG_EXPR_LIST_PTR(A7, USB2AHDP), SIG_EXPR_LIST_PTR(A7, USB2ADDP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define A8 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) SIG_EXPR_LIST_DECL_SINGLE(A8, USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) SIG_EXPR_LIST_DECL_SINGLE(A8, USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) PIN_DECL_(A8, SIG_EXPR_LIST_PTR(A8, USB2AHDN), SIG_EXPR_LIST_PTR(A8, USB2ADDN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) FUNC_GROUP_DECL(USB2AH, A7, A8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) FUNC_GROUP_DECL(USB2AD, A7, A8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) #define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) #define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) #define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) #define B6 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) SIG_EXPR_LIST_DECL_SINGLE(B6, USB11BDP, USB11BHID, USB11BHID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) SIG_EXPR_LIST_DECL_SINGLE(B6, USB2BDDP, USB2BD, USB2BD_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) SIG_EXPR_DECL_SINGLE(USB2BHDP1, USB2BH, USB2BH1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) SIG_EXPR_DECL_SINGLE(USB2BHDP2, USB2BH, USB2BH2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) SIG_EXPR_LIST_DECL(USB2BHDP, USB2BH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) SIG_EXPR_PTR(USB2BHDP1, USB2BH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) SIG_EXPR_PTR(USB2BHDP2, USB2BH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) SIG_EXPR_LIST_ALIAS(B6, USB2BHDP, USB2BH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDP), SIG_EXPR_LIST_PTR(B6, USB2BDDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) SIG_EXPR_LIST_PTR(B6, USB2BHDP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #define A6 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) SIG_EXPR_LIST_DECL_SINGLE(A6, USB11BDN, USB11BHID, USB11BHID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) SIG_EXPR_LIST_DECL_SINGLE(A6, USB2BDN, USB2BD, USB2BD_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) SIG_EXPR_DECL_SINGLE(USB2BHDN1, USB2BH, USB2BH1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) SIG_EXPR_DECL_SINGLE(USB2BHDN2, USB2BH, USB2BH2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) SIG_EXPR_LIST_DECL(USB2BHDN, USB2BH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) SIG_EXPR_PTR(USB2BHDN1, USB2BH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) SIG_EXPR_PTR(USB2BHDN2, USB2BH));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) SIG_EXPR_LIST_ALIAS(A6, USB2BHDN, USB2BH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDN), SIG_EXPR_LIST_PTR(A6, USB2BDN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) SIG_EXPR_LIST_PTR(A6, USB2BHDN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) FUNC_GROUP_DECL(USB11BHID, B6, A6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) FUNC_GROUP_DECL(USB2BD, B6, A6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) FUNC_GROUP_DECL(USB2BH, B6, A6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ASPEED_PINCTRL_PIN(A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) ASPEED_PINCTRL_PIN(A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) ASPEED_PINCTRL_PIN(A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) ASPEED_PINCTRL_PIN(A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) ASPEED_PINCTRL_PIN(A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) ASPEED_PINCTRL_PIN(A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) ASPEED_PINCTRL_PIN(A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) ASPEED_PINCTRL_PIN(A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) ASPEED_PINCTRL_PIN(A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) ASPEED_PINCTRL_PIN(A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ASPEED_PINCTRL_PIN(A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) ASPEED_PINCTRL_PIN(A20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ASPEED_PINCTRL_PIN(A21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) ASPEED_PINCTRL_PIN(A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) ASPEED_PINCTRL_PIN(A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) ASPEED_PINCTRL_PIN(A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) ASPEED_PINCTRL_PIN(A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) ASPEED_PINCTRL_PIN(A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ASPEED_PINCTRL_PIN(A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) ASPEED_PINCTRL_PIN(A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ASPEED_PINCTRL_PIN(AA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) ASPEED_PINCTRL_PIN(AA19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) ASPEED_PINCTRL_PIN(AA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ASPEED_PINCTRL_PIN(AA20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) ASPEED_PINCTRL_PIN(AA21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) ASPEED_PINCTRL_PIN(AA22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) ASPEED_PINCTRL_PIN(AA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) ASPEED_PINCTRL_PIN(AA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) ASPEED_PINCTRL_PIN(AA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ASPEED_PINCTRL_PIN(AB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) ASPEED_PINCTRL_PIN(AB20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) ASPEED_PINCTRL_PIN(AB21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) ASPEED_PINCTRL_PIN(AB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) ASPEED_PINCTRL_PIN(AB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) ASPEED_PINCTRL_PIN(AB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) ASPEED_PINCTRL_PIN(B1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) ASPEED_PINCTRL_PIN(B10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) ASPEED_PINCTRL_PIN(B11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) ASPEED_PINCTRL_PIN(B12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) ASPEED_PINCTRL_PIN(B13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ASPEED_PINCTRL_PIN(B14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) ASPEED_PINCTRL_PIN(B15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) ASPEED_PINCTRL_PIN(B16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) ASPEED_PINCTRL_PIN(B17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) ASPEED_PINCTRL_PIN(B18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) ASPEED_PINCTRL_PIN(B19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) ASPEED_PINCTRL_PIN(B2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) ASPEED_PINCTRL_PIN(B20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) ASPEED_PINCTRL_PIN(B21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) ASPEED_PINCTRL_PIN(B22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) ASPEED_PINCTRL_PIN(B3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) ASPEED_PINCTRL_PIN(B4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) ASPEED_PINCTRL_PIN(B5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) ASPEED_PINCTRL_PIN(B6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) ASPEED_PINCTRL_PIN(B9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) ASPEED_PINCTRL_PIN(C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) ASPEED_PINCTRL_PIN(C11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) ASPEED_PINCTRL_PIN(C12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) ASPEED_PINCTRL_PIN(C13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ASPEED_PINCTRL_PIN(C14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) ASPEED_PINCTRL_PIN(C15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) ASPEED_PINCTRL_PIN(C16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) ASPEED_PINCTRL_PIN(C17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ASPEED_PINCTRL_PIN(C18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) ASPEED_PINCTRL_PIN(C19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) ASPEED_PINCTRL_PIN(C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) ASPEED_PINCTRL_PIN(C20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ASPEED_PINCTRL_PIN(C21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) ASPEED_PINCTRL_PIN(C22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) ASPEED_PINCTRL_PIN(C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) ASPEED_PINCTRL_PIN(C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) ASPEED_PINCTRL_PIN(C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) ASPEED_PINCTRL_PIN(D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) ASPEED_PINCTRL_PIN(D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ASPEED_PINCTRL_PIN(D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) ASPEED_PINCTRL_PIN(D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) ASPEED_PINCTRL_PIN(D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) ASPEED_PINCTRL_PIN(D16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ASPEED_PINCTRL_PIN(D17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) ASPEED_PINCTRL_PIN(D18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) ASPEED_PINCTRL_PIN(D19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) ASPEED_PINCTRL_PIN(D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) ASPEED_PINCTRL_PIN(D20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) ASPEED_PINCTRL_PIN(D21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) ASPEED_PINCTRL_PIN(D22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) ASPEED_PINCTRL_PIN(D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ASPEED_PINCTRL_PIN(D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) ASPEED_PINCTRL_PIN(D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) ASPEED_PINCTRL_PIN(D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) ASPEED_PINCTRL_PIN(D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) ASPEED_PINCTRL_PIN(D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) ASPEED_PINCTRL_PIN(E1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ASPEED_PINCTRL_PIN(E10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) ASPEED_PINCTRL_PIN(E12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) ASPEED_PINCTRL_PIN(E13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) ASPEED_PINCTRL_PIN(E14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) ASPEED_PINCTRL_PIN(E15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) ASPEED_PINCTRL_PIN(E16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) ASPEED_PINCTRL_PIN(E17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) ASPEED_PINCTRL_PIN(E18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) ASPEED_PINCTRL_PIN(E19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) ASPEED_PINCTRL_PIN(E2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) ASPEED_PINCTRL_PIN(E20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) ASPEED_PINCTRL_PIN(E21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) ASPEED_PINCTRL_PIN(E22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) ASPEED_PINCTRL_PIN(E3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) ASPEED_PINCTRL_PIN(E6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) ASPEED_PINCTRL_PIN(E7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) ASPEED_PINCTRL_PIN(E9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) ASPEED_PINCTRL_PIN(F1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) ASPEED_PINCTRL_PIN(F17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) ASPEED_PINCTRL_PIN(F18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) ASPEED_PINCTRL_PIN(F19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) ASPEED_PINCTRL_PIN(F2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) ASPEED_PINCTRL_PIN(F20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) ASPEED_PINCTRL_PIN(F21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) ASPEED_PINCTRL_PIN(F22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) ASPEED_PINCTRL_PIN(F3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) ASPEED_PINCTRL_PIN(F4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) ASPEED_PINCTRL_PIN(F5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ASPEED_PINCTRL_PIN(F9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) ASPEED_PINCTRL_PIN(G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) ASPEED_PINCTRL_PIN(G17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ASPEED_PINCTRL_PIN(G18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) ASPEED_PINCTRL_PIN(G2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) ASPEED_PINCTRL_PIN(G20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) ASPEED_PINCTRL_PIN(G21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) ASPEED_PINCTRL_PIN(G22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) ASPEED_PINCTRL_PIN(G3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) ASPEED_PINCTRL_PIN(G4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) ASPEED_PINCTRL_PIN(G5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) ASPEED_PINCTRL_PIN(H18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) ASPEED_PINCTRL_PIN(H19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) ASPEED_PINCTRL_PIN(H20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) ASPEED_PINCTRL_PIN(H21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) ASPEED_PINCTRL_PIN(H22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) ASPEED_PINCTRL_PIN(H3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) ASPEED_PINCTRL_PIN(H4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) ASPEED_PINCTRL_PIN(H5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) ASPEED_PINCTRL_PIN(J18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) ASPEED_PINCTRL_PIN(J19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) ASPEED_PINCTRL_PIN(J20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) ASPEED_PINCTRL_PIN(K18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) ASPEED_PINCTRL_PIN(K19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) ASPEED_PINCTRL_PIN(L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) ASPEED_PINCTRL_PIN(L18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) ASPEED_PINCTRL_PIN(L19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) ASPEED_PINCTRL_PIN(L2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) ASPEED_PINCTRL_PIN(L3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ASPEED_PINCTRL_PIN(L4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) ASPEED_PINCTRL_PIN(M18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) ASPEED_PINCTRL_PIN(M19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) ASPEED_PINCTRL_PIN(M20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) ASPEED_PINCTRL_PIN(N1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) ASPEED_PINCTRL_PIN(N18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) ASPEED_PINCTRL_PIN(N19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) ASPEED_PINCTRL_PIN(N2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) ASPEED_PINCTRL_PIN(N20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) ASPEED_PINCTRL_PIN(N21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) ASPEED_PINCTRL_PIN(N22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) ASPEED_PINCTRL_PIN(N3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) ASPEED_PINCTRL_PIN(N4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) ASPEED_PINCTRL_PIN(N5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ASPEED_PINCTRL_PIN(P1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) ASPEED_PINCTRL_PIN(P18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) ASPEED_PINCTRL_PIN(P19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) ASPEED_PINCTRL_PIN(P2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) ASPEED_PINCTRL_PIN(P20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) ASPEED_PINCTRL_PIN(P21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ASPEED_PINCTRL_PIN(P22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) ASPEED_PINCTRL_PIN(P3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) ASPEED_PINCTRL_PIN(P4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) ASPEED_PINCTRL_PIN(P5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) ASPEED_PINCTRL_PIN(R1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) ASPEED_PINCTRL_PIN(R18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) ASPEED_PINCTRL_PIN(R19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) ASPEED_PINCTRL_PIN(R2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) ASPEED_PINCTRL_PIN(R20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) ASPEED_PINCTRL_PIN(R21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) ASPEED_PINCTRL_PIN(R22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) ASPEED_PINCTRL_PIN(R3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) ASPEED_PINCTRL_PIN(R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) ASPEED_PINCTRL_PIN(R5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) ASPEED_PINCTRL_PIN(T1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) ASPEED_PINCTRL_PIN(T17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) ASPEED_PINCTRL_PIN(T19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) ASPEED_PINCTRL_PIN(T2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) ASPEED_PINCTRL_PIN(T20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) ASPEED_PINCTRL_PIN(T21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) ASPEED_PINCTRL_PIN(T22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) ASPEED_PINCTRL_PIN(T3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ASPEED_PINCTRL_PIN(T4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) ASPEED_PINCTRL_PIN(T5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) ASPEED_PINCTRL_PIN(U1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) ASPEED_PINCTRL_PIN(U19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ASPEED_PINCTRL_PIN(U2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) ASPEED_PINCTRL_PIN(U20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) ASPEED_PINCTRL_PIN(U21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) ASPEED_PINCTRL_PIN(U22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) ASPEED_PINCTRL_PIN(U3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) ASPEED_PINCTRL_PIN(U4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ASPEED_PINCTRL_PIN(U5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) ASPEED_PINCTRL_PIN(V1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) ASPEED_PINCTRL_PIN(V19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) ASPEED_PINCTRL_PIN(V2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) ASPEED_PINCTRL_PIN(V20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) ASPEED_PINCTRL_PIN(V21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) ASPEED_PINCTRL_PIN(V22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) ASPEED_PINCTRL_PIN(V3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) ASPEED_PINCTRL_PIN(V4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) ASPEED_PINCTRL_PIN(V5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) ASPEED_PINCTRL_PIN(V6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) ASPEED_PINCTRL_PIN(W1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) ASPEED_PINCTRL_PIN(W19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) ASPEED_PINCTRL_PIN(W2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) ASPEED_PINCTRL_PIN(W20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) ASPEED_PINCTRL_PIN(W21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) ASPEED_PINCTRL_PIN(W22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) ASPEED_PINCTRL_PIN(W3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) ASPEED_PINCTRL_PIN(W4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) ASPEED_PINCTRL_PIN(W5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) ASPEED_PINCTRL_PIN(W6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) ASPEED_PINCTRL_PIN(Y1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) ASPEED_PINCTRL_PIN(Y19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) ASPEED_PINCTRL_PIN(Y2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) ASPEED_PINCTRL_PIN(Y20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) ASPEED_PINCTRL_PIN(Y21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) ASPEED_PINCTRL_PIN(Y22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) ASPEED_PINCTRL_PIN(Y3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) ASPEED_PINCTRL_PIN(Y4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) ASPEED_PINCTRL_PIN(Y5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) ASPEED_PINCTRL_PIN(Y6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) static const struct aspeed_pin_group aspeed_g5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) ASPEED_PINCTRL_GROUP(ACPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) ASPEED_PINCTRL_GROUP(ADC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) ASPEED_PINCTRL_GROUP(ADC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) ASPEED_PINCTRL_GROUP(ADC10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) ASPEED_PINCTRL_GROUP(ADC11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) ASPEED_PINCTRL_GROUP(ADC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) ASPEED_PINCTRL_GROUP(ADC13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) ASPEED_PINCTRL_GROUP(ADC14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) ASPEED_PINCTRL_GROUP(ADC15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) ASPEED_PINCTRL_GROUP(ADC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) ASPEED_PINCTRL_GROUP(ADC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) ASPEED_PINCTRL_GROUP(ADC4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) ASPEED_PINCTRL_GROUP(ADC5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) ASPEED_PINCTRL_GROUP(ADC6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) ASPEED_PINCTRL_GROUP(ADC7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) ASPEED_PINCTRL_GROUP(ADC8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) ASPEED_PINCTRL_GROUP(ADC9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) ASPEED_PINCTRL_GROUP(BMCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) ASPEED_PINCTRL_GROUP(DDCCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) ASPEED_PINCTRL_GROUP(DDCDAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) ASPEED_PINCTRL_GROUP(ESPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) ASPEED_PINCTRL_GROUP(FWSPICS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) ASPEED_PINCTRL_GROUP(FWSPICS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) ASPEED_PINCTRL_GROUP(GPID0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) ASPEED_PINCTRL_GROUP(GPID2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) ASPEED_PINCTRL_GROUP(GPID4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) ASPEED_PINCTRL_GROUP(GPID6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) ASPEED_PINCTRL_GROUP(GPIE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) ASPEED_PINCTRL_GROUP(GPIE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) ASPEED_PINCTRL_GROUP(GPIE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) ASPEED_PINCTRL_GROUP(GPIE6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) ASPEED_PINCTRL_GROUP(I2C10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) ASPEED_PINCTRL_GROUP(I2C11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) ASPEED_PINCTRL_GROUP(I2C12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) ASPEED_PINCTRL_GROUP(I2C13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) ASPEED_PINCTRL_GROUP(I2C14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) ASPEED_PINCTRL_GROUP(I2C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) ASPEED_PINCTRL_GROUP(I2C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) ASPEED_PINCTRL_GROUP(I2C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) ASPEED_PINCTRL_GROUP(I2C6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) ASPEED_PINCTRL_GROUP(I2C7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) ASPEED_PINCTRL_GROUP(I2C8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ASPEED_PINCTRL_GROUP(I2C9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) ASPEED_PINCTRL_GROUP(LAD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) ASPEED_PINCTRL_GROUP(LAD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) ASPEED_PINCTRL_GROUP(LAD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) ASPEED_PINCTRL_GROUP(LAD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) ASPEED_PINCTRL_GROUP(LCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) ASPEED_PINCTRL_GROUP(LFRAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) ASPEED_PINCTRL_GROUP(LPCHC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) ASPEED_PINCTRL_GROUP(LPCPD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) ASPEED_PINCTRL_GROUP(LPCPLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) ASPEED_PINCTRL_GROUP(LPCPME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) ASPEED_PINCTRL_GROUP(LPCRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) ASPEED_PINCTRL_GROUP(LPCSMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) ASPEED_PINCTRL_GROUP(LSIRQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) ASPEED_PINCTRL_GROUP(MAC1LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) ASPEED_PINCTRL_GROUP(MAC2LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) ASPEED_PINCTRL_GROUP(MDIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) ASPEED_PINCTRL_GROUP(MDIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) ASPEED_PINCTRL_GROUP(NCTS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) ASPEED_PINCTRL_GROUP(NCTS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) ASPEED_PINCTRL_GROUP(NCTS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) ASPEED_PINCTRL_GROUP(NCTS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) ASPEED_PINCTRL_GROUP(NDCD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) ASPEED_PINCTRL_GROUP(NDCD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) ASPEED_PINCTRL_GROUP(NDCD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) ASPEED_PINCTRL_GROUP(NDCD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) ASPEED_PINCTRL_GROUP(NDSR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) ASPEED_PINCTRL_GROUP(NDSR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) ASPEED_PINCTRL_GROUP(NDSR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) ASPEED_PINCTRL_GROUP(NDSR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) ASPEED_PINCTRL_GROUP(NDTR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) ASPEED_PINCTRL_GROUP(NDTR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) ASPEED_PINCTRL_GROUP(NDTR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) ASPEED_PINCTRL_GROUP(NDTR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) ASPEED_PINCTRL_GROUP(NRI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) ASPEED_PINCTRL_GROUP(NRI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) ASPEED_PINCTRL_GROUP(NRI3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) ASPEED_PINCTRL_GROUP(NRI4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) ASPEED_PINCTRL_GROUP(NRTS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) ASPEED_PINCTRL_GROUP(NRTS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) ASPEED_PINCTRL_GROUP(NRTS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) ASPEED_PINCTRL_GROUP(NRTS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) ASPEED_PINCTRL_GROUP(OSCCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) ASPEED_PINCTRL_GROUP(PEWAKE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) ASPEED_PINCTRL_GROUP(PNOR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) ASPEED_PINCTRL_GROUP(PWM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) ASPEED_PINCTRL_GROUP(PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) ASPEED_PINCTRL_GROUP(PWM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) ASPEED_PINCTRL_GROUP(PWM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) ASPEED_PINCTRL_GROUP(PWM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) ASPEED_PINCTRL_GROUP(PWM5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) ASPEED_PINCTRL_GROUP(PWM6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) ASPEED_PINCTRL_GROUP(PWM7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) ASPEED_PINCTRL_GROUP(RGMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) ASPEED_PINCTRL_GROUP(RGMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) ASPEED_PINCTRL_GROUP(RMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) ASPEED_PINCTRL_GROUP(RMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) ASPEED_PINCTRL_GROUP(RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) ASPEED_PINCTRL_GROUP(RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) ASPEED_PINCTRL_GROUP(RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) ASPEED_PINCTRL_GROUP(RXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) ASPEED_PINCTRL_GROUP(SALT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) ASPEED_PINCTRL_GROUP(SALT10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) ASPEED_PINCTRL_GROUP(SALT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) ASPEED_PINCTRL_GROUP(SALT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) ASPEED_PINCTRL_GROUP(SALT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) ASPEED_PINCTRL_GROUP(SALT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) ASPEED_PINCTRL_GROUP(SALT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) ASPEED_PINCTRL_GROUP(SALT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) ASPEED_PINCTRL_GROUP(SALT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) ASPEED_PINCTRL_GROUP(SALT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) ASPEED_PINCTRL_GROUP(SALT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) ASPEED_PINCTRL_GROUP(SALT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) ASPEED_PINCTRL_GROUP(SALT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) ASPEED_PINCTRL_GROUP(SALT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) ASPEED_PINCTRL_GROUP(SCL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) ASPEED_PINCTRL_GROUP(SCL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) ASPEED_PINCTRL_GROUP(SD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) ASPEED_PINCTRL_GROUP(SD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) ASPEED_PINCTRL_GROUP(SDA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) ASPEED_PINCTRL_GROUP(SDA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) ASPEED_PINCTRL_GROUP(SGPM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) ASPEED_PINCTRL_GROUP(SGPS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) ASPEED_PINCTRL_GROUP(SGPS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) ASPEED_PINCTRL_GROUP(SIOONCTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) ASPEED_PINCTRL_GROUP(SIOPBI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) ASPEED_PINCTRL_GROUP(SIOPBO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) ASPEED_PINCTRL_GROUP(SIOPWREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) ASPEED_PINCTRL_GROUP(SIOPWRGD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) ASPEED_PINCTRL_GROUP(SIOS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) ASPEED_PINCTRL_GROUP(SIOS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) ASPEED_PINCTRL_GROUP(SIOSCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) ASPEED_PINCTRL_GROUP(SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) ASPEED_PINCTRL_GROUP(SPI1CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) ASPEED_PINCTRL_GROUP(SPI1DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) ASPEED_PINCTRL_GROUP(SPI2CK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) ASPEED_PINCTRL_GROUP(SPI2CS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) ASPEED_PINCTRL_GROUP(SPI2CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) ASPEED_PINCTRL_GROUP(SPI2MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) ASPEED_PINCTRL_GROUP(SPI2MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) ASPEED_PINCTRL_GROUP(TIMER3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) ASPEED_PINCTRL_GROUP(TIMER4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) ASPEED_PINCTRL_GROUP(TIMER5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) ASPEED_PINCTRL_GROUP(TIMER6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) ASPEED_PINCTRL_GROUP(TIMER7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) ASPEED_PINCTRL_GROUP(TIMER8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) ASPEED_PINCTRL_GROUP(TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) ASPEED_PINCTRL_GROUP(TXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) ASPEED_PINCTRL_GROUP(TXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) ASPEED_PINCTRL_GROUP(TXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) ASPEED_PINCTRL_GROUP(UART6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) ASPEED_PINCTRL_GROUP(USB11BHID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) ASPEED_PINCTRL_GROUP(USB2AD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) ASPEED_PINCTRL_GROUP(USB2AH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) ASPEED_PINCTRL_GROUP(USB2BD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) ASPEED_PINCTRL_GROUP(USB2BH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) ASPEED_PINCTRL_GROUP(USBCKI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) ASPEED_PINCTRL_GROUP(VGABIOSROM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) ASPEED_PINCTRL_GROUP(VGAHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) ASPEED_PINCTRL_GROUP(VGAVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) ASPEED_PINCTRL_GROUP(VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) ASPEED_PINCTRL_GROUP(VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) ASPEED_PINCTRL_GROUP(WDTRST1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) ASPEED_PINCTRL_GROUP(WDTRST2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) static const struct aspeed_pin_function aspeed_g5_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) ASPEED_PINCTRL_FUNC(ACPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) ASPEED_PINCTRL_FUNC(ADC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) ASPEED_PINCTRL_FUNC(ADC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) ASPEED_PINCTRL_FUNC(ADC10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) ASPEED_PINCTRL_FUNC(ADC11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) ASPEED_PINCTRL_FUNC(ADC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) ASPEED_PINCTRL_FUNC(ADC13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) ASPEED_PINCTRL_FUNC(ADC14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) ASPEED_PINCTRL_FUNC(ADC15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) ASPEED_PINCTRL_FUNC(ADC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) ASPEED_PINCTRL_FUNC(ADC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) ASPEED_PINCTRL_FUNC(ADC4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) ASPEED_PINCTRL_FUNC(ADC5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) ASPEED_PINCTRL_FUNC(ADC6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) ASPEED_PINCTRL_FUNC(ADC7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) ASPEED_PINCTRL_FUNC(ADC8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) ASPEED_PINCTRL_FUNC(ADC9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) ASPEED_PINCTRL_FUNC(BMCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) ASPEED_PINCTRL_FUNC(DDCCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) ASPEED_PINCTRL_FUNC(DDCDAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) ASPEED_PINCTRL_FUNC(ESPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) ASPEED_PINCTRL_FUNC(FWSPICS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) ASPEED_PINCTRL_FUNC(FWSPICS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) ASPEED_PINCTRL_FUNC(GPID0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) ASPEED_PINCTRL_FUNC(GPID2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) ASPEED_PINCTRL_FUNC(GPID4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) ASPEED_PINCTRL_FUNC(GPID6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) ASPEED_PINCTRL_FUNC(GPIE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) ASPEED_PINCTRL_FUNC(GPIE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) ASPEED_PINCTRL_FUNC(GPIE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) ASPEED_PINCTRL_FUNC(GPIE6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) ASPEED_PINCTRL_FUNC(I2C10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) ASPEED_PINCTRL_FUNC(I2C11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) ASPEED_PINCTRL_FUNC(I2C12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) ASPEED_PINCTRL_FUNC(I2C13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) ASPEED_PINCTRL_FUNC(I2C14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) ASPEED_PINCTRL_FUNC(I2C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) ASPEED_PINCTRL_FUNC(I2C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) ASPEED_PINCTRL_FUNC(I2C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) ASPEED_PINCTRL_FUNC(I2C6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) ASPEED_PINCTRL_FUNC(I2C7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) ASPEED_PINCTRL_FUNC(I2C8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) ASPEED_PINCTRL_FUNC(I2C9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) ASPEED_PINCTRL_FUNC(LAD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) ASPEED_PINCTRL_FUNC(LAD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) ASPEED_PINCTRL_FUNC(LAD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) ASPEED_PINCTRL_FUNC(LAD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) ASPEED_PINCTRL_FUNC(LCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) ASPEED_PINCTRL_FUNC(LFRAME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) ASPEED_PINCTRL_FUNC(LPCHC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) ASPEED_PINCTRL_FUNC(LPCPD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) ASPEED_PINCTRL_FUNC(LPCPLUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) ASPEED_PINCTRL_FUNC(LPCPME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) ASPEED_PINCTRL_FUNC(LPCRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) ASPEED_PINCTRL_FUNC(LPCSMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) ASPEED_PINCTRL_FUNC(LSIRQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) ASPEED_PINCTRL_FUNC(MAC1LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) ASPEED_PINCTRL_FUNC(MAC2LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) ASPEED_PINCTRL_FUNC(MDIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) ASPEED_PINCTRL_FUNC(MDIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) ASPEED_PINCTRL_FUNC(NCTS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) ASPEED_PINCTRL_FUNC(NCTS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) ASPEED_PINCTRL_FUNC(NCTS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) ASPEED_PINCTRL_FUNC(NCTS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) ASPEED_PINCTRL_FUNC(NDCD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) ASPEED_PINCTRL_FUNC(NDCD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) ASPEED_PINCTRL_FUNC(NDCD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) ASPEED_PINCTRL_FUNC(NDCD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) ASPEED_PINCTRL_FUNC(NDSR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) ASPEED_PINCTRL_FUNC(NDSR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) ASPEED_PINCTRL_FUNC(NDSR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) ASPEED_PINCTRL_FUNC(NDSR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) ASPEED_PINCTRL_FUNC(NDTR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) ASPEED_PINCTRL_FUNC(NDTR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) ASPEED_PINCTRL_FUNC(NDTR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) ASPEED_PINCTRL_FUNC(NDTR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) ASPEED_PINCTRL_FUNC(NRI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) ASPEED_PINCTRL_FUNC(NRI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) ASPEED_PINCTRL_FUNC(NRI3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) ASPEED_PINCTRL_FUNC(NRI4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) ASPEED_PINCTRL_FUNC(NRTS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) ASPEED_PINCTRL_FUNC(NRTS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) ASPEED_PINCTRL_FUNC(NRTS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) ASPEED_PINCTRL_FUNC(NRTS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) ASPEED_PINCTRL_FUNC(OSCCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) ASPEED_PINCTRL_FUNC(PEWAKE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) ASPEED_PINCTRL_FUNC(PNOR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) ASPEED_PINCTRL_FUNC(PWM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) ASPEED_PINCTRL_FUNC(PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) ASPEED_PINCTRL_FUNC(PWM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) ASPEED_PINCTRL_FUNC(PWM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) ASPEED_PINCTRL_FUNC(PWM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) ASPEED_PINCTRL_FUNC(PWM5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) ASPEED_PINCTRL_FUNC(PWM6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) ASPEED_PINCTRL_FUNC(PWM7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) ASPEED_PINCTRL_FUNC(RGMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) ASPEED_PINCTRL_FUNC(RGMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) ASPEED_PINCTRL_FUNC(RMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) ASPEED_PINCTRL_FUNC(RMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) ASPEED_PINCTRL_FUNC(RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) ASPEED_PINCTRL_FUNC(RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) ASPEED_PINCTRL_FUNC(RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) ASPEED_PINCTRL_FUNC(RXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) ASPEED_PINCTRL_FUNC(SALT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) ASPEED_PINCTRL_FUNC(SALT10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) ASPEED_PINCTRL_FUNC(SALT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) ASPEED_PINCTRL_FUNC(SALT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) ASPEED_PINCTRL_FUNC(SALT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) ASPEED_PINCTRL_FUNC(SALT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) ASPEED_PINCTRL_FUNC(SALT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) ASPEED_PINCTRL_FUNC(SALT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) ASPEED_PINCTRL_FUNC(SALT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) ASPEED_PINCTRL_FUNC(SALT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) ASPEED_PINCTRL_FUNC(SALT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) ASPEED_PINCTRL_FUNC(SALT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) ASPEED_PINCTRL_FUNC(SALT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) ASPEED_PINCTRL_FUNC(SALT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) ASPEED_PINCTRL_FUNC(SCL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) ASPEED_PINCTRL_FUNC(SCL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) ASPEED_PINCTRL_FUNC(SD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) ASPEED_PINCTRL_FUNC(SD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) ASPEED_PINCTRL_FUNC(SDA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) ASPEED_PINCTRL_FUNC(SDA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) ASPEED_PINCTRL_FUNC(SGPM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) ASPEED_PINCTRL_FUNC(SGPS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) ASPEED_PINCTRL_FUNC(SGPS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) ASPEED_PINCTRL_FUNC(SIOONCTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) ASPEED_PINCTRL_FUNC(SIOPBI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) ASPEED_PINCTRL_FUNC(SIOPBO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) ASPEED_PINCTRL_FUNC(SIOPWREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) ASPEED_PINCTRL_FUNC(SIOPWRGD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) ASPEED_PINCTRL_FUNC(SIOS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) ASPEED_PINCTRL_FUNC(SIOS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) ASPEED_PINCTRL_FUNC(SIOSCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) ASPEED_PINCTRL_FUNC(SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) ASPEED_PINCTRL_FUNC(SPI1CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) ASPEED_PINCTRL_FUNC(SPI1DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) ASPEED_PINCTRL_FUNC(SPI2CK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) ASPEED_PINCTRL_FUNC(SPI2CS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) ASPEED_PINCTRL_FUNC(SPI2CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) ASPEED_PINCTRL_FUNC(SPI2MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) ASPEED_PINCTRL_FUNC(SPI2MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) ASPEED_PINCTRL_FUNC(TIMER3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) ASPEED_PINCTRL_FUNC(TIMER4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) ASPEED_PINCTRL_FUNC(TIMER5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) ASPEED_PINCTRL_FUNC(TIMER6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) ASPEED_PINCTRL_FUNC(TIMER7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) ASPEED_PINCTRL_FUNC(TIMER8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) ASPEED_PINCTRL_FUNC(TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) ASPEED_PINCTRL_FUNC(TXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) ASPEED_PINCTRL_FUNC(TXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) ASPEED_PINCTRL_FUNC(TXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) ASPEED_PINCTRL_FUNC(UART6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) ASPEED_PINCTRL_FUNC(USB11BHID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) ASPEED_PINCTRL_FUNC(USB2AD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) ASPEED_PINCTRL_FUNC(USB2AH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) ASPEED_PINCTRL_FUNC(USB2BD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) ASPEED_PINCTRL_FUNC(USB2BH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) ASPEED_PINCTRL_FUNC(USBCKI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) ASPEED_PINCTRL_FUNC(VGABIOSROM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) ASPEED_PINCTRL_FUNC(VGAHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) ASPEED_PINCTRL_FUNC(VGAVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) ASPEED_PINCTRL_FUNC(VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) ASPEED_PINCTRL_FUNC(VPO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) ASPEED_PINCTRL_FUNC(WDTRST1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) ASPEED_PINCTRL_FUNC(WDTRST2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) static struct aspeed_pin_config aspeed_g5_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) /* GPIOA, GPIOQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B14, B13, SCU8C, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B14, B13, SCU8C, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A11, N20, SCU8C, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A11, N20, SCU8C, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) /* GPIOB, GPIOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, K19, H20, SCU8C, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, K19, H20, SCU8C, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AA19, E10, SCU8C, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AA19, E10, SCU8C, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) /* GPIOC, GPIOS*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C12, B11, SCU8C, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C12, B11, SCU8C, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, AA20, SCU8C, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, AA20, SCU8C, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) /* GPIOD, GPIOY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F19, C21, SCU8C, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F19, C21, SCU8C, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R22, P20, SCU8C, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R22, P20, SCU8C, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) /* GPIOE, GPIOZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B20, B19, SCU8C, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B20, B19, SCU8C, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y20, W21, SCU8C, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y20, W21, SCU8C, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) /* GPIOF, GPIOAA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J19, H18, SCU8C, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J19, H18, SCU8C, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y21, P19, SCU8C, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y21, P19, SCU8C, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) /* GPIOG, GPIOAB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A19, E14, SCU8C, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A19, E14, SCU8C, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N19, R20, SCU8C, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N19, R20, SCU8C, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) /* GPIOH, GPIOAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, D18, SCU8C, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, D18, SCU8C, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G21, G22, SCU8C, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G21, G22, SCU8C, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) /* GPIOs [I, P] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C18, A15, SCU8C, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R2, T3, SCU8C, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R2, T3, SCU8C, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, R1, SCU8C, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, R1, SCU8C, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, T2, W1, SCU8C, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, T2, W1, SCU8C, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, T5, SCU8C, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, T5, SCU8C, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V2, T4, SCU8C, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V2, T4, SCU8C, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U5, W4, SCU8C, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U5, W4, SCU8C, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V4, V6, SCU8C, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V4, V6, SCU8C, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* GPIOs T[0-5] (RGMII1 Tx pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B5, B5, SCU90, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, E9, A5, SCU90, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B5, D7, SCU90, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B5, D7, SCU90, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B2, B2, SCU90, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B1, B3, SCU90, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D4, SCU90, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D4, SCU90, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B4, C4, SCU90, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B4, C4, SCU90, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) /* GPIOs V[2-7] (RGMII2 Rx pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C2, E6, SCU90, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C2, E6, SCU90, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) /* ADC pull-downs (SCUA8[19:4]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F4, F4, SCUA8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F4, F4, SCUA8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F5, F5, SCUA8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F5, F5, SCUA8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E2, E2, SCUA8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E2, E2, SCUA8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E1, E1, SCUA8, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E1, E1, SCUA8, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F3, F3, SCUA8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F3, F3, SCUA8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E3, E3, SCUA8, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E3, E3, SCUA8, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G5, G5, SCUA8, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G5, G5, SCUA8, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G4, G4, SCUA8, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G4, G4, SCUA8, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F2, F2, SCUA8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F2, F2, SCUA8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G3, G3, SCUA8, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G3, G3, SCUA8, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G2, G2, SCUA8, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G2, G2, SCUA8, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F1, F1, SCUA8, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F1, F1, SCUA8, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H5, H5, SCUA8, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H5, H5, SCUA8, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G1, G1, SCUA8, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G1, G1, SCUA8, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H3, H3, SCUA8, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H3, H3, SCUA8, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H4, H4, SCUA8, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H4, H4, SCUA8, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) * Debounce settings for GPIOs D and E passthrough mode are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) * SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) * banks D and E is handled by the GPIO driver - GPIO passthrough is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) * treated like any other non-GPIO mux function. There is a catch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) * however, in that the debounce period is configured in the GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) * controller. Due to this tangle between GPIO and pinctrl we don't yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) * fully support pass-through debounce.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F19, E21, SCUA8, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F20, D20, SCUA8, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D21, E20, SCUA8, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, G18, C21, SCUA8, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B20, C20, SCUA8, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F18, F17, SCUA8, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E18, D19, SCUA8, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A20, B19, SCUA8, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) int ip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (ip == ASPEED_IP_SCU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) WARN(!ctx->maps[ip], "Missing SCU syscon!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) return ctx->maps[ip];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) if (ip >= ASPEED_NR_PINMUX_IPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) if (likely(ctx->maps[ip]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) return ctx->maps[ip];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) if (ip == ASPEED_IP_GFX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) node = of_parse_phandle(ctx->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) "aspeed,external-nodes", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) map = syscon_node_to_regmap(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) if (IS_ERR(map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) return map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) ctx->maps[ASPEED_IP_GFX] = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) dev_dbg(ctx->dev, "Acquired GFX regmap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) return map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) if (ip == ASPEED_IP_LPC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) node = of_parse_phandle(ctx->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) "aspeed,external-nodes", 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) if (node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) map = syscon_node_to_regmap(node->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) if (IS_ERR(map))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) return map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) ctx->maps[ASPEED_IP_LPC] = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) dev_dbg(ctx->dev, "Acquired LPC regmap");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) return map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) static int aspeed_g5_sig_expr_eval(struct aspeed_pinmux_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) const struct aspeed_sig_expr *expr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) bool enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) for (i = 0; i < expr->ndescs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) const struct aspeed_sig_desc *desc = &expr->descs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) map = aspeed_g5_acquire_regmap(ctx, desc->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) dev_err(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) "Failed to acquire regmap for IP block %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) desc->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) ret = aspeed_sig_desc_eval(desc, enabled, ctx->maps[desc->ip]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) if (ret <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) * Configure a pin's signal by applying an expression's descriptor state for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) * all descriptors in the expression.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) * @ctx: The pinmux context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) * @expr: The expression associated with the function whose signal is to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) * configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) * @enable: true to enable an function's signal through a pin's signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) * expression, false to disable the function's signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) * Return: 0 if the expression is configured as requested and a negative error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) * code otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) const struct aspeed_sig_expr *expr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) for (i = 0; i < expr->ndescs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) const struct aspeed_sig_desc *desc = &expr->descs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) u32 pattern = enable ? desc->enable : desc->disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) u32 val = (pattern << __ffs(desc->mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) map = aspeed_g5_acquire_regmap(ctx, desc->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) dev_err(ctx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) "Failed to acquire regmap for IP block %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) desc->ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) * Strap registers are configured in hardware or by early-boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) * firmware. Treat them as read-only despite that we can write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) * them. This may mean that certain functions cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) * deconfigured and is the reason we re-evaluate after writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) * all descriptor bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) * Port D and port E GPIO loopback modes are the only exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) * as those are commonly used with front-panel buttons to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) * normal operation of the host when the BMC is powered off or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) * fails to boot. Once the BMC has booted, the loopback mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) * must be disabled for the BMC to control host power-on and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) * reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) !(desc->mask & (BIT(21) | BIT(22))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) /* On AST2500, Set bits in SCU70 are cleared from SCU7C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) u32 value = ~val & desc->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) ret = regmap_write(ctx->maps[desc->ip],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) HW_REVISION_ID, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) desc->mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) ret = aspeed_sig_expr_eval(ctx, expr, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) static const struct aspeed_pinmux_ops aspeed_g5_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) .eval = aspeed_g5_sig_expr_eval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) .set = aspeed_g5_sig_expr_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) .pins = aspeed_g5_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .npins = ARRAY_SIZE(aspeed_g5_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) .pinmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) .ops = &aspeed_g5_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) .groups = aspeed_g5_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) .ngroups = ARRAY_SIZE(aspeed_g5_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .functions = aspeed_g5_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) .nfunctions = ARRAY_SIZE(aspeed_g5_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) .configs = aspeed_g5_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) .nconfigs = ARRAY_SIZE(aspeed_g5_configs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) .confmaps = aspeed_g5_pin_config_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) .nconfmaps = ARRAY_SIZE(aspeed_g5_pin_config_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) static const struct pinmux_ops aspeed_g5_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .get_functions_count = aspeed_pinmux_get_fn_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .get_function_name = aspeed_pinmux_get_fn_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .get_function_groups = aspeed_pinmux_get_fn_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .set_mux = aspeed_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .gpio_request_enable = aspeed_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) .strict = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) static const struct pinctrl_ops aspeed_g5_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) .get_groups_count = aspeed_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .get_group_name = aspeed_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .get_group_pins = aspeed_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) .pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) static const struct pinconf_ops aspeed_g5_conf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .pin_config_get = aspeed_pin_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) .pin_config_set = aspeed_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) .pin_config_group_get = aspeed_pin_config_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) .pin_config_group_set = aspeed_pin_config_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) .name = "aspeed-g5-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .pins = aspeed_g5_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) .npins = ARRAY_SIZE(aspeed_g5_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) .pctlops = &aspeed_g5_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) .pmxops = &aspeed_g5_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .confops = &aspeed_g5_conf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) aspeed_g5_pins[i].number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) aspeed_g5_pinctrl_data.pinmux.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) &aspeed_g5_pinctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) static const struct of_device_id aspeed_g5_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) { .compatible = "aspeed,ast2500-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) * The aspeed,g5-pinctrl compatible has been removed the from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) * bindings, but keep the match in case of old devicetrees.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) { .compatible = "aspeed,g5-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) static struct platform_driver aspeed_g5_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .probe = aspeed_g5_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) .name = "aspeed-g5-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .of_match_table = aspeed_g5_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) static int aspeed_g5_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) return platform_driver_register(&aspeed_g5_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) arch_initcall(aspeed_g5_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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