^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "pinmux-aspeed.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pinctrl-aspeed.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Wrap some of the common macros for clarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SIG_EXPR_DECL_SINGLE(sig, func, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SIG_EXPR_DECL(sig, func, func, __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * references registers by the device/offset mnemonic. The register macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * below are named the same way to ease transcription and verification (as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * reference registers beyond those dedicated to pinmux, such as the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * reset control and MAC clock configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCU2C 0x2C /* Misc. Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCU3C 0x3C /* System Reset Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCU48 0x48 /* MAC Interface Clock Delay Setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HW_REVISION_ID 0x7C /* Silicon revision ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCU80 0x80 /* Multi-function Pin Control #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCU84 0x84 /* Multi-function Pin Control #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCU88 0x88 /* Multi-function Pin Control #3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCU8C 0x8C /* Multi-function Pin Control #4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCU90 0x90 /* Multi-function Pin Control #5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SCU94 0x94 /* Multi-function Pin Control #6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SCUA0 0xA0 /* Multi-function Pin Control #7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SCUA4 0xA4 /* Multi-function Pin Control #8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SCUA8 0xA8 /* Multi-function Pin Control #9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SCUAC 0xAC /* Multi-function Pin Control #10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HW_STRAP2 0xD0 /* Strapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Uses undefined macros for symbol naming and references, eg GPIOA0, MAC1LINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * TIMER3 etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Pins are defined in GPIO bank order:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * GPIOA0: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * GPIOA7: 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * GPIOB0: 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * GPIOZ7: 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * GPIOAA0: 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * GPIOAB3: 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Not all pins have their signals defined (yet).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define D6 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define B5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) SSSF_PIN_DECL(B5, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define A4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define E6 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SSSF_PIN_DECL(E6, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define I2C9_DESC SIG_DESC_SET(SCU90, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define C5 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SIG_EXPR_LIST_DECL_SINGLE(C5, SCL9, I2C9, I2C9_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SIG_EXPR_LIST_DECL_SINGLE(C5, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PIN_DECL_2(C5, GPIOA4, SCL9, TIMER5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FUNC_GROUP_DECL(TIMER5, C5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define B4 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) SIG_EXPR_LIST_DECL_SINGLE(B4, SDA9, I2C9, I2C9_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) SIG_EXPR_LIST_DECL_SINGLE(B4, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PIN_DECL_2(B4, GPIOA5, SDA9, TIMER6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FUNC_GROUP_DECL(TIMER6, B4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FUNC_GROUP_DECL(I2C9, C5, B4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MDIO2_DESC SIG_DESC_SET(SCU90, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define A3 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SIG_EXPR_LIST_DECL_SINGLE(A3, MDC2, MDIO2, MDIO2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SIG_EXPR_LIST_DECL_SINGLE(A3, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PIN_DECL_2(A3, GPIOA6, MDC2, TIMER7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) FUNC_GROUP_DECL(TIMER7, A3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define D5 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SIG_EXPR_LIST_DECL_SINGLE(D5, MDIO2, MDIO2, MDIO2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SIG_EXPR_LIST_DECL_SINGLE(D5, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PIN_DECL_2(D5, GPIOA7, MDIO2, TIMER8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) FUNC_GROUP_DECL(TIMER8, D5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FUNC_GROUP_DECL(MDIO2, A3, D5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define J21 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SSSF_PIN_DECL(J21, GPIOB0, SALT1, SIG_DESC_SET(SCU80, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define J20 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SSSF_PIN_DECL(J20, GPIOB1, SALT2, SIG_DESC_SET(SCU80, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define H18 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SSSF_PIN_DECL(H18, GPIOB2, SALT3, SIG_DESC_SET(SCU80, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define F18 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SSSF_PIN_DECL(F18, GPIOB3, SALT4, SIG_DESC_SET(SCU80, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define E19 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) SIG_EXPR_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) SIG_EXPR_DECL_SINGLE(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SIG_EXPR_LIST_DECL_DUAL(E19, LPCRST, LPCRST, LPCRSTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PIN_DECL_1(E19, GPIOB4, LPCRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FUNC_GROUP_DECL(LPCRST, E19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define H19 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define H19_DESC SIG_DESC_SET(SCU80, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SIG_EXPR_LIST_DECL_SINGLE(H19, LPCPD, LPCPD, H19_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SIG_EXPR_LIST_DECL_SINGLE(H19, LPCSMI, LPCSMI, H19_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PIN_DECL_2(H19, GPIOB5, LPCPD, LPCSMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FUNC_GROUP_DECL(LPCPD, H19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) FUNC_GROUP_DECL(LPCSMI, H19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define H20 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define E18 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SIG_EXPR_LIST_DECL_SINGLE(E18, EXTRST, EXTRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) SIG_DESC_SET(SCU80, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SIG_DESC_BIT(SCU90, 31, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) SIG_DESC_SET(SCU3C, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SIG_EXPR_LIST_DECL_SINGLE(E18, SPICS1, SPICS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) SIG_DESC_SET(SCU80, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SIG_DESC_SET(SCU90, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PIN_DECL_2(E18, GPIOB7, EXTRST, SPICS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) FUNC_GROUP_DECL(EXTRST, E18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) FUNC_GROUP_DECL(SPICS1, E18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SD1_DESC SIG_DESC_SET(SCU90, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define I2C10_DESC SIG_DESC_SET(SCU90, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define C4 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SIG_EXPR_LIST_DECL_SINGLE(C4, SD1CLK, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SIG_EXPR_LIST_DECL_SINGLE(C4, SCL10, I2C10, I2C10_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PIN_DECL_2(C4, GPIOC0, SD1CLK, SCL10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define B3 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SIG_EXPR_LIST_DECL_SINGLE(B3, SD1CMD, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SIG_EXPR_LIST_DECL_SINGLE(B3, SDA10, I2C10, I2C10_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PIN_DECL_2(B3, GPIOC1, SD1CMD, SDA10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) FUNC_GROUP_DECL(I2C10, C4, B3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define I2C11_DESC SIG_DESC_SET(SCU90, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define A2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) SIG_EXPR_LIST_DECL_SINGLE(A2, SD1DAT0, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SIG_EXPR_LIST_DECL_SINGLE(A2, SCL11, I2C11, I2C11_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PIN_DECL_2(A2, GPIOC2, SD1DAT0, SCL11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define E5 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SIG_EXPR_LIST_DECL_SINGLE(E5, SD1DAT1, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SIG_EXPR_LIST_DECL_SINGLE(E5, SDA11, I2C11, I2C11_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PIN_DECL_2(E5, GPIOC3, SD1DAT1, SDA11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) FUNC_GROUP_DECL(I2C11, A2, E5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define I2C12_DESC SIG_DESC_SET(SCU90, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define D4 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) SIG_EXPR_LIST_DECL_SINGLE(D4, SD1DAT2, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SIG_EXPR_LIST_DECL_SINGLE(D4, SCL12, I2C12, I2C12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PIN_DECL_2(D4, GPIOC4, SD1DAT2, SCL12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define C3 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) SIG_EXPR_LIST_DECL_SINGLE(C3, SD1DAT3, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) SIG_EXPR_LIST_DECL_SINGLE(C3, SDA12, I2C12, I2C12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PIN_DECL_2(C3, GPIOC5, SD1DAT3, SDA12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) FUNC_GROUP_DECL(I2C12, D4, C3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define I2C13_DESC SIG_DESC_SET(SCU90, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define B2 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) SIG_EXPR_LIST_DECL_SINGLE(B2, SD1CD, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SIG_EXPR_LIST_DECL_SINGLE(B2, SCL13, I2C13, I2C13_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PIN_DECL_2(B2, GPIOC6, SD1CD, SCL13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define A1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SIG_EXPR_LIST_DECL_SINGLE(A1, SD1WP, SD1, SD1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SIG_EXPR_LIST_DECL_SINGLE(A1, SDA13, I2C13, I2C13_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PIN_DECL_2(A1, GPIOC7, SD1WP, SDA13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) FUNC_GROUP_DECL(I2C13, B2, A1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SD2_DESC SIG_DESC_SET(SCU90, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GPID0_DESC SIG_DESC_SET(SCU8C, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define A18 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SIG_EXPR_LIST_DECL_SINGLE(A18, SD2CLK, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SIG_EXPR_LIST_DECL_DUAL(A18, GPID0IN, GPID0, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PIN_DECL_2(A18, GPIOD0, SD2CLK, GPID0IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define D16 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) SIG_EXPR_LIST_DECL_SINGLE(D16, SD2CMD, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) SIG_EXPR_LIST_DECL_DUAL(D16, GPID0OUT, GPID0, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PIN_DECL_2(D16, GPIOD1, SD2CMD, GPID0OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) FUNC_GROUP_DECL(GPID0, A18, D16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define B17 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) SIG_EXPR_LIST_DECL_SINGLE(B17, SD2DAT0, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SIG_EXPR_LIST_DECL_DUAL(B17, GPID2IN, GPID2, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PIN_DECL_2(B17, GPIOD2, SD2DAT0, GPID2IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define A17 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SIG_EXPR_LIST_DECL_SINGLE(A17, SD2DAT1, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SIG_EXPR_LIST_DECL_DUAL(A17, GPID2OUT, GPID2, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PIN_DECL_2(A17, GPIOD3, SD2DAT1, GPID2OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) FUNC_GROUP_DECL(GPID2, B17, A17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define C16 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) SIG_EXPR_LIST_DECL_SINGLE(C16, SD2DAT2, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) SIG_EXPR_LIST_DECL_DUAL(C16, GPID4IN, GPID4, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PIN_DECL_2(C16, GPIOD4, SD2DAT2, GPID4IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define B16 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) SIG_EXPR_LIST_DECL_SINGLE(B16, SD2DAT3, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) SIG_EXPR_LIST_DECL_DUAL(B16, GPID4OUT, GPID4, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PIN_DECL_2(B16, GPIOD5, SD2DAT3, GPID4OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) FUNC_GROUP_DECL(GPID4, C16, B16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define A16 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) SIG_EXPR_LIST_DECL_SINGLE(A16, SD2CD, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) SIG_EXPR_LIST_DECL_DUAL(A16, GPID6IN, GPID6, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PIN_DECL_2(A16, GPIOD6, SD2CD, GPID6IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define E15 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) SIG_EXPR_LIST_DECL_SINGLE(E15, SD2WP, SD2, SD2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) SIG_EXPR_LIST_DECL_DUAL(E15, GPID6OUT, GPID6, GPID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PIN_DECL_2(E15, GPIOD7, SD2WP, GPID6OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) FUNC_GROUP_DECL(GPID6, A16, E15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) FUNC_GROUP_DECL(SD2, A18, D16, B17, A17, C16, B16, A16, E15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) FUNC_GROUP_DECL(GPID, A18, D16, B17, A17, C16, B16, A16, E15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define GPIE4_DESC SIG_DESC_SET(SCU8C, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define D15 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) SIG_EXPR_LIST_DECL_SINGLE(D15, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SIG_EXPR_LIST_DECL_DUAL(D15, GPIE0IN, GPIE0, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PIN_DECL_2(D15, GPIOE0, NCTS3, GPIE0IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) FUNC_GROUP_DECL(NCTS3, D15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define C15 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) SIG_EXPR_LIST_DECL_SINGLE(C15, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SIG_EXPR_LIST_DECL_DUAL(C15, GPIE0OUT, GPIE0, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PIN_DECL_2(C15, GPIOE1, NDCD3, GPIE0OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) FUNC_GROUP_DECL(NDCD3, C15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) FUNC_GROUP_DECL(GPIE0, D15, C15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define B15 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SIG_EXPR_LIST_DECL_SINGLE(B15, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) SIG_EXPR_LIST_DECL_DUAL(B15, GPIE2IN, GPIE2, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PIN_DECL_2(B15, GPIOE2, NDSR3, GPIE2IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) FUNC_GROUP_DECL(NDSR3, B15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define A15 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) SIG_EXPR_LIST_DECL_SINGLE(A15, NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) SIG_EXPR_LIST_DECL_DUAL(A15, GPIE2OUT, GPIE2, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PIN_DECL_2(A15, GPIOE3, NRI3, GPIE2OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) FUNC_GROUP_DECL(NRI3, A15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) FUNC_GROUP_DECL(GPIE2, B15, A15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define E14 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) SIG_EXPR_LIST_DECL_SINGLE(E14, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SIG_EXPR_LIST_DECL_DUAL(E14, GPIE4IN, GPIE4, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PIN_DECL_2(E14, GPIOE4, NDTR3, GPIE4IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) FUNC_GROUP_DECL(NDTR3, E14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define D14 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) SIG_EXPR_LIST_DECL_SINGLE(D14, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) SIG_EXPR_LIST_DECL_DUAL(D14, GPIE4OUT, GPIE4, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PIN_DECL_2(D14, GPIOE5, NRTS3, GPIE4OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) FUNC_GROUP_DECL(NRTS3, D14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) FUNC_GROUP_DECL(GPIE4, E14, D14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define C14 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) SIG_EXPR_LIST_DECL_SINGLE(C14, TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) SIG_EXPR_LIST_DECL_DUAL(C14, GPIE6IN, GPIE6, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PIN_DECL_2(C14, GPIOE6, TXD3, GPIE6IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) FUNC_GROUP_DECL(TXD3, C14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define B14 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) SIG_EXPR_LIST_DECL_SINGLE(B14, RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) SIG_EXPR_LIST_DECL_DUAL(B14, GPIE6OUT, GPIE6, GPIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PIN_DECL_2(B14, GPIOE7, RXD3, GPIE6OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) FUNC_GROUP_DECL(RXD3, B14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) FUNC_GROUP_DECL(GPIE6, C14, B14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define D18 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) SSSF_PIN_DECL(D18, GPIOF0, NCTS4, SIG_DESC_SET(SCU80, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define ACPI_DESC SIG_DESC_BIT(HW_STRAP1, 19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define B19 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) SIG_EXPR_LIST_DECL_SINGLE(B19, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, ACPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) SIG_EXPR_LIST_DECL_DUAL(B19, SIOPBI, SIOPBI, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PIN_DECL_2(B19, GPIOF1, NDCD4, SIOPBI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) FUNC_GROUP_DECL(NDCD4, B19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) FUNC_GROUP_DECL(SIOPBI, B19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define A20 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) SIG_EXPR_LIST_DECL_SINGLE(A20, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, ACPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SIG_EXPR_LIST_DECL_DUAL(A20, SIOPWRGD, SIOPWRGD, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PIN_DECL_2(A20, GPIOF2, NDSR4, SIOPWRGD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) FUNC_GROUP_DECL(NDSR4, A20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) FUNC_GROUP_DECL(SIOPWRGD, A20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define D17 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) SIG_EXPR_LIST_DECL_SINGLE(D17, NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, ACPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) SIG_EXPR_LIST_DECL_DUAL(D17, SIOPBO, SIOPBO, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PIN_DECL_2(D17, GPIOF3, NRI4, SIOPBO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) FUNC_GROUP_DECL(NRI4, D17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) FUNC_GROUP_DECL(SIOPBO, D17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define B18 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SSSF_PIN_DECL(B18, GPIOF4, NDTR4, SIG_DESC_SET(SCU80, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define A19 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) SIG_EXPR_LIST_DECL_SINGLE(A19, NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, ACPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) SIG_EXPR_LIST_DECL_DUAL(A19, SIOSCI, SIOSCI, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PIN_DECL_2(A19, GPIOF5, NDTS4, SIOSCI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) FUNC_GROUP_DECL(NDTS4, A19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) FUNC_GROUP_DECL(SIOSCI, A19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define E16 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define C17 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define A14 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) SSSF_PIN_DECL(A14, GPIOG0, SGPSCK, SIG_DESC_SET(SCU84, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define E13 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) SSSF_PIN_DECL(E13, GPIOG1, SGPSLD, SIG_DESC_SET(SCU84, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define D13 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) SSSF_PIN_DECL(D13, GPIOG2, SGPSI0, SIG_DESC_SET(SCU84, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define C13 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) SSSF_PIN_DECL(C13, GPIOG3, SGPSI1, SIG_DESC_SET(SCU84, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define B13 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) SIG_EXPR_LIST_DECL_SINGLE(B13, OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) SIG_EXPR_LIST_DECL_SINGLE(B13, WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PIN_DECL_2(B13, GPIOG4, OSCCLK, WDTRST1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) FUNC_GROUP_DECL(OSCCLK, B13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) FUNC_GROUP_DECL(WDTRST1, B13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define Y21 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) SIG_EXPR_LIST_DECL_SINGLE(Y21, USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) SIG_EXPR_LIST_DECL_SINGLE(Y21, WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PIN_DECL_2(Y21, GPIOG5, USBCKI, WDTRST2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) FUNC_GROUP_DECL(USBCKI, Y21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) FUNC_GROUP_DECL(WDTRST2, Y21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define AA22 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define U18 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define UART6_DESC SIG_DESC_SET(SCU90, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define ROM16_DESC SIG_DESC_SET(SCU90, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define A8 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) SIG_EXPR_DECL_SINGLE(ROMD8, ROM16, ROM16_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) SIG_EXPR_DECL_SINGLE(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SIG_EXPR_LIST_DECL_DUAL(A8, ROMD8, ROM16, ROM16S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) SIG_EXPR_LIST_DECL_SINGLE(A8, NCTS6, NCTS6, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define C7 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) SIG_EXPR_DECL_SINGLE(ROMD9, ROM16, ROM16_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) SIG_EXPR_DECL_SINGLE(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) SIG_EXPR_LIST_DECL_DUAL(C7, ROMD9, ROM16, ROM16S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) SIG_EXPR_LIST_DECL_SINGLE(C7, NDCD6, NDCD6, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PIN_DECL_2(C7, GPIOH1, ROMD9, NDCD6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define B7 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SIG_EXPR_DECL_SINGLE(ROMD10, ROM16, ROM16_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) SIG_EXPR_DECL_SINGLE(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) SIG_EXPR_LIST_DECL_DUAL(B7, ROMD10, ROM16, ROM16S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SIG_EXPR_LIST_DECL_SINGLE(B7, NDSR6, NDSR6, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PIN_DECL_2(B7, GPIOH2, ROMD10, NDSR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define A7 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) SIG_EXPR_DECL_SINGLE(ROMD11, ROM16, ROM16_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) SIG_EXPR_DECL_SINGLE(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) SIG_EXPR_LIST_DECL_DUAL(A7, ROMD11, ROM16, ROM16S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) SIG_EXPR_LIST_DECL_SINGLE(A7, NRI6, NRI6, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PIN_DECL_2(A7, GPIOH3, ROMD11, NRI6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define D7 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SIG_EXPR_DECL_SINGLE(ROMD12, ROM16, ROM16_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SIG_EXPR_DECL_SINGLE(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) SIG_EXPR_LIST_DECL_DUAL(D7, ROMD12, ROM16, ROM16S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) SIG_EXPR_LIST_DECL_SINGLE(D7, NDTR6, NDTR6, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PIN_DECL_2(D7, GPIOH4, ROMD12, NDTR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define B6 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) SIG_EXPR_DECL_SINGLE(ROMD13, ROM16, ROM16_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) SIG_EXPR_DECL_SINGLE(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) SIG_EXPR_LIST_DECL_DUAL(B6, ROMD13, ROM16, ROM16S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SIG_EXPR_LIST_DECL_SINGLE(B6, NRTS6, NRTS6, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PIN_DECL_2(B6, GPIOH5, ROMD13, NRTS6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define A6 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) SIG_EXPR_DECL_SINGLE(ROMD14, ROM16, ROM16_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) SIG_EXPR_DECL_SINGLE(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SIG_EXPR_LIST_DECL_DUAL(A6, ROMD14, ROM16, ROM16S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) SIG_EXPR_LIST_DECL_SINGLE(A6, TXD6, TXD6, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PIN_DECL_2(A6, GPIOH6, ROMD14, TXD6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define E7 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) SIG_EXPR_DECL_SINGLE(ROMD15, ROM16, ROM16_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) SIG_EXPR_DECL_SINGLE(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) SIG_EXPR_LIST_DECL_DUAL(E7, ROMD15, ROM16, ROM16S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SIG_EXPR_LIST_DECL_SINGLE(E7, RXD6, RXD6, UART6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PIN_DECL_2(E7, GPIOH7, ROMD15, RXD6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SPI1_DESC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define SPI1DEBUG_DESC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SPI1PASSTHRU_DESC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define C22 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) SIG_EXPR_LIST_DECL_DUAL(C22, SYSCS, SPI1DEBUG, SPI1PASSTHRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PIN_DECL_1(C22, GPIOI0, SYSCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define G18 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) SIG_EXPR_LIST_DECL_DUAL(G18, SYSCK, SPI1DEBUG, SPI1PASSTHRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PIN_DECL_1(G18, GPIOI1, SYSCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define D19 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) SIG_EXPR_DECL_SINGLE(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) SIG_EXPR_DECL_SINGLE(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) SIG_EXPR_LIST_DECL_DUAL(D19, SYSDO, SPI1DEBUG, SPI1PASSTHRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PIN_DECL_1(D19, GPIOI2, SYSDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define C20 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) SIG_EXPR_DECL_SINGLE(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) SIG_EXPR_DECL_SINGLE(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) SIG_EXPR_LIST_DECL_DUAL(C20, SYSDI, SPI1DEBUG, SPI1PASSTHRU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PIN_DECL_1(C20, GPIOI3, SYSDI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define B22 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, SPI1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) SIG_EXPR_LIST_DECL(SPI1CS0, SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) SIG_EXPR_PTR(SPI1CS0, SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) SIG_EXPR_LIST_ALIAS(B22, SPI1CS0, SPI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) SIG_EXPR_LIST_DECL_SINGLE(B22, VBCS, VGABIOS_ROM, VB_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PIN_DECL_2(B22, GPIOI4, SPI1CS0, VBCS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define G19 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, SPI1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) SIG_EXPR_LIST_DECL(SPI1CK, SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) SIG_EXPR_PTR(SPI1CK, SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) SIG_EXPR_LIST_ALIAS(G19, SPI1CK, SPI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) SIG_EXPR_LIST_DECL_SINGLE(G19, VBCK, VGABIOS_ROM, VB_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PIN_DECL_2(G19, GPIOI5, SPI1CK, VBCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define C18 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1, SPI1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) SIG_EXPR_LIST_DECL(SPI1DO, SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) SIG_EXPR_PTR(SPI1DO, SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) SIG_EXPR_PTR(SPI1DO, SPI1DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) SIG_EXPR_PTR(SPI1DO, SPI1PASSTHRU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) SIG_EXPR_LIST_ALIAS(C18, SPI1DO, SPI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) SIG_EXPR_LIST_DECL_SINGLE(C18, VBDO, VGABIOS_ROM, VB_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PIN_DECL_2(C18, GPIOI6, SPI1DO, VBDO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define E20 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1, SPI1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) SIG_EXPR_LIST_DECL(SPI1DI, SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) SIG_EXPR_PTR(SPI1DI, SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) SIG_EXPR_PTR(SPI1DI, SPI1DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) SIG_EXPR_PTR(SPI1DI, SPI1PASSTHRU));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) SIG_EXPR_LIST_ALIAS(E20, SPI1DI, SPI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) SIG_EXPR_LIST_DECL_SINGLE(E20, VBDI, VGABIOS_ROM, VB_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PIN_DECL_2(E20, GPIOI7, SPI1DI, VBDI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) FUNC_GROUP_DECL(SPI1, B22, G19, C18, E20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) FUNC_GROUP_DECL(SPI1DEBUG, C22, G18, D19, C20, B22, G19, C18, E20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) FUNC_GROUP_DECL(SPI1PASSTHRU, C22, G18, D19, C20, B22, G19, C18, E20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) FUNC_GROUP_DECL(VGABIOS_ROM, B22, G19, C18, E20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define J5 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) SSSF_PIN_DECL(J5, GPIOJ0, SGPMCK, SIG_DESC_SET(SCU84, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define J4 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) SSSF_PIN_DECL(J4, GPIOJ1, SGPMLD, SIG_DESC_SET(SCU84, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define K5 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) SSSF_PIN_DECL(K5, GPIOJ2, SGPMO, SIG_DESC_SET(SCU84, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define J3 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define T4 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) SSSF_PIN_DECL(T4, GPIOJ4, VGAHS, SIG_DESC_SET(SCU84, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define U2 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) SSSF_PIN_DECL(U2, GPIOJ5, VGAVS, SIG_DESC_SET(SCU84, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define T2 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) SSSF_PIN_DECL(T2, GPIOJ6, DDCCLK, SIG_DESC_SET(SCU84, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define T1 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define I2C5_DESC SIG_DESC_SET(SCU90, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define E3 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) SIG_EXPR_LIST_DECL_SINGLE(E3, SCL5, I2C5, I2C5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PIN_DECL_1(E3, GPIOK0, SCL5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define D2 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) SIG_EXPR_LIST_DECL_SINGLE(D2, SDA5, I2C5, I2C5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PIN_DECL_1(D2, GPIOK1, SDA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) FUNC_GROUP_DECL(I2C5, E3, D2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define I2C6_DESC SIG_DESC_SET(SCU90, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define C1 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) SIG_EXPR_LIST_DECL_SINGLE(C1, SCL6, I2C6, I2C6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PIN_DECL_1(C1, GPIOK2, SCL6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define F4 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SIG_EXPR_LIST_DECL_SINGLE(F4, SDA6, I2C6, I2C6_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PIN_DECL_1(F4, GPIOK3, SDA6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) FUNC_GROUP_DECL(I2C6, C1, F4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define I2C7_DESC SIG_DESC_SET(SCU90, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define E2 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) SIG_EXPR_LIST_DECL_SINGLE(E2, SCL7, I2C7, I2C7_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PIN_DECL_1(E2, GPIOK4, SCL7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define D1 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) SIG_EXPR_LIST_DECL_SINGLE(D1, SDA7, I2C7, I2C7_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PIN_DECL_1(D1, GPIOK5, SDA7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) FUNC_GROUP_DECL(I2C7, E2, D1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define I2C8_DESC SIG_DESC_SET(SCU90, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define G5 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) SIG_EXPR_LIST_DECL_SINGLE(G5, SCL8, I2C8, I2C8_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PIN_DECL_1(G5, GPIOK6, SCL8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define F3 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) SIG_EXPR_LIST_DECL_SINGLE(F3, SDA8, I2C8, I2C8_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PIN_DECL_1(F3, GPIOK7, SDA8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) FUNC_GROUP_DECL(I2C8, G5, F3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define U1 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define VPI18_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define VPI30_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define T5 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define T5_DESC SIG_DESC_SET(SCU84, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) SIG_EXPR_DECL_SINGLE(VPIDE, VPI18, VPI18_DESC, T5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) SIG_EXPR_DECL_SINGLE(VPIDE, VPI24, VPI24_DESC, T5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) SIG_EXPR_DECL_SINGLE(VPIDE, VPI30, VPI30_DESC, T5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) SIG_EXPR_LIST_DECL(VPIDE, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) SIG_EXPR_PTR(VPIDE, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) SIG_EXPR_PTR(VPIDE, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) SIG_EXPR_PTR(VPIDE, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) SIG_EXPR_LIST_ALIAS(T5, VPIDE, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) SIG_EXPR_LIST_DECL_SINGLE(T5, NDCD1, NDCD1, T5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PIN_DECL_2(T5, GPIOL1, VPIDE, NDCD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) FUNC_GROUP_DECL(NDCD1, T5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define U3 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define U3_DESC SIG_DESC_SET(SCU84, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) SIG_EXPR_DECL_SINGLE(VPIODD, VPI18, VPI18_DESC, U3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) SIG_EXPR_DECL_SINGLE(VPIODD, VPI24, VPI24_DESC, U3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) SIG_EXPR_DECL_SINGLE(VPIODD, VPI30, VPI30_DESC, U3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) SIG_EXPR_LIST_DECL(VPIODD, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) SIG_EXPR_PTR(VPIODD, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) SIG_EXPR_PTR(VPIODD, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) SIG_EXPR_PTR(VPIODD, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) SIG_EXPR_LIST_ALIAS(U3, VPIODD, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) SIG_EXPR_LIST_DECL_SINGLE(U3, NDSR1, NDSR1, U3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PIN_DECL_2(U3, GPIOL2, VPIODD, NDSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) FUNC_GROUP_DECL(NDSR1, U3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define V1 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define V1_DESC SIG_DESC_SET(SCU84, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) SIG_EXPR_DECL_SINGLE(VPIHS, VPI18, VPI18_DESC, V1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) SIG_EXPR_DECL_SINGLE(VPIHS, VPI24, VPI24_DESC, V1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) SIG_EXPR_DECL_SINGLE(VPIHS, VPI30, VPI30_DESC, V1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) SIG_EXPR_LIST_DECL(VPIHS, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) SIG_EXPR_PTR(VPIHS, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) SIG_EXPR_PTR(VPIHS, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) SIG_EXPR_PTR(VPIHS, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) SIG_EXPR_LIST_ALIAS(V1, VPIHS, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) SIG_EXPR_LIST_DECL_SINGLE(V1, NRI1, NRI1, V1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PIN_DECL_2(V1, GPIOL3, VPIHS, NRI1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) FUNC_GROUP_DECL(NRI1, V1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define U4 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define U4_DESC SIG_DESC_SET(SCU84, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) SIG_EXPR_DECL_SINGLE(VPIVS, VPI18, VPI18_DESC, U4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) SIG_EXPR_DECL_SINGLE(VPIVS, VPI24, VPI24_DESC, U4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) SIG_EXPR_DECL_SINGLE(VPIVS, VPI30, VPI30_DESC, U4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) SIG_EXPR_LIST_DECL(VPIVS, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) SIG_EXPR_PTR(VPIVS, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) SIG_EXPR_PTR(VPIVS, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) SIG_EXPR_PTR(VPIVS, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) SIG_EXPR_LIST_ALIAS(U4, VPIVS, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) SIG_EXPR_LIST_DECL_SINGLE(U4, NDTR1, NDTR1, U4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PIN_DECL_2(U4, GPIOL4, VPIVS, NDTR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) FUNC_GROUP_DECL(NDTR1, U4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define V2 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define V2_DESC SIG_DESC_SET(SCU84, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) SIG_EXPR_DECL_SINGLE(VPICLK, VPI18, VPI18_DESC, V2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) SIG_EXPR_DECL_SINGLE(VPICLK, VPI24, VPI24_DESC, V2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) SIG_EXPR_DECL_SINGLE(VPICLK, VPI30, VPI30_DESC, V2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) SIG_EXPR_LIST_DECL(VPICLK, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) SIG_EXPR_PTR(VPICLK, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) SIG_EXPR_PTR(VPICLK, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) SIG_EXPR_PTR(VPICLK, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) SIG_EXPR_LIST_ALIAS(V2, VPICLK, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) SIG_EXPR_LIST_DECL_SINGLE(V2, NRTS1, NRTS1, V2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PIN_DECL_2(V2, GPIOL5, VPICLK, NRTS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) FUNC_GROUP_DECL(NRTS1, V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define W1 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define W1_DESC SIG_DESC_SET(SCU84, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) SIG_EXPR_LIST_DECL_SINGLE(W1, VPIB0, VPI30, VPI30_DESC, W1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) SIG_EXPR_LIST_DECL_SINGLE(W1, TXD1, TXD1, W1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PIN_DECL_2(W1, GPIOL6, VPIB0, TXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) FUNC_GROUP_DECL(TXD1, W1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define U5 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define U5_DESC SIG_DESC_SET(SCU84, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) SIG_EXPR_LIST_DECL_SINGLE(U5, VPIB1, VPI30, VPI30_DESC, U5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) SIG_EXPR_LIST_DECL_SINGLE(U5, RXD1, RXD1, U5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) PIN_DECL_2(U5, GPIOL7, VPIB1, RXD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) FUNC_GROUP_DECL(RXD1, U5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define V3 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define V3_DESC SIG_DESC_SET(SCU84, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) SIG_EXPR_DECL_SINGLE(VPIOB2, VPI18, VPI18_DESC, V3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) SIG_EXPR_DECL_SINGLE(VPIOB2, VPI24, VPI24_DESC, V3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) SIG_EXPR_DECL_SINGLE(VPIOB2, VPI30, VPI30_DESC, V3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) SIG_EXPR_LIST_DECL(VPIOB2, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) SIG_EXPR_PTR(VPIOB2, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) SIG_EXPR_PTR(VPIOB2, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) SIG_EXPR_PTR(VPIOB2, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) SIG_EXPR_LIST_ALIAS(V3, VPIOB2, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) SIG_EXPR_LIST_DECL_SINGLE(V3, NCTS2, NCTS2, V3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PIN_DECL_2(V3, GPIOM0, VPIOB2, NCTS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) FUNC_GROUP_DECL(NCTS2, V3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define W2 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define W2_DESC SIG_DESC_SET(SCU84, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) SIG_EXPR_DECL_SINGLE(VPIOB3, VPI18, VPI18_DESC, W2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) SIG_EXPR_DECL_SINGLE(VPIOB3, VPI24, VPI24_DESC, W2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) SIG_EXPR_DECL_SINGLE(VPIOB3, VPI30, VPI30_DESC, W2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) SIG_EXPR_LIST_DECL(VPIOB3, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) SIG_EXPR_PTR(VPIOB3, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) SIG_EXPR_PTR(VPIOB3, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) SIG_EXPR_PTR(VPIOB3, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) SIG_EXPR_LIST_ALIAS(W2, VPIOB3, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) SIG_EXPR_LIST_DECL_SINGLE(W2, NDCD2, NDCD2, W2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PIN_DECL_2(W2, GPIOM1, VPIOB3, NDCD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) FUNC_GROUP_DECL(NDCD2, W2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define Y1 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define Y1_DESC SIG_DESC_SET(SCU84, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) SIG_EXPR_DECL_SINGLE(VPIOB4, VPI18, VPI18_DESC, Y1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) SIG_EXPR_DECL_SINGLE(VPIOB4, VPI24, VPI24_DESC, Y1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) SIG_EXPR_DECL_SINGLE(VPIOB4, VPI30, VPI30_DESC, Y1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) SIG_EXPR_LIST_DECL(VPIOB4, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) SIG_EXPR_PTR(VPIOB4, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) SIG_EXPR_PTR(VPIOB4, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) SIG_EXPR_PTR(VPIOB4, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) SIG_EXPR_LIST_ALIAS(Y1, VPIOB4, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) SIG_EXPR_LIST_DECL_SINGLE(Y1, NDSR2, NDSR2, Y1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) PIN_DECL_2(Y1, GPIOM2, VPIOB4, NDSR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) FUNC_GROUP_DECL(NDSR2, Y1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define V4 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define V4_DESC SIG_DESC_SET(SCU84, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) SIG_EXPR_DECL_SINGLE(VPIOB5, VPI18, VPI18_DESC, V4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) SIG_EXPR_DECL_SINGLE(VPIOB5, VPI24, VPI24_DESC, V4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) SIG_EXPR_DECL_SINGLE(VPIOB5, VPI30, VPI30_DESC, V4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) SIG_EXPR_LIST_DECL(VPIOB5, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) SIG_EXPR_PTR(VPIOB5, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) SIG_EXPR_PTR(VPIOB5, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) SIG_EXPR_PTR(VPIOB5, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) SIG_EXPR_LIST_ALIAS(V4, VPIOB5, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) SIG_EXPR_LIST_DECL_SINGLE(V4, NRI2, NRI2, V4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PIN_DECL_2(V4, GPIOM3, VPIOB5, NRI2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) FUNC_GROUP_DECL(NRI2, V4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define W3 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define W3_DESC SIG_DESC_SET(SCU84, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) SIG_EXPR_DECL_SINGLE(VPIOB6, VPI18, VPI18_DESC, W3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) SIG_EXPR_DECL_SINGLE(VPIOB6, VPI24, VPI24_DESC, W3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) SIG_EXPR_DECL_SINGLE(VPIOB6, VPI30, VPI30_DESC, W3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) SIG_EXPR_LIST_DECL(VPIOB6, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) SIG_EXPR_PTR(VPIOB6, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) SIG_EXPR_PTR(VPIOB6, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) SIG_EXPR_PTR(VPIOB6, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) SIG_EXPR_LIST_ALIAS(W3, VPIOB6, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) SIG_EXPR_LIST_DECL_SINGLE(W3, NDTR2, NDTR2, W3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) PIN_DECL_2(W3, GPIOM4, VPIOB6, NDTR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) FUNC_GROUP_DECL(NDTR2, W3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define Y2 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define Y2_DESC SIG_DESC_SET(SCU84, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) SIG_EXPR_DECL_SINGLE(VPIOB7, VPI18, VPI18_DESC, Y2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) SIG_EXPR_DECL_SINGLE(VPIOB7, VPI24, VPI24_DESC, Y2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) SIG_EXPR_DECL_SINGLE(VPIOB7, VPI30, VPI30_DESC, Y2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) SIG_EXPR_LIST_DECL(VPIOB7, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) SIG_EXPR_PTR(VPIOB7, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) SIG_EXPR_PTR(VPIOB7, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) SIG_EXPR_PTR(VPIOB7, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) SIG_EXPR_LIST_ALIAS(Y2, VPIOB7, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) SIG_EXPR_LIST_DECL_SINGLE(Y2, NRTS2, NRTS2, Y2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) PIN_DECL_2(Y2, GPIOM5, VPIOB7, NRTS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) FUNC_GROUP_DECL(NRTS2, Y2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define AA1 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define AA1_DESC SIG_DESC_SET(SCU84, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) SIG_EXPR_DECL_SINGLE(VPIOB8, VPI18, VPI18_DESC, AA1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) SIG_EXPR_DECL_SINGLE(VPIOB8, VPI24, VPI24_DESC, AA1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) SIG_EXPR_DECL_SINGLE(VPIOB8, VPI30, VPI30_DESC, AA1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) SIG_EXPR_LIST_DECL(VPIOB8, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) SIG_EXPR_PTR(VPIOB8, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) SIG_EXPR_PTR(VPIOB8, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) SIG_EXPR_PTR(VPIOB8, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) SIG_EXPR_LIST_ALIAS(AA1, VPIOB8, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) SIG_EXPR_LIST_DECL_SINGLE(AA1, TXD2, TXD2, AA1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PIN_DECL_2(AA1, GPIOM6, VPIOB8, TXD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) FUNC_GROUP_DECL(TXD2, AA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define V5 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define V5_DESC SIG_DESC_SET(SCU84, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) SIG_EXPR_DECL_SINGLE(VPIOB9, VPI18, VPI18_DESC, V5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) SIG_EXPR_DECL_SINGLE(VPIOB9, VPI24, VPI24_DESC, V5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) SIG_EXPR_DECL_SINGLE(VPIOB9, VPI30, VPI30_DESC, V5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) SIG_EXPR_LIST_DECL(VPIOB9, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) SIG_EXPR_PTR(VPIOB9, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) SIG_EXPR_PTR(VPIOB9, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) SIG_EXPR_PTR(VPIOB9, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) SIG_EXPR_LIST_ALIAS(V5, VPIOB9, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) SIG_EXPR_LIST_DECL_SINGLE(V5, RXD2, RXD2, V5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PIN_DECL_2(V5, GPIOM7, VPIOB9, RXD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) FUNC_GROUP_DECL(RXD2, V5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define W4 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define W4_DESC SIG_DESC_SET(SCU88, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) SIG_EXPR_LIST_DECL_SINGLE(W4, VPIG0, VPI30, VPI30_DESC, W4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) SIG_EXPR_LIST_DECL_SINGLE(W4, PWM0, PWM0, W4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PIN_DECL_2(W4, GPION0, VPIG0, PWM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) FUNC_GROUP_DECL(PWM0, W4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define Y3 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define Y3_DESC SIG_DESC_SET(SCU88, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG1, VPI30, VPI30_DESC, Y3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM1, PWM1, Y3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PIN_DECL_2(Y3, GPION1, VPIG1, PWM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) FUNC_GROUP_DECL(PWM1, Y3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define AA2 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define AA2_DESC SIG_DESC_SET(SCU88, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) SIG_EXPR_DECL_SINGLE(VPIG2, VPI18, VPI18_DESC, AA2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, AA2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) SIG_EXPR_DECL_SINGLE(VPIG2, VPI30, VPI30_DESC, AA2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) SIG_EXPR_LIST_DECL(VPIG2, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) SIG_EXPR_PTR(VPIG2, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) SIG_EXPR_PTR(VPIG2, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) SIG_EXPR_PTR(VPIG2, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) SIG_EXPR_LIST_ALIAS(AA2, VPIG2, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) SIG_EXPR_LIST_DECL_SINGLE(AA2, PWM2, PWM2, AA2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PIN_DECL_2(AA2, GPION2, VPIG2, PWM2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) FUNC_GROUP_DECL(PWM2, AA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define AB1 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define AB1_DESC SIG_DESC_SET(SCU88, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) SIG_EXPR_DECL_SINGLE(VPIG3, VPI18, VPI18_DESC, AB1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, AB1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) SIG_EXPR_DECL_SINGLE(VPIG3, VPI30, VPI30_DESC, AB1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) SIG_EXPR_LIST_DECL(VPIG3, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) SIG_EXPR_PTR(VPIG3, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) SIG_EXPR_PTR(VPIG3, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) SIG_EXPR_PTR(VPIG3, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) SIG_EXPR_LIST_ALIAS(AB1, VPIG3, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) SIG_EXPR_LIST_DECL_SINGLE(AB1, PWM3, PWM3, AB1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PIN_DECL_2(AB1, GPION3, VPIG3, PWM3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) FUNC_GROUP_DECL(PWM3, AB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define W5 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define W5_DESC SIG_DESC_SET(SCU88, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) SIG_EXPR_DECL_SINGLE(VPIG4, VPI18, VPI18_DESC, W5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) SIG_EXPR_DECL_SINGLE(VPIG4, VPI30, VPI30_DESC, W5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) SIG_EXPR_LIST_DECL(VPIG4, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) SIG_EXPR_PTR(VPIG4, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) SIG_EXPR_PTR(VPIG4, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) SIG_EXPR_PTR(VPIG4, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) SIG_EXPR_LIST_ALIAS(W5, VPIG4, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) SIG_EXPR_LIST_DECL_SINGLE(W5, PWM4, PWM4, W5_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PIN_DECL_2(W5, GPION4, VPIG4, PWM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) FUNC_GROUP_DECL(PWM4, W5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define Y4 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define Y4_DESC SIG_DESC_SET(SCU88, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) SIG_EXPR_DECL_SINGLE(VPIG5, VPI18, VPI18_DESC, Y4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, Y4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) SIG_EXPR_DECL_SINGLE(VPIG5, VPI30, VPI30_DESC, Y4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) SIG_EXPR_LIST_DECL(VPIG5, VPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) SIG_EXPR_PTR(VPIG5, VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) SIG_EXPR_PTR(VPIG5, VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) SIG_EXPR_PTR(VPIG5, VPI30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) SIG_EXPR_LIST_ALIAS(Y4, VPIG5, VPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) SIG_EXPR_LIST_DECL_SINGLE(Y4, PWM5, PWM5, Y4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PIN_DECL_2(Y4, GPION5, VPIG5, PWM5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) FUNC_GROUP_DECL(PWM5, Y4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define AA3 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define AA3_DESC SIG_DESC_SET(SCU88, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) SIG_EXPR_LIST_DECL_SINGLE(AA3, VPIG6, VPI30, VPI30_DESC, AA3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM6, PWM6, AA3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PIN_DECL_2(AA3, GPION6, VPIG6, PWM6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) FUNC_GROUP_DECL(PWM6, AA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define AB2 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define AB2_DESC SIG_DESC_SET(SCU88, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIG7, VPI30, VPI30_DESC, AB2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) SIG_EXPR_LIST_DECL_SINGLE(AB2, PWM7, PWM7, AB2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PIN_DECL_2(AB2, GPION7, VPIG7, PWM7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) FUNC_GROUP_DECL(PWM7, AB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define V6 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) SIG_EXPR_LIST_DECL_SINGLE(V6, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PIN_DECL_1(V6, GPIOO0, VPIG8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define Y5 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) SIG_EXPR_LIST_DECL_SINGLE(Y5, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PIN_DECL_1(Y5, GPIOO1, VPIG9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define AA4 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR0, VPI30, VPI30_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) SIG_DESC_SET(SCU88, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PIN_DECL_1(AA4, GPIOO2, VPIR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define AB3 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR1, VPI30, VPI30_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) SIG_DESC_SET(SCU88, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PIN_DECL_1(AB3, GPIOO3, VPIR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define W6 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) SIG_EXPR_LIST_DECL_SINGLE(W6, VPIR2, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) SIG_DESC_SET(SCU88, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PIN_DECL_1(W6, GPIOO4, VPIR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define AA5 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR3, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) SIG_DESC_SET(SCU88, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PIN_DECL_1(AA5, GPIOO5, VPIR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define AB4 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) SIG_EXPR_LIST_DECL_SINGLE(AB4, VPIR4, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) SIG_DESC_SET(SCU88, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PIN_DECL_1(AB4, GPIOO6, VPIR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define V7 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) SIG_EXPR_LIST_DECL_SINGLE(V7, VPIR5, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) SIG_DESC_SET(SCU88, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PIN_DECL_1(V7, GPIOO7, VPIR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) #define Y6 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) SIG_EXPR_LIST_DECL_SINGLE(Y6, VPIR6, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) SIG_DESC_SET(SCU88, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PIN_DECL_1(Y6, GPIOP0, VPIR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define AB5 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR7, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) SIG_DESC_SET(SCU88, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PIN_DECL_1(AB5, GPIOP1, VPIR7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define W7 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) SIG_EXPR_LIST_DECL_SINGLE(W7, VPIR8, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) SIG_DESC_SET(SCU88, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PIN_DECL_1(W7, GPIOP2, VPIR8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define AA6 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) SIG_EXPR_LIST_DECL_SINGLE(AA6, VPIR9, VPI24, VPI24_DESC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) SIG_DESC_SET(SCU88, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PIN_DECL_1(AA6, GPIOP3, VPIR9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) AA22, W5, Y4, AA3, AB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) AA22, W5, Y4, AA3, AB2, V6, Y5, W6, AA5, AB4, V7, Y6, AB5, W7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) AA6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) V5, W4, Y3, AA22, W5, Y4, AA3, AB2, AA4, AB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define AB6 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) SIG_EXPR_LIST_DECL_SINGLE(AB6, GPIOP4, GPIOP4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(AB6, GPIOP4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define Y7 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) SIG_EXPR_LIST_DECL_SINGLE(Y7, GPIOP5, GPIOP5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PIN_DECL_(Y7, SIG_EXPR_LIST_PTR(Y7, GPIOP5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define AA7 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) SSSF_PIN_DECL(AA7, GPIOP6, BMCINT, SIG_DESC_SET(SCU88, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define AB7 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) SSSF_PIN_DECL(AB7, GPIOP7, FLACK, SIG_DESC_SET(SCU88, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define I2C3_DESC SIG_DESC_SET(SCU90, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define D3 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) SIG_EXPR_LIST_DECL_SINGLE(D3, SCL3, I2C3, I2C3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) PIN_DECL_1(D3, GPIOQ0, SCL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define C2 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) SIG_EXPR_LIST_DECL_SINGLE(C2, SDA3, I2C3, I2C3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) PIN_DECL_1(C2, GPIOQ1, SDA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) FUNC_GROUP_DECL(I2C3, D3, C2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define I2C4_DESC SIG_DESC_SET(SCU90, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define B1 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) SIG_EXPR_LIST_DECL_SINGLE(B1, SCL4, I2C4, I2C4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PIN_DECL_1(B1, GPIOQ2, SCL4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define F5 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) SIG_EXPR_LIST_DECL_SINGLE(F5, SDA4, I2C4, I2C4_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PIN_DECL_1(F5, GPIOQ3, SDA4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) FUNC_GROUP_DECL(I2C4, B1, F5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define I2C14_DESC SIG_DESC_SET(SCU90, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define H4 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) SIG_EXPR_LIST_DECL_SINGLE(H4, SCL14, I2C14, I2C14_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PIN_DECL_1(H4, GPIOQ4, SCL14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define H3 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) SIG_EXPR_LIST_DECL_SINGLE(H3, SDA14, I2C14, I2C14_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PIN_DECL_1(H3, GPIOQ5, SDA14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) FUNC_GROUP_DECL(I2C14, H4, H3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * There are several opportunities to document USB port 4 in the datasheet, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * it is only mentioned in one location. Particularly, the Multi-function Pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * Mapping and Control table in the datasheet elides the signal names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * suggesting that port 4 may not actually be functional. As such we define the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * signal names and control bit, but don't export the capability's function or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define USB11H3_DESC SIG_DESC_SET(SCU90, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define H2 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) SIG_EXPR_LIST_DECL_SINGLE(H2, USB11HDP3, USB11H3, USB11H3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PIN_DECL_1(H2, GPIOQ6, USB11HDP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define H1 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) SIG_EXPR_LIST_DECL_SINGLE(H1, USB11HDN3, USB11H3, USB11H3_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PIN_DECL_1(H1, GPIOQ7, USB11HDN3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define V20 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define W21 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) SSSF_PIN_DECL(W21, GPIOR1, ROMCS2, SIG_DESC_SET(SCU88, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define Y22 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) SSSF_PIN_DECL(Y22, GPIOR2, ROMCS3, SIG_DESC_SET(SCU88, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define U19 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define VPO12_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define VPO24_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define VPO_OFF_12 { ASPEED_IP_SCU, SCU94, 0x2, 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define VPO_24_OFF SIG_DESC_SET(SCU94, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define V21 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define V21_DESC SIG_DESC_SET(SCU88, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) SIG_EXPR_DECL_SINGLE(ROMA24, ROM8, V21_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) SIG_EXPR_DECL_SINGLE(ROMA24, ROM16, V21_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) SIG_EXPR_DECL_SINGLE(ROMA24, ROM16S, V21_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) SIG_EXPR_LIST_DECL(ROMA24, ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) SIG_EXPR_PTR(ROMA24, ROM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) SIG_EXPR_PTR(ROMA24, ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) SIG_EXPR_PTR(ROMA24, ROM16S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) SIG_EXPR_LIST_ALIAS(V21, ROMA24, ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) SIG_EXPR_LIST_DECL_SINGLE(V21, VPOR6, VPO24, V21_DESC, VPO_24_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PIN_DECL_2(V21, GPIOR4, ROMA24, VPOR6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define W22 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #define W22_DESC SIG_DESC_SET(SCU88, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) SIG_EXPR_DECL_SINGLE(ROMA25, ROM8, W22_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) SIG_EXPR_DECL_SINGLE(ROMA25, ROM16, W22_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) SIG_EXPR_DECL_SINGLE(ROMA25, ROM16S, W22_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) SIG_EXPR_LIST_DECL(ROMA25, ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) SIG_EXPR_PTR(ROMA25, ROM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) SIG_EXPR_PTR(ROMA25, ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) SIG_EXPR_PTR(ROMA25, ROM16S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) SIG_EXPR_LIST_ALIAS(W22, ROMA25, ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) SIG_EXPR_LIST_DECL_SINGLE(W22, VPOR7, VPO24, W22_DESC, VPO_24_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PIN_DECL_2(W22, GPIOR5, ROMA25, VPOR7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define C6 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) SIG_EXPR_LIST_DECL_SINGLE(C6, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) PIN_DECL_1(C6, GPIOR6, MDC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define A5 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) SIG_EXPR_LIST_DECL_SINGLE(A5, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PIN_DECL_1(A5, GPIOR7, MDIO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) FUNC_GROUP_DECL(MDIO1, C6, A5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define U21 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define U21_DESC SIG_DESC_SET(SCU8C, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) SIG_EXPR_DECL_SINGLE(ROMD4, ROM8, U21_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) SIG_EXPR_DECL_SINGLE(ROMD4, ROM16, U21_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) SIG_EXPR_DECL_SINGLE(ROMD4, ROM16S, U21_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) SIG_EXPR_LIST_DECL(ROMD4, ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) SIG_EXPR_PTR(ROMD4, ROM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) SIG_EXPR_PTR(ROMD4, ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) SIG_EXPR_PTR(ROMD4, ROM16S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) SIG_EXPR_LIST_ALIAS(U21, ROMD4, ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) SIG_EXPR_DECL_SINGLE(VPODE, VPO12, U21_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) SIG_EXPR_DECL_SINGLE(VPODE, VPO24, U21_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) SIG_EXPR_LIST_DECL_DUAL(U21, VPODE, VPO12, VPO24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PIN_DECL_2(U21, GPIOS0, ROMD4, VPODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define T19 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define T19_DESC SIG_DESC_SET(SCU8C, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) SIG_EXPR_DECL_SINGLE(ROMD5, ROM8, T19_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) SIG_EXPR_DECL_SINGLE(ROMD5, ROM16, T19_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) SIG_EXPR_DECL_SINGLE(ROMD5, ROM16S, T19_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) SIG_EXPR_LIST_DECL(ROMD5, ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) SIG_EXPR_PTR(ROMD5, ROM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) SIG_EXPR_PTR(ROMD5, ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) SIG_EXPR_PTR(ROMD5, ROM16S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) SIG_EXPR_LIST_ALIAS(T19, ROMD5, ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) SIG_EXPR_DECL_SINGLE(VPOHS, VPO12, T19_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) SIG_EXPR_DECL_SINGLE(VPOHS, VPO24, T19_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) SIG_EXPR_LIST_DECL_DUAL(T19, VPOHS, VPO12, VPO24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PIN_DECL_2(T19, GPIOS1, ROMD5, VPOHS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define V22 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define V22_DESC SIG_DESC_SET(SCU8C, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) SIG_EXPR_DECL_SINGLE(ROMD6, ROM8, V22_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) SIG_EXPR_DECL_SINGLE(ROMD6, ROM16, V22_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) SIG_EXPR_DECL_SINGLE(ROMD6, ROM16S, V22_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) SIG_EXPR_LIST_DECL(ROMD6, ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) SIG_EXPR_PTR(ROMD6, ROM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) SIG_EXPR_PTR(ROMD6, ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) SIG_EXPR_PTR(ROMD6, ROM16S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) SIG_EXPR_LIST_ALIAS(V22, ROMD6, ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) SIG_EXPR_DECL_SINGLE(VPOVS, VPO12, V22_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) SIG_EXPR_DECL_SINGLE(VPOVS, VPO24, V22_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) SIG_EXPR_LIST_DECL_DUAL(V22, VPOVS, VPO12, VPO24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PIN_DECL_2(V22, GPIOS2, ROMD6, VPOVS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define U20 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define U20_DESC SIG_DESC_SET(SCU8C, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) SIG_EXPR_DECL_SINGLE(ROMD7, ROM8, U20_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) SIG_EXPR_DECL_SINGLE(ROMD7, ROM16, U20_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) SIG_EXPR_DECL_SINGLE(ROMD7, ROM16S, U20_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) SIG_EXPR_LIST_DECL(ROMD7, ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) SIG_EXPR_PTR(ROMD7, ROM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) SIG_EXPR_PTR(ROMD7, ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) SIG_EXPR_PTR(ROMD7, ROM16S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) SIG_EXPR_LIST_ALIAS(U20, ROMD7, ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) SIG_EXPR_DECL_SINGLE(VPOCLK, VPO12, U20_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) SIG_EXPR_DECL_SINGLE(VPOCLK, VPO24, U20_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) SIG_EXPR_LIST_DECL_DUAL(U20, VPOCLK, VPO12, VPO24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PIN_DECL_2(U20, GPIOS3, ROMD7, VPOCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define R18 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define ROMOE_DESC SIG_DESC_SET(SCU8C, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) SIG_EXPR_LIST_DECL_SINGLE(R18, GPIOS4, GPIOS4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) SIG_EXPR_DECL_SINGLE(ROMOE, ROM8, ROMOE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) SIG_EXPR_DECL_SINGLE(ROMOE, ROM16, ROMOE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) SIG_EXPR_DECL_SINGLE(ROMOE, ROM16S, ROMOE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) SIG_EXPR_LIST_DECL(ROMOE, ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) SIG_EXPR_PTR(ROMOE, ROM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) SIG_EXPR_PTR(ROMOE, ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) SIG_EXPR_PTR(ROMOE, ROM16S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) SIG_EXPR_LIST_ALIAS(R18, ROMOE, ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PIN_DECL_(R18, SIG_EXPR_LIST_PTR(R18, ROMOE), SIG_EXPR_LIST_PTR(R18, GPIOS4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define N21 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define ROMWE_DESC SIG_DESC_SET(SCU8C, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) SIG_EXPR_LIST_DECL_SINGLE(N21, GPIOS5, GPIOS5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) SIG_EXPR_DECL_SINGLE(ROMWE, ROM8, ROMWE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) SIG_EXPR_DECL_SINGLE(ROMWE, ROM16, ROMWE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) SIG_EXPR_DECL_SINGLE(ROMWE, ROM16S, ROMWE_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) SIG_EXPR_LIST_DECL(ROMWE, ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) SIG_EXPR_PTR(ROMWE, ROM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) SIG_EXPR_PTR(ROMWE, ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) SIG_EXPR_PTR(ROMWE, ROM16S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) SIG_EXPR_LIST_ALIAS(N21, ROMWE, ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PIN_DECL_(N21, SIG_EXPR_LIST_PTR(N21, ROMWE), SIG_EXPR_LIST_PTR(N21, GPIOS5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define L22 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define L22_DESC SIG_DESC_SET(SCU8C, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) SIG_EXPR_DECL_SINGLE(ROMA22, ROM8, L22_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) SIG_EXPR_DECL_SINGLE(ROMA22, ROM16, L22_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) SIG_EXPR_DECL_SINGLE(ROMA22, ROM16S, L22_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) SIG_EXPR_LIST_DECL(ROMA22, ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) SIG_EXPR_PTR(ROMA22, ROM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) SIG_EXPR_PTR(ROMA22, ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) SIG_EXPR_PTR(ROMA22, ROM16S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) SIG_EXPR_LIST_ALIAS(L22, ROMA22, ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) SIG_EXPR_LIST_DECL_SINGLE(L22, VPOR4, VPO24, L22_DESC, VPO_24_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PIN_DECL_2(L22, GPIOS6, ROMA22, VPOR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define K18 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define K18_DESC SIG_DESC_SET(SCU8C, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) SIG_EXPR_DECL_SINGLE(ROMA23, ROM8, K18_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) SIG_EXPR_DECL_SINGLE(ROMA23, ROM16, K18_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) SIG_EXPR_DECL_SINGLE(ROMA23, ROM16S, K18_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) SIG_EXPR_LIST_DECL(ROMA23, ROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) SIG_EXPR_PTR(ROMA23, ROM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) SIG_EXPR_PTR(ROMA23, ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) SIG_EXPR_PTR(ROMA23, ROM16S));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) SIG_EXPR_LIST_ALIAS(K18, ROMA23, ROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) SIG_EXPR_LIST_DECL_SINGLE(K18, VPOR5, VPO24, K18_DESC, VPO_24_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) PIN_DECL_2(K18, GPIOS7, ROMA23, VPOR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define A12 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) SIG_EXPR_LIST_DECL_SINGLE(A12, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) SIG_EXPR_LIST_DECL_SINGLE(A12, RMII1TXEN, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) SIG_EXPR_LIST_DECL_SINGLE(A12, RGMII1TXCK, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PIN_DECL_(A12, SIG_EXPR_LIST_PTR(A12, GPIOT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) SIG_EXPR_LIST_PTR(A12, RMII1TXEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) SIG_EXPR_LIST_PTR(A12, RGMII1TXCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define B12 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) SIG_EXPR_LIST_DECL_SINGLE(B12, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) SIG_EXPR_LIST_DECL_SINGLE(B12, DASHB12, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) SIG_EXPR_LIST_DECL_SINGLE(B12, RGMII1TXCTL, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) PIN_DECL_(B12, SIG_EXPR_LIST_PTR(B12, GPIOT1), SIG_EXPR_LIST_PTR(B12, DASHB12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) SIG_EXPR_LIST_PTR(B12, RGMII1TXCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define C12 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) SIG_EXPR_LIST_DECL_SINGLE(C12, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) SIG_EXPR_LIST_DECL_SINGLE(C12, RMII1TXD0, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) SIG_EXPR_LIST_DECL_SINGLE(C12, RGMII1TXD0, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PIN_DECL_(C12, SIG_EXPR_LIST_PTR(C12, GPIOT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) SIG_EXPR_LIST_PTR(C12, RMII1TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) SIG_EXPR_LIST_PTR(C12, RGMII1TXD0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define D12 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) SIG_EXPR_LIST_DECL_SINGLE(D12, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) SIG_EXPR_LIST_DECL_SINGLE(D12, RMII1TXD1, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) SIG_EXPR_LIST_DECL_SINGLE(D12, RGMII1TXD1, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) PIN_DECL_(D12, SIG_EXPR_LIST_PTR(D12, GPIOT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) SIG_EXPR_LIST_PTR(D12, RMII1TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) SIG_EXPR_LIST_PTR(D12, RGMII1TXD1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define E12 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) SIG_EXPR_LIST_DECL_SINGLE(E12, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) SIG_EXPR_LIST_DECL_SINGLE(E12, DASHE12, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) SIG_EXPR_LIST_DECL_SINGLE(E12, RGMII1TXD2, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) PIN_DECL_(E12, SIG_EXPR_LIST_PTR(E12, GPIOT4), SIG_EXPR_LIST_PTR(E12, DASHE12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) SIG_EXPR_LIST_PTR(E12, RGMII1TXD2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define A13 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) SIG_EXPR_LIST_DECL_SINGLE(A13, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) SIG_EXPR_LIST_DECL_SINGLE(A13, DASHA13, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) SIG_EXPR_LIST_DECL_SINGLE(A13, RGMII1TXD3, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) PIN_DECL_(A13, SIG_EXPR_LIST_PTR(A13, GPIOT5), SIG_EXPR_LIST_PTR(A13, DASHA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) SIG_EXPR_LIST_PTR(A13, RGMII1TXD3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define D9 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) SIG_EXPR_LIST_DECL_SINGLE(D9, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) SIG_EXPR_LIST_DECL_SINGLE(D9, RMII2TXEN, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) SIG_EXPR_LIST_DECL_SINGLE(D9, RGMII2TXCK, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) PIN_DECL_(D9, SIG_EXPR_LIST_PTR(D9, GPIOT6), SIG_EXPR_LIST_PTR(D9, RMII2TXEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) SIG_EXPR_LIST_PTR(D9, RGMII2TXCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define E9 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) SIG_EXPR_LIST_DECL_SINGLE(E9, DASHE9, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII2TXCTL, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT7), SIG_EXPR_LIST_PTR(E9, DASHE9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) SIG_EXPR_LIST_PTR(E9, RGMII2TXCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define A10 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) SIG_EXPR_LIST_DECL_SINGLE(A10, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) SIG_EXPR_LIST_DECL_SINGLE(A10, RMII2TXD0, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) SIG_EXPR_LIST_DECL_SINGLE(A10, RGMII2TXD0, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PIN_DECL_(A10, SIG_EXPR_LIST_PTR(A10, GPIOU0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) SIG_EXPR_LIST_PTR(A10, RMII2TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) SIG_EXPR_LIST_PTR(A10, RGMII2TXD0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define B10 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) SIG_EXPR_LIST_DECL_SINGLE(B10, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) SIG_EXPR_LIST_DECL_SINGLE(B10, RMII2TXD1, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) SIG_EXPR_LIST_DECL_SINGLE(B10, RGMII2TXD1, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) PIN_DECL_(B10, SIG_EXPR_LIST_PTR(B10, GPIOU1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) SIG_EXPR_LIST_PTR(B10, RMII2TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) SIG_EXPR_LIST_PTR(B10, RGMII2TXD1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define C10 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) SIG_EXPR_LIST_DECL_SINGLE(C10, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) SIG_EXPR_LIST_DECL_SINGLE(C10, DASHC10, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) SIG_EXPR_LIST_DECL_SINGLE(C10, RGMII2TXD2, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) PIN_DECL_(C10, SIG_EXPR_LIST_PTR(C10, GPIOU2), SIG_EXPR_LIST_PTR(C10, DASHC10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) SIG_EXPR_LIST_PTR(C10, RGMII2TXD2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define D10 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) SIG_EXPR_LIST_DECL_SINGLE(D10, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) SIG_EXPR_LIST_DECL_SINGLE(D10, DASHD10, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) SIG_EXPR_LIST_DECL_SINGLE(D10, RGMII2TXD3, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) PIN_DECL_(D10, SIG_EXPR_LIST_PTR(D10, GPIOU3), SIG_EXPR_LIST_PTR(D10, DASHD10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) SIG_EXPR_LIST_PTR(D10, RGMII2TXD3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define E11 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) SIG_EXPR_LIST_DECL_SINGLE(E11, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) SIG_EXPR_LIST_DECL_SINGLE(E11, RMII1RCLK, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) SIG_EXPR_LIST_DECL_SINGLE(E11, RGMII1RXCK, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) PIN_DECL_(E11, SIG_EXPR_LIST_PTR(E11, GPIOU4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) SIG_EXPR_LIST_PTR(E11, RMII1RCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) SIG_EXPR_LIST_PTR(E11, RGMII1RXCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define D11 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) SIG_EXPR_LIST_DECL_SINGLE(D11, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) SIG_EXPR_LIST_DECL_SINGLE(D11, DASHD11, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) SIG_EXPR_LIST_DECL_SINGLE(D11, RGMII1RXCTL, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) PIN_DECL_(D11, SIG_EXPR_LIST_PTR(D11, GPIOU5), SIG_EXPR_LIST_PTR(D11, DASHD11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) SIG_EXPR_LIST_PTR(D11, RGMII1RXCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define C11 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) SIG_EXPR_LIST_DECL_SINGLE(C11, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) SIG_EXPR_LIST_DECL_SINGLE(C11, RMII1RXD0, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) SIG_EXPR_LIST_DECL_SINGLE(C11, RGMII1RXD0, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PIN_DECL_(C11, SIG_EXPR_LIST_PTR(C11, GPIOU6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) SIG_EXPR_LIST_PTR(C11, RMII1RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) SIG_EXPR_LIST_PTR(C11, RGMII1RXD0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define B11 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) SIG_EXPR_LIST_DECL_SINGLE(B11, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) SIG_EXPR_LIST_DECL_SINGLE(B11, RMII1RXD1, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) SIG_EXPR_LIST_DECL_SINGLE(B11, RGMII1RXD1, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) PIN_DECL_(B11, SIG_EXPR_LIST_PTR(B11, GPIOU7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) SIG_EXPR_LIST_PTR(B11, RMII1RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) SIG_EXPR_LIST_PTR(B11, RGMII1RXD1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define A11 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) SIG_EXPR_LIST_DECL_SINGLE(A11, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) SIG_EXPR_LIST_DECL_SINGLE(A11, RMII1CRSDV, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) SIG_EXPR_LIST_DECL_SINGLE(A11, RGMII1RXD2, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) PIN_DECL_(A11, SIG_EXPR_LIST_PTR(A11, GPIOV0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) SIG_EXPR_LIST_PTR(A11, RMII1CRSDV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) SIG_EXPR_LIST_PTR(A11, RGMII1RXD2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define E10 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) SIG_EXPR_LIST_DECL_SINGLE(E10, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) SIG_EXPR_LIST_DECL_SINGLE(E10, RMII1RXER, RMII1, RMII1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) SIG_EXPR_LIST_DECL_SINGLE(E10, RGMII1RXD3, RGMII1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) PIN_DECL_(E10, SIG_EXPR_LIST_PTR(E10, GPIOV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) SIG_EXPR_LIST_PTR(E10, RMII1RXER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) SIG_EXPR_LIST_PTR(E10, RGMII1RXD3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define C9 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) SIG_EXPR_LIST_DECL_SINGLE(C9, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) SIG_EXPR_LIST_DECL_SINGLE(C9, RMII2RCLK, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) SIG_EXPR_LIST_DECL_SINGLE(C9, RGMII2RXCK, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) PIN_DECL_(C9, SIG_EXPR_LIST_PTR(C9, GPIOV2), SIG_EXPR_LIST_PTR(C9, RMII2RCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) SIG_EXPR_LIST_PTR(C9, RGMII2RXCK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define B9 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) SIG_EXPR_LIST_DECL_SINGLE(B9, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) SIG_EXPR_LIST_DECL_SINGLE(B9, DASHB9, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) SIG_EXPR_LIST_DECL_SINGLE(B9, RGMII2RXCTL, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) PIN_DECL_(B9, SIG_EXPR_LIST_PTR(B9, GPIOV3), SIG_EXPR_LIST_PTR(B9, DASHB9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) SIG_EXPR_LIST_PTR(B9, RGMII2RXCTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define A9 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) SIG_EXPR_LIST_DECL_SINGLE(A9, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) SIG_EXPR_LIST_DECL_SINGLE(A9, RMII2RXD0, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) SIG_EXPR_LIST_DECL_SINGLE(A9, RGMII2RXD0, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) PIN_DECL_(A9, SIG_EXPR_LIST_PTR(A9, GPIOV4), SIG_EXPR_LIST_PTR(A9, RMII2RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) SIG_EXPR_LIST_PTR(A9, RGMII2RXD0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define E8 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) SIG_EXPR_LIST_DECL_SINGLE(E8, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) SIG_EXPR_LIST_DECL_SINGLE(E8, RMII2RXD1, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) SIG_EXPR_LIST_DECL_SINGLE(E8, RGMII2RXD1, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) PIN_DECL_(E8, SIG_EXPR_LIST_PTR(E8, GPIOV5), SIG_EXPR_LIST_PTR(E8, RMII2RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) SIG_EXPR_LIST_PTR(E8, RGMII2RXD1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define D8 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) SIG_EXPR_LIST_DECL_SINGLE(D8, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) SIG_EXPR_LIST_DECL_SINGLE(D8, RMII2CRSDV, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) SIG_EXPR_LIST_DECL_SINGLE(D8, RGMII2RXD2, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) PIN_DECL_(D8, SIG_EXPR_LIST_PTR(D8, GPIOV6), SIG_EXPR_LIST_PTR(D8, RMII2CRSDV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) SIG_EXPR_LIST_PTR(D8, RGMII2RXD2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define C8 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) SIG_EXPR_LIST_DECL_SINGLE(C8, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) SIG_EXPR_LIST_DECL_SINGLE(C8, RMII2RXER, RMII2, RMII2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) SIG_EXPR_LIST_DECL_SINGLE(C8, RGMII2RXD3, RGMII2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) PIN_DECL_(C8, SIG_EXPR_LIST_PTR(C8, GPIOV7), SIG_EXPR_LIST_PTR(C8, RMII2RXER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) SIG_EXPR_LIST_PTR(C8, RGMII2RXD3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) E10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) E10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) FUNC_GROUP_DECL(RMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) FUNC_GROUP_DECL(RGMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define L5 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) SIG_EXPR_LIST_DECL_SINGLE(L5, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) SIG_EXPR_LIST_DECL_SINGLE(L5, ADC0, ADC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) PIN_DECL_(L5, SIG_EXPR_LIST_PTR(L5, GPIOW0), SIG_EXPR_LIST_PTR(L5, ADC0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) FUNC_GROUP_DECL(ADC0, L5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define L4 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) SIG_EXPR_LIST_DECL_SINGLE(L4, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) SIG_EXPR_LIST_DECL_SINGLE(L4, ADC1, ADC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) PIN_DECL_(L4, SIG_EXPR_LIST_PTR(L4, GPIOW1), SIG_EXPR_LIST_PTR(L4, ADC1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) FUNC_GROUP_DECL(ADC1, L4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define L3 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) SIG_EXPR_LIST_DECL_SINGLE(L3, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) SIG_EXPR_LIST_DECL_SINGLE(L3, ADC2, ADC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) PIN_DECL_(L3, SIG_EXPR_LIST_PTR(L3, GPIOW2), SIG_EXPR_LIST_PTR(L3, ADC2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) FUNC_GROUP_DECL(ADC2, L3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define L2 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) SIG_EXPR_LIST_DECL_SINGLE(L2, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) SIG_EXPR_LIST_DECL_SINGLE(L2, ADC3, ADC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) PIN_DECL_(L2, SIG_EXPR_LIST_PTR(L2, GPIOW3), SIG_EXPR_LIST_PTR(L2, ADC3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) FUNC_GROUP_DECL(ADC3, L2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define L1 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) SIG_EXPR_LIST_DECL_SINGLE(L1, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) SIG_EXPR_LIST_DECL_SINGLE(L1, ADC4, ADC4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) PIN_DECL_(L1, SIG_EXPR_LIST_PTR(L1, GPIOW4), SIG_EXPR_LIST_PTR(L1, ADC4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) FUNC_GROUP_DECL(ADC4, L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define M5 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) SIG_EXPR_LIST_DECL_SINGLE(M5, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) SIG_EXPR_LIST_DECL_SINGLE(M5, ADC5, ADC5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) PIN_DECL_(M5, SIG_EXPR_LIST_PTR(M5, GPIOW5), SIG_EXPR_LIST_PTR(M5, ADC5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) FUNC_GROUP_DECL(ADC5, M5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define M4 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) SIG_EXPR_LIST_DECL_SINGLE(M4, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) SIG_EXPR_LIST_DECL_SINGLE(M4, ADC6, ADC6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) PIN_DECL_(M4, SIG_EXPR_LIST_PTR(M4, GPIOW6), SIG_EXPR_LIST_PTR(M4, ADC6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) FUNC_GROUP_DECL(ADC6, M4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define M3 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) SIG_EXPR_LIST_DECL_SINGLE(M3, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) SIG_EXPR_LIST_DECL_SINGLE(M3, ADC7, ADC7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) PIN_DECL_(M3, SIG_EXPR_LIST_PTR(M3, GPIOW7), SIG_EXPR_LIST_PTR(M3, ADC7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) FUNC_GROUP_DECL(ADC7, M3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define M2 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) SIG_EXPR_LIST_DECL_SINGLE(M2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) SIG_EXPR_LIST_DECL_SINGLE(M2, ADC8, ADC8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) PIN_DECL_(M2, SIG_EXPR_LIST_PTR(M2, GPIOX0), SIG_EXPR_LIST_PTR(M2, ADC8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) FUNC_GROUP_DECL(ADC8, M2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define M1 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) SIG_EXPR_LIST_DECL_SINGLE(M1, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) SIG_EXPR_LIST_DECL_SINGLE(M1, ADC9, ADC9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) PIN_DECL_(M1, SIG_EXPR_LIST_PTR(M1, GPIOX1), SIG_EXPR_LIST_PTR(M1, ADC9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) FUNC_GROUP_DECL(ADC9, M1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define N5 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) SIG_EXPR_LIST_DECL_SINGLE(N5, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) SIG_EXPR_LIST_DECL_SINGLE(N5, ADC10, ADC10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) PIN_DECL_(N5, SIG_EXPR_LIST_PTR(N5, GPIOX2), SIG_EXPR_LIST_PTR(N5, ADC10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) FUNC_GROUP_DECL(ADC10, N5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define N4 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) SIG_EXPR_LIST_DECL_SINGLE(N4, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) SIG_EXPR_LIST_DECL_SINGLE(N4, ADC11, ADC11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) PIN_DECL_(N4, SIG_EXPR_LIST_PTR(N4, GPIOX3), SIG_EXPR_LIST_PTR(N4, ADC11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) FUNC_GROUP_DECL(ADC11, N4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #define N3 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) SIG_EXPR_LIST_DECL_SINGLE(N3, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) SIG_EXPR_LIST_DECL_SINGLE(N3, ADC12, ADC12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) PIN_DECL_(N3, SIG_EXPR_LIST_PTR(N3, GPIOX4), SIG_EXPR_LIST_PTR(N3, ADC12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) FUNC_GROUP_DECL(ADC12, N3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define N2 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) SIG_EXPR_LIST_DECL_SINGLE(N2, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) SIG_EXPR_LIST_DECL_SINGLE(N2, ADC13, ADC13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) PIN_DECL_(N2, SIG_EXPR_LIST_PTR(N2, GPIOX5), SIG_EXPR_LIST_PTR(N2, ADC13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) FUNC_GROUP_DECL(ADC13, N2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #define N1 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) SIG_EXPR_LIST_DECL_SINGLE(N1, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) SIG_EXPR_LIST_DECL_SINGLE(N1, ADC14, ADC14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) PIN_DECL_(N1, SIG_EXPR_LIST_PTR(N1, GPIOX6), SIG_EXPR_LIST_PTR(N1, ADC14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) FUNC_GROUP_DECL(ADC14, N1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #define P5 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) SIG_EXPR_LIST_DECL_SINGLE(P5, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) SIG_EXPR_LIST_DECL_SINGLE(P5, ADC15, ADC15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) PIN_DECL_(P5, SIG_EXPR_LIST_PTR(P5, GPIOX7), SIG_EXPR_LIST_PTR(P5, ADC15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) FUNC_GROUP_DECL(ADC15, P5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) #define C21 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) SIG_EXPR_LIST_DECL_DUAL(C21, SIOS3, SIOS3, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) PIN_DECL_1(C21, GPIOY0, SIOS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) FUNC_GROUP_DECL(SIOS3, C21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define F20 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) SIG_EXPR_LIST_DECL_DUAL(F20, SIOS5, SIOS5, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) PIN_DECL_1(F20, GPIOY1, SIOS5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) FUNC_GROUP_DECL(SIOS5, F20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define G20 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) SIG_EXPR_LIST_DECL_DUAL(G20, SIOPWREQ, SIOPWREQ, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) PIN_DECL_1(G20, GPIOY2, SIOPWREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) FUNC_GROUP_DECL(SIOPWREQ, G20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #define K20 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) SIG_EXPR_LIST_DECL_DUAL(K20, SIOONCTRL, SIOONCTRL, ACPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) PIN_DECL_1(K20, GPIOY3, SIOONCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) FUNC_GROUP_DECL(SIOONCTRL, K20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) FUNC_GROUP_DECL(ACPI, B19, A20, D17, A19, C21, F20, G20, K20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define R22 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define R22_DESC SIG_DESC_SET(SCUA4, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) SIG_EXPR_DECL_SINGLE(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) SIG_EXPR_DECL_SINGLE(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) SIG_EXPR_LIST_DECL_DUAL(R22, ROMA2, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) SIG_EXPR_DECL_SINGLE(VPOB0, VPO12, R22_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) SIG_EXPR_DECL_SINGLE(VPOB0, VPO24, R22_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) SIG_EXPR_DECL_SINGLE(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) SIG_EXPR_LIST_DECL(VPOB0, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) SIG_EXPR_PTR(VPOB0, VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) SIG_EXPR_PTR(VPOB0, VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) SIG_EXPR_PTR(VPOB0, VPOOFF1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) SIG_EXPR_LIST_ALIAS(R22, VPOB0, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) PIN_DECL_2(R22, GPIOZ0, ROMA2, VPOB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define P18 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define P18_DESC SIG_DESC_SET(SCUA4, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) SIG_EXPR_DECL_SINGLE(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) SIG_EXPR_DECL_SINGLE(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) SIG_EXPR_LIST_DECL_DUAL(P18, ROMA3, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) SIG_EXPR_DECL_SINGLE(VPOB1, VPO12, P18_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) SIG_EXPR_DECL_SINGLE(VPOB1, VPO24, P18_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) SIG_EXPR_DECL_SINGLE(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) SIG_EXPR_LIST_DECL(VPOB1, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) SIG_EXPR_PTR(VPOB1, VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) SIG_EXPR_PTR(VPOB1, VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) SIG_EXPR_PTR(VPOB1, VPOOFF1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) SIG_EXPR_LIST_ALIAS(P18, VPOB1, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) PIN_DECL_2(P18, GPIOZ1, ROMA3, VPOB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define P19 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #define P19_DESC SIG_DESC_SET(SCUA4, 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) SIG_EXPR_DECL_SINGLE(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) SIG_EXPR_DECL_SINGLE(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) SIG_EXPR_LIST_DECL_DUAL(P19, ROMA4, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) SIG_EXPR_DECL_SINGLE(VPOB2, VPO12, P19_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) SIG_EXPR_DECL_SINGLE(VPOB2, VPO24, P19_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) SIG_EXPR_LIST_DECL(VPOB2, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) SIG_EXPR_PTR(VPOB2, VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) SIG_EXPR_PTR(VPOB2, VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) SIG_EXPR_PTR(VPOB2, VPOOFF1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) SIG_EXPR_LIST_ALIAS(P19, VPOB2, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) PIN_DECL_2(P19, GPIOZ2, ROMA4, VPOB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define P20 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define P20_DESC SIG_DESC_SET(SCUA4, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) SIG_EXPR_DECL_SINGLE(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) SIG_EXPR_DECL_SINGLE(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) SIG_EXPR_LIST_DECL_DUAL(P20, ROMA5, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) SIG_EXPR_DECL_SINGLE(VPOB3, VPO12, P20_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) SIG_EXPR_DECL_SINGLE(VPOB3, VPO24, P20_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) SIG_EXPR_LIST_DECL(VPOB3, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) SIG_EXPR_PTR(VPOB3, VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) SIG_EXPR_PTR(VPOB3, VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) SIG_EXPR_PTR(VPOB3, VPOOFF1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) SIG_EXPR_LIST_ALIAS(P20, VPOB3, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) PIN_DECL_2(P20, GPIOZ3, ROMA5, VPOB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) #define P21 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) #define P21_DESC SIG_DESC_SET(SCUA4, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) SIG_EXPR_DECL_SINGLE(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) SIG_EXPR_DECL_SINGLE(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) SIG_EXPR_LIST_DECL_DUAL(P21, ROMA6, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) SIG_EXPR_DECL_SINGLE(VPOB4, VPO12, P21_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) SIG_EXPR_DECL_SINGLE(VPOB4, VPO24, P21_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) SIG_EXPR_LIST_DECL(VPOB4, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) SIG_EXPR_PTR(VPOB4, VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) SIG_EXPR_PTR(VPOB4, VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) SIG_EXPR_PTR(VPOB4, VPOOFF1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) SIG_EXPR_LIST_ALIAS(P21, VPOB4, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) PIN_DECL_2(P21, GPIOZ4, ROMA6, VPOB4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #define P22 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) #define P22_DESC SIG_DESC_SET(SCUA4, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) SIG_EXPR_DECL_SINGLE(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) SIG_EXPR_DECL_SINGLE(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) SIG_EXPR_LIST_DECL_DUAL(P22, ROMA7, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) SIG_EXPR_DECL_SINGLE(VPOB5, VPO12, P22_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) SIG_EXPR_DECL_SINGLE(VPOB5, VPO24, P22_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) SIG_EXPR_LIST_DECL(VPOB5, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) SIG_EXPR_PTR(VPOB5, VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) SIG_EXPR_PTR(VPOB5, VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) SIG_EXPR_PTR(VPOB5, VPOOFF1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) SIG_EXPR_LIST_ALIAS(P22, VPOB5, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) PIN_DECL_2(P22, GPIOZ5, ROMA7, VPOB5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) #define M19 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #define M19_DESC SIG_DESC_SET(SCUA4, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) SIG_EXPR_DECL_SINGLE(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) SIG_EXPR_DECL_SINGLE(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) SIG_EXPR_LIST_DECL_DUAL(M19, ROMA8, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) SIG_EXPR_DECL_SINGLE(VPOB6, VPO12, M19_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) SIG_EXPR_DECL_SINGLE(VPOB6, VPO24, M19_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) SIG_EXPR_LIST_DECL(VPOB6, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) SIG_EXPR_PTR(VPOB6, VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) SIG_EXPR_PTR(VPOB6, VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) SIG_EXPR_PTR(VPOB6, VPOOFF1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) SIG_EXPR_LIST_ALIAS(M19, VPOB6, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) PIN_DECL_2(M19, GPIOZ6, ROMA8, VPOB6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #define M20 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #define M20_DESC SIG_DESC_SET(SCUA4, 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) SIG_EXPR_DECL_SINGLE(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) SIG_EXPR_DECL_SINGLE(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) SIG_EXPR_LIST_DECL_DUAL(M20, ROMA9, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) SIG_EXPR_DECL_SINGLE(VPOB7, VPO12, M20_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) SIG_EXPR_DECL_SINGLE(VPOB7, VPO24, M20_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) SIG_EXPR_LIST_DECL(VPOB7, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) SIG_EXPR_PTR(VPOB7, VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) SIG_EXPR_PTR(VPOB7, VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) SIG_EXPR_PTR(VPOB7, VPOOFF1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) SIG_EXPR_LIST_ALIAS(M20, VPOB7, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) PIN_DECL_2(M20, GPIOZ7, ROMA9, VPOB7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define M21 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define M21_DESC SIG_DESC_SET(SCUA4, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) SIG_EXPR_DECL_SINGLE(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) SIG_EXPR_DECL_SINGLE(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) SIG_EXPR_LIST_DECL_DUAL(M21, ROMA10, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) SIG_EXPR_DECL_SINGLE(VPOG0, VPO12, M21_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) SIG_EXPR_DECL_SINGLE(VPOG0, VPO24, M21_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) SIG_EXPR_DECL_SINGLE(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) SIG_EXPR_LIST_DECL(VPOG0, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) SIG_EXPR_PTR(VPOG0, VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) SIG_EXPR_PTR(VPOG0, VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) SIG_EXPR_PTR(VPOG0, VPOOFF1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) SIG_EXPR_LIST_ALIAS(M21, VPOG0, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) PIN_DECL_2(M21, GPIOAA0, ROMA10, VPOG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) #define M22 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) #define M22_DESC SIG_DESC_SET(SCUA4, 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) SIG_EXPR_DECL_SINGLE(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) SIG_EXPR_DECL_SINGLE(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) SIG_EXPR_LIST_DECL_DUAL(M22, ROMA11, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) SIG_EXPR_DECL_SINGLE(VPOG1, VPO12, M22_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) SIG_EXPR_DECL_SINGLE(VPOG1, VPO24, M22_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) SIG_EXPR_DECL_SINGLE(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) SIG_EXPR_LIST_DECL(VPOG1, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) SIG_EXPR_PTR(VPOG1, VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) SIG_EXPR_PTR(VPOG1, VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) SIG_EXPR_PTR(VPOG1, VPOOFF1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) SIG_EXPR_LIST_ALIAS(M22, VPOG1, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) PIN_DECL_2(M22, GPIOAA1, ROMA11, VPOG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #define L18 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #define L18_DESC SIG_DESC_SET(SCUA4, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) SIG_EXPR_DECL_SINGLE(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) SIG_EXPR_DECL_SINGLE(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) SIG_EXPR_LIST_DECL_DUAL(L18, ROMA12, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) SIG_EXPR_DECL_SINGLE(VPOG2, VPO12, L18_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) SIG_EXPR_DECL_SINGLE(VPOG2, VPO24, L18_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) SIG_EXPR_LIST_DECL(VPOG2, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) SIG_EXPR_PTR(VPOG2, VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) SIG_EXPR_PTR(VPOG2, VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) SIG_EXPR_PTR(VPOG2, VPOOFF1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) SIG_EXPR_LIST_ALIAS(L18, VPOG2, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) PIN_DECL_2(L18, GPIOAA2, ROMA12, VPOG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #define L19 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #define L19_DESC SIG_DESC_SET(SCUA4, 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) SIG_EXPR_DECL_SINGLE(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) SIG_EXPR_DECL_SINGLE(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) SIG_EXPR_LIST_DECL_DUAL(L19, ROMA13, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) SIG_EXPR_DECL_SINGLE(VPOG3, VPO12, L19_DESC, VPO12_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) SIG_EXPR_DECL_SINGLE(VPOG3, VPO24, L19_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) SIG_EXPR_LIST_DECL(VPOG3, VPO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) SIG_EXPR_PTR(VPOG3, VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) SIG_EXPR_PTR(VPOG3, VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) SIG_EXPR_PTR(VPOG3, VPOOFF1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) SIG_EXPR_LIST_ALIAS(L19, VPOG3, VPO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) PIN_DECL_2(L19, GPIOAA3, ROMA13, VPOG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define L20 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define L20_DESC SIG_DESC_SET(SCUA4, 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) SIG_EXPR_DECL_SINGLE(ROMA14, ROM8, L20_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) SIG_EXPR_DECL_SINGLE(ROMA14, ROM16, L20_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) SIG_EXPR_LIST_DECL_DUAL(L20, ROMA14, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) SIG_EXPR_DECL_SINGLE(VPOG4, VPO24, L20_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) SIG_EXPR_LIST_DECL_DUAL(L20, VPOG4, VPO24, VPOOFF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) PIN_DECL_2(L20, GPIOAA4, ROMA14, VPOG4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define L21 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #define L21_DESC SIG_DESC_SET(SCUA4, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) SIG_EXPR_DECL_SINGLE(ROMA15, ROM8, L21_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) SIG_EXPR_DECL_SINGLE(ROMA15, ROM16, L21_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) SIG_EXPR_LIST_DECL_DUAL(L21, ROMA15, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) SIG_EXPR_DECL_SINGLE(VPOG5, VPO24, L21_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) SIG_EXPR_LIST_DECL_DUAL(L21, VPOG5, VPO24, VPOOFF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) PIN_DECL_2(L21, GPIOAA5, ROMA15, VPOG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #define T18 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) #define T18_DESC SIG_DESC_SET(SCUA4, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) SIG_EXPR_DECL_SINGLE(ROMA16, ROM8, T18_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) SIG_EXPR_DECL_SINGLE(ROMA16, ROM16, T18_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) SIG_EXPR_LIST_DECL_DUAL(T18, ROMA16, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) SIG_EXPR_DECL_SINGLE(VPOG6, VPO24, T18_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) SIG_EXPR_LIST_DECL_DUAL(T18, VPOG6, VPO24, VPOOFF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) PIN_DECL_2(T18, GPIOAA6, ROMA16, VPOG6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) #define N18 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #define N18_DESC SIG_DESC_SET(SCUA4, 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) SIG_EXPR_DECL_SINGLE(ROMA17, ROM8, N18_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) SIG_EXPR_DECL_SINGLE(ROMA17, ROM16, N18_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) SIG_EXPR_LIST_DECL_DUAL(N18, ROMA17, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) SIG_EXPR_DECL_SINGLE(VPOG7, VPO24, N18_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) SIG_EXPR_LIST_DECL_DUAL(N18, VPOG7, VPO24, VPOOFF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) PIN_DECL_2(N18, GPIOAA7, ROMA17, VPOG7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define N19 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define N19_DESC SIG_DESC_SET(SCUA8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) SIG_EXPR_DECL_SINGLE(ROMA18, ROM8, N19_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) SIG_EXPR_DECL_SINGLE(ROMA18, ROM16, N19_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) SIG_EXPR_LIST_DECL_DUAL(N19, ROMA18, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) SIG_EXPR_DECL_SINGLE(VPOR0, VPO24, N19_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) SIG_EXPR_DECL_SINGLE(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) SIG_EXPR_LIST_DECL_DUAL(N19, VPOR0, VPO24, VPOOFF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) PIN_DECL_2(N19, GPIOAB0, ROMA18, VPOR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #define M18 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) #define M18_DESC SIG_DESC_SET(SCUA8, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) SIG_EXPR_DECL_SINGLE(ROMA19, ROM8, M18_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) SIG_EXPR_DECL_SINGLE(ROMA19, ROM16, M18_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) SIG_EXPR_LIST_DECL_DUAL(M18, ROMA19, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) SIG_EXPR_DECL_SINGLE(VPOR1, VPO24, M18_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) SIG_EXPR_DECL_SINGLE(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) SIG_EXPR_LIST_DECL_DUAL(M18, VPOR1, VPO24, VPOOFF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) PIN_DECL_2(M18, GPIOAB1, ROMA19, VPOR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) #define N22 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #define N22_DESC SIG_DESC_SET(SCUA8, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) SIG_EXPR_DECL_SINGLE(ROMA20, ROM8, N22_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) SIG_EXPR_DECL_SINGLE(ROMA20, ROM16, N22_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) SIG_EXPR_LIST_DECL_DUAL(N22, ROMA20, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) SIG_EXPR_DECL_SINGLE(VPOR2, VPO24, N22_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) SIG_EXPR_LIST_DECL_DUAL(N22, VPOR2, VPO24, VPOOFF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) PIN_DECL_2(N22, GPIOAB2, ROMA20, VPOR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #define N20 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define N20_DESC SIG_DESC_SET(SCUA8, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) SIG_EXPR_DECL_SINGLE(ROMA21, ROM8, N20_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) SIG_EXPR_DECL_SINGLE(ROMA21, ROM16, N20_DESC, VPO_OFF_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) SIG_EXPR_LIST_DECL_DUAL(N20, ROMA21, ROM8, ROM16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) SIG_EXPR_DECL_SINGLE(VPOR3, VPO24, N20_DESC, VPO24_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) SIG_EXPR_LIST_DECL_DUAL(N20, VPOR3, VPO24, VPOOFF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) PIN_DECL_2(N20, GPIOAB3, ROMA21, VPOR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) U19, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) L19, L20, L21, T18, N18, N19, M18, N22, N20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19, R22, P18, P19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) P20, P21, P22, M19, M20, M21, M22, L18, L19, L20, L21, T18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) N18, N19, M18, N22, N20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) M20, M21, M22, L18, L19, L20, L21, T18, N18, N19, M18, N22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) N20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) P20, P21, P22, M19, M20, M21, M22, L18, L19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #define USB11H2_DESC SIG_DESC_SET(SCU90, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #define USB11D1_DESC SIG_DESC_BIT(SCU90, 3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) #define K4 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) SIG_EXPR_LIST_DECL_SINGLE(K4, USB11HDP2, USB11H2, USB11H2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) SIG_EXPR_LIST_DECL_SINGLE(K4, USB11DP1, USB11D1, USB11D1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) PIN_DECL_(K4, SIG_EXPR_LIST_PTR(K4, USB11HDP2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) SIG_EXPR_LIST_PTR(K4, USB11DP1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #define K3 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) SIG_EXPR_LIST_DECL_SINGLE(K3, USB11HDN1, USB11H2, USB11H2_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) SIG_EXPR_LIST_DECL_SINGLE(K3, USB11DDN1, USB11D1, USB11D1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) PIN_DECL_(K3, SIG_EXPR_LIST_PTR(K3, USB11HDN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) SIG_EXPR_LIST_PTR(K3, USB11DDN1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) FUNC_GROUP_DECL(USB11H2, K4, K3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) FUNC_GROUP_DECL(USB11D1, K4, K3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #define USB2H1_DESC SIG_DESC_SET(SCU90, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define USB2D1_DESC SIG_DESC_BIT(SCU90, 29, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define AB21 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) SIG_EXPR_LIST_DECL_SINGLE(AB21, USB2HDP1, USB2H1, USB2H1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) SIG_EXPR_LIST_DECL_SINGLE(AB21, USB2DDP1, USB2D1, USB2D1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, USB2HDP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) SIG_EXPR_LIST_PTR(AB21, USB2DDP1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) #define AB20 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) SIG_EXPR_LIST_DECL_SINGLE(AB20, USB2HDN1, USB2H1, USB2H1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) SIG_EXPR_LIST_DECL_SINGLE(AB20, USB2DDN1, USB2D1, USB2D1_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, USB2HDN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) SIG_EXPR_LIST_PTR(AB20, USB2DDN1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) FUNC_GROUP_DECL(USB2H1, AB21, AB20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) FUNC_GROUP_DECL(USB2D1, AB21, AB20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) * pins becomes 220. Four additional non-GPIO-capable pins are present for USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define ASPEED_G4_NR_PINS 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) /* Pins, groups and functions are sort(1):ed alphabetically for sanity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) ASPEED_PINCTRL_PIN(A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) ASPEED_PINCTRL_PIN(A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) ASPEED_PINCTRL_PIN(A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) ASPEED_PINCTRL_PIN(A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) ASPEED_PINCTRL_PIN(A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ASPEED_PINCTRL_PIN(A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) ASPEED_PINCTRL_PIN(A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ASPEED_PINCTRL_PIN(A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) ASPEED_PINCTRL_PIN(A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) ASPEED_PINCTRL_PIN(A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) ASPEED_PINCTRL_PIN(A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) ASPEED_PINCTRL_PIN(A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) ASPEED_PINCTRL_PIN(A20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ASPEED_PINCTRL_PIN(A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) ASPEED_PINCTRL_PIN(A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ASPEED_PINCTRL_PIN(A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) ASPEED_PINCTRL_PIN(A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) ASPEED_PINCTRL_PIN(A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ASPEED_PINCTRL_PIN(A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) ASPEED_PINCTRL_PIN(A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) ASPEED_PINCTRL_PIN(AA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) ASPEED_PINCTRL_PIN(AA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) ASPEED_PINCTRL_PIN(AA22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) ASPEED_PINCTRL_PIN(AA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ASPEED_PINCTRL_PIN(AA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) ASPEED_PINCTRL_PIN(AA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) ASPEED_PINCTRL_PIN(AA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) ASPEED_PINCTRL_PIN(AA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) ASPEED_PINCTRL_PIN(AB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) ASPEED_PINCTRL_PIN(AB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) ASPEED_PINCTRL_PIN(AB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) ASPEED_PINCTRL_PIN(AB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) ASPEED_PINCTRL_PIN(AB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) ASPEED_PINCTRL_PIN(AB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) ASPEED_PINCTRL_PIN(AB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ASPEED_PINCTRL_PIN(AB20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) ASPEED_PINCTRL_PIN(AB21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) ASPEED_PINCTRL_PIN(B1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) ASPEED_PINCTRL_PIN(B10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) ASPEED_PINCTRL_PIN(B11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) ASPEED_PINCTRL_PIN(B12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) ASPEED_PINCTRL_PIN(B13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) ASPEED_PINCTRL_PIN(B14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) ASPEED_PINCTRL_PIN(B15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) ASPEED_PINCTRL_PIN(B16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) ASPEED_PINCTRL_PIN(B17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) ASPEED_PINCTRL_PIN(B18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) ASPEED_PINCTRL_PIN(B19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) ASPEED_PINCTRL_PIN(B2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) ASPEED_PINCTRL_PIN(B22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) ASPEED_PINCTRL_PIN(B3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) ASPEED_PINCTRL_PIN(B4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) ASPEED_PINCTRL_PIN(B5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) ASPEED_PINCTRL_PIN(B6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ASPEED_PINCTRL_PIN(B7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) ASPEED_PINCTRL_PIN(B9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) ASPEED_PINCTRL_PIN(C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) ASPEED_PINCTRL_PIN(C10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ASPEED_PINCTRL_PIN(C11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) ASPEED_PINCTRL_PIN(C12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) ASPEED_PINCTRL_PIN(C13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) ASPEED_PINCTRL_PIN(C14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ASPEED_PINCTRL_PIN(C15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) ASPEED_PINCTRL_PIN(C16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) ASPEED_PINCTRL_PIN(C17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) ASPEED_PINCTRL_PIN(C18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) ASPEED_PINCTRL_PIN(C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) ASPEED_PINCTRL_PIN(C20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) ASPEED_PINCTRL_PIN(C21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ASPEED_PINCTRL_PIN(C22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) ASPEED_PINCTRL_PIN(C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) ASPEED_PINCTRL_PIN(C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) ASPEED_PINCTRL_PIN(C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ASPEED_PINCTRL_PIN(C6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) ASPEED_PINCTRL_PIN(C7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) ASPEED_PINCTRL_PIN(C8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) ASPEED_PINCTRL_PIN(C9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) ASPEED_PINCTRL_PIN(D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) ASPEED_PINCTRL_PIN(D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) ASPEED_PINCTRL_PIN(D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) ASPEED_PINCTRL_PIN(D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ASPEED_PINCTRL_PIN(D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) ASPEED_PINCTRL_PIN(D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) ASPEED_PINCTRL_PIN(D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) ASPEED_PINCTRL_PIN(D16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) ASPEED_PINCTRL_PIN(D17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) ASPEED_PINCTRL_PIN(D18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ASPEED_PINCTRL_PIN(D19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) ASPEED_PINCTRL_PIN(D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) ASPEED_PINCTRL_PIN(D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) ASPEED_PINCTRL_PIN(D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) ASPEED_PINCTRL_PIN(D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) ASPEED_PINCTRL_PIN(D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) ASPEED_PINCTRL_PIN(D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) ASPEED_PINCTRL_PIN(D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) ASPEED_PINCTRL_PIN(D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) ASPEED_PINCTRL_PIN(E10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) ASPEED_PINCTRL_PIN(E11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) ASPEED_PINCTRL_PIN(E12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) ASPEED_PINCTRL_PIN(E13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) ASPEED_PINCTRL_PIN(E14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) ASPEED_PINCTRL_PIN(E15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) ASPEED_PINCTRL_PIN(E16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) ASPEED_PINCTRL_PIN(E18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) ASPEED_PINCTRL_PIN(E19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) ASPEED_PINCTRL_PIN(E2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) ASPEED_PINCTRL_PIN(E20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) ASPEED_PINCTRL_PIN(E3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) ASPEED_PINCTRL_PIN(E5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) ASPEED_PINCTRL_PIN(E6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) ASPEED_PINCTRL_PIN(E7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) ASPEED_PINCTRL_PIN(E8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) ASPEED_PINCTRL_PIN(E9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) ASPEED_PINCTRL_PIN(F18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) ASPEED_PINCTRL_PIN(F20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ASPEED_PINCTRL_PIN(F3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) ASPEED_PINCTRL_PIN(F4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) ASPEED_PINCTRL_PIN(F5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ASPEED_PINCTRL_PIN(G18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) ASPEED_PINCTRL_PIN(G19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) ASPEED_PINCTRL_PIN(G20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) ASPEED_PINCTRL_PIN(G5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) ASPEED_PINCTRL_PIN(H1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) ASPEED_PINCTRL_PIN(H18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) ASPEED_PINCTRL_PIN(H19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) ASPEED_PINCTRL_PIN(H2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) ASPEED_PINCTRL_PIN(H20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) ASPEED_PINCTRL_PIN(H3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) ASPEED_PINCTRL_PIN(H4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) ASPEED_PINCTRL_PIN(J20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) ASPEED_PINCTRL_PIN(J21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) ASPEED_PINCTRL_PIN(J3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) ASPEED_PINCTRL_PIN(J4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) ASPEED_PINCTRL_PIN(J5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) ASPEED_PINCTRL_PIN(K18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) ASPEED_PINCTRL_PIN(K20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) ASPEED_PINCTRL_PIN(K3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) ASPEED_PINCTRL_PIN(K4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) ASPEED_PINCTRL_PIN(K5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) ASPEED_PINCTRL_PIN(L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) ASPEED_PINCTRL_PIN(L18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) ASPEED_PINCTRL_PIN(L19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) ASPEED_PINCTRL_PIN(L2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) ASPEED_PINCTRL_PIN(L20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ASPEED_PINCTRL_PIN(L21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) ASPEED_PINCTRL_PIN(L22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) ASPEED_PINCTRL_PIN(L3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) ASPEED_PINCTRL_PIN(L4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) ASPEED_PINCTRL_PIN(L5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) ASPEED_PINCTRL_PIN(M1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) ASPEED_PINCTRL_PIN(M18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) ASPEED_PINCTRL_PIN(M19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) ASPEED_PINCTRL_PIN(M2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) ASPEED_PINCTRL_PIN(M20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) ASPEED_PINCTRL_PIN(M21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) ASPEED_PINCTRL_PIN(M22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) ASPEED_PINCTRL_PIN(M3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) ASPEED_PINCTRL_PIN(M4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ASPEED_PINCTRL_PIN(M5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) ASPEED_PINCTRL_PIN(N1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) ASPEED_PINCTRL_PIN(N18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) ASPEED_PINCTRL_PIN(N19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) ASPEED_PINCTRL_PIN(N2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) ASPEED_PINCTRL_PIN(N20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ASPEED_PINCTRL_PIN(N21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) ASPEED_PINCTRL_PIN(N22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) ASPEED_PINCTRL_PIN(N3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) ASPEED_PINCTRL_PIN(N4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) ASPEED_PINCTRL_PIN(N5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) ASPEED_PINCTRL_PIN(P18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) ASPEED_PINCTRL_PIN(P19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) ASPEED_PINCTRL_PIN(P20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) ASPEED_PINCTRL_PIN(P21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) ASPEED_PINCTRL_PIN(P22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) ASPEED_PINCTRL_PIN(P5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) ASPEED_PINCTRL_PIN(R18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) ASPEED_PINCTRL_PIN(R22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) ASPEED_PINCTRL_PIN(T1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) ASPEED_PINCTRL_PIN(T18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) ASPEED_PINCTRL_PIN(T19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) ASPEED_PINCTRL_PIN(T2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) ASPEED_PINCTRL_PIN(T4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) ASPEED_PINCTRL_PIN(T5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) ASPEED_PINCTRL_PIN(U1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) ASPEED_PINCTRL_PIN(U18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) ASPEED_PINCTRL_PIN(U19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ASPEED_PINCTRL_PIN(U2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) ASPEED_PINCTRL_PIN(U20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) ASPEED_PINCTRL_PIN(U21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) ASPEED_PINCTRL_PIN(U3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ASPEED_PINCTRL_PIN(U4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) ASPEED_PINCTRL_PIN(U5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) ASPEED_PINCTRL_PIN(V1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) ASPEED_PINCTRL_PIN(V2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) ASPEED_PINCTRL_PIN(V20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) ASPEED_PINCTRL_PIN(V21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ASPEED_PINCTRL_PIN(V22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) ASPEED_PINCTRL_PIN(V3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) ASPEED_PINCTRL_PIN(V4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) ASPEED_PINCTRL_PIN(V5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) ASPEED_PINCTRL_PIN(V6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) ASPEED_PINCTRL_PIN(V7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) ASPEED_PINCTRL_PIN(W1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) ASPEED_PINCTRL_PIN(W2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) ASPEED_PINCTRL_PIN(W21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) ASPEED_PINCTRL_PIN(W22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) ASPEED_PINCTRL_PIN(W3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) ASPEED_PINCTRL_PIN(W4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) ASPEED_PINCTRL_PIN(W5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) ASPEED_PINCTRL_PIN(W6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) ASPEED_PINCTRL_PIN(W7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) ASPEED_PINCTRL_PIN(Y1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) ASPEED_PINCTRL_PIN(Y2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) ASPEED_PINCTRL_PIN(Y21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) ASPEED_PINCTRL_PIN(Y22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) ASPEED_PINCTRL_PIN(Y3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) ASPEED_PINCTRL_PIN(Y4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) ASPEED_PINCTRL_PIN(Y5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) ASPEED_PINCTRL_PIN(Y6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) ASPEED_PINCTRL_PIN(Y7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static const struct aspeed_pin_group aspeed_g4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) ASPEED_PINCTRL_GROUP(ACPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) ASPEED_PINCTRL_GROUP(ADC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) ASPEED_PINCTRL_GROUP(ADC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) ASPEED_PINCTRL_GROUP(ADC10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) ASPEED_PINCTRL_GROUP(ADC11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) ASPEED_PINCTRL_GROUP(ADC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) ASPEED_PINCTRL_GROUP(ADC13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) ASPEED_PINCTRL_GROUP(ADC14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) ASPEED_PINCTRL_GROUP(ADC15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) ASPEED_PINCTRL_GROUP(ADC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) ASPEED_PINCTRL_GROUP(ADC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) ASPEED_PINCTRL_GROUP(ADC4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) ASPEED_PINCTRL_GROUP(ADC5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) ASPEED_PINCTRL_GROUP(ADC6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) ASPEED_PINCTRL_GROUP(ADC7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) ASPEED_PINCTRL_GROUP(ADC8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) ASPEED_PINCTRL_GROUP(ADC9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) ASPEED_PINCTRL_GROUP(BMCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) ASPEED_PINCTRL_GROUP(DDCCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) ASPEED_PINCTRL_GROUP(DDCDAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) ASPEED_PINCTRL_GROUP(EXTRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) ASPEED_PINCTRL_GROUP(FLACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) ASPEED_PINCTRL_GROUP(FLBUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) ASPEED_PINCTRL_GROUP(FLWP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) ASPEED_PINCTRL_GROUP(GPID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) ASPEED_PINCTRL_GROUP(GPID0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) ASPEED_PINCTRL_GROUP(GPID2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) ASPEED_PINCTRL_GROUP(GPID4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) ASPEED_PINCTRL_GROUP(GPID6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) ASPEED_PINCTRL_GROUP(GPIE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) ASPEED_PINCTRL_GROUP(GPIE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) ASPEED_PINCTRL_GROUP(GPIE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) ASPEED_PINCTRL_GROUP(GPIE6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) ASPEED_PINCTRL_GROUP(I2C10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) ASPEED_PINCTRL_GROUP(I2C11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) ASPEED_PINCTRL_GROUP(I2C12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) ASPEED_PINCTRL_GROUP(I2C13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) ASPEED_PINCTRL_GROUP(I2C14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) ASPEED_PINCTRL_GROUP(I2C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) ASPEED_PINCTRL_GROUP(I2C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) ASPEED_PINCTRL_GROUP(I2C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) ASPEED_PINCTRL_GROUP(I2C6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) ASPEED_PINCTRL_GROUP(I2C7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) ASPEED_PINCTRL_GROUP(I2C8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) ASPEED_PINCTRL_GROUP(I2C9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) ASPEED_PINCTRL_GROUP(LPCPD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) ASPEED_PINCTRL_GROUP(LPCPME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) ASPEED_PINCTRL_GROUP(LPCRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) ASPEED_PINCTRL_GROUP(LPCSMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) ASPEED_PINCTRL_GROUP(MAC1LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) ASPEED_PINCTRL_GROUP(MAC2LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) ASPEED_PINCTRL_GROUP(MDIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) ASPEED_PINCTRL_GROUP(MDIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) ASPEED_PINCTRL_GROUP(NCTS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) ASPEED_PINCTRL_GROUP(NCTS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) ASPEED_PINCTRL_GROUP(NCTS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) ASPEED_PINCTRL_GROUP(NCTS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) ASPEED_PINCTRL_GROUP(NDCD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) ASPEED_PINCTRL_GROUP(NDCD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) ASPEED_PINCTRL_GROUP(NDCD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) ASPEED_PINCTRL_GROUP(NDCD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) ASPEED_PINCTRL_GROUP(NDSR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) ASPEED_PINCTRL_GROUP(NDSR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) ASPEED_PINCTRL_GROUP(NDSR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) ASPEED_PINCTRL_GROUP(NDSR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) ASPEED_PINCTRL_GROUP(NDTR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) ASPEED_PINCTRL_GROUP(NDTR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) ASPEED_PINCTRL_GROUP(NDTR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) ASPEED_PINCTRL_GROUP(NDTR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) ASPEED_PINCTRL_GROUP(NDTS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) ASPEED_PINCTRL_GROUP(NRI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) ASPEED_PINCTRL_GROUP(NRI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) ASPEED_PINCTRL_GROUP(NRI3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) ASPEED_PINCTRL_GROUP(NRI4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) ASPEED_PINCTRL_GROUP(NRTS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) ASPEED_PINCTRL_GROUP(NRTS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) ASPEED_PINCTRL_GROUP(NRTS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) ASPEED_PINCTRL_GROUP(OSCCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) ASPEED_PINCTRL_GROUP(PWM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) ASPEED_PINCTRL_GROUP(PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) ASPEED_PINCTRL_GROUP(PWM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) ASPEED_PINCTRL_GROUP(PWM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) ASPEED_PINCTRL_GROUP(PWM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) ASPEED_PINCTRL_GROUP(PWM5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) ASPEED_PINCTRL_GROUP(PWM6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) ASPEED_PINCTRL_GROUP(PWM7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) ASPEED_PINCTRL_GROUP(RGMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) ASPEED_PINCTRL_GROUP(RGMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) ASPEED_PINCTRL_GROUP(RMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) ASPEED_PINCTRL_GROUP(RMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) ASPEED_PINCTRL_GROUP(ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) ASPEED_PINCTRL_GROUP(ROM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) ASPEED_PINCTRL_GROUP(ROMCS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) ASPEED_PINCTRL_GROUP(ROMCS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) ASPEED_PINCTRL_GROUP(ROMCS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) ASPEED_PINCTRL_GROUP(ROMCS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) ASPEED_PINCTRL_GROUP(RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) ASPEED_PINCTRL_GROUP(RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) ASPEED_PINCTRL_GROUP(RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) ASPEED_PINCTRL_GROUP(RXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) ASPEED_PINCTRL_GROUP(SALT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) ASPEED_PINCTRL_GROUP(SALT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) ASPEED_PINCTRL_GROUP(SALT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) ASPEED_PINCTRL_GROUP(SALT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) ASPEED_PINCTRL_GROUP(SD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) ASPEED_PINCTRL_GROUP(SD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) ASPEED_PINCTRL_GROUP(SGPMCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) ASPEED_PINCTRL_GROUP(SGPMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) ASPEED_PINCTRL_GROUP(SGPMLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) ASPEED_PINCTRL_GROUP(SGPMO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) ASPEED_PINCTRL_GROUP(SGPSCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) ASPEED_PINCTRL_GROUP(SGPSI0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) ASPEED_PINCTRL_GROUP(SGPSI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) ASPEED_PINCTRL_GROUP(SGPSLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) ASPEED_PINCTRL_GROUP(SIOONCTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) ASPEED_PINCTRL_GROUP(SIOPBI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) ASPEED_PINCTRL_GROUP(SIOPBO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) ASPEED_PINCTRL_GROUP(SIOPWREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) ASPEED_PINCTRL_GROUP(SIOPWRGD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) ASPEED_PINCTRL_GROUP(SIOS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) ASPEED_PINCTRL_GROUP(SIOS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) ASPEED_PINCTRL_GROUP(SIOSCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) ASPEED_PINCTRL_GROUP(SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) ASPEED_PINCTRL_GROUP(SPI1DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) ASPEED_PINCTRL_GROUP(SPICS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) ASPEED_PINCTRL_GROUP(TIMER3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) ASPEED_PINCTRL_GROUP(TIMER4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) ASPEED_PINCTRL_GROUP(TIMER5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) ASPEED_PINCTRL_GROUP(TIMER6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) ASPEED_PINCTRL_GROUP(TIMER7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) ASPEED_PINCTRL_GROUP(TIMER8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) ASPEED_PINCTRL_GROUP(TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) ASPEED_PINCTRL_GROUP(TXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) ASPEED_PINCTRL_GROUP(TXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) ASPEED_PINCTRL_GROUP(TXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) ASPEED_PINCTRL_GROUP(UART6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) ASPEED_PINCTRL_GROUP(USB11D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) ASPEED_PINCTRL_GROUP(USB11H2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) ASPEED_PINCTRL_GROUP(USB2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) ASPEED_PINCTRL_GROUP(USB2H1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) ASPEED_PINCTRL_GROUP(USBCKI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) ASPEED_PINCTRL_GROUP(VGABIOS_ROM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) ASPEED_PINCTRL_GROUP(VGAHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) ASPEED_PINCTRL_GROUP(VGAVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) ASPEED_PINCTRL_GROUP(VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) ASPEED_PINCTRL_GROUP(VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) ASPEED_PINCTRL_GROUP(VPI30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) ASPEED_PINCTRL_GROUP(VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) ASPEED_PINCTRL_GROUP(VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) ASPEED_PINCTRL_GROUP(WDTRST1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) ASPEED_PINCTRL_GROUP(WDTRST2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) static const struct aspeed_pin_function aspeed_g4_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) ASPEED_PINCTRL_FUNC(ACPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) ASPEED_PINCTRL_FUNC(ADC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) ASPEED_PINCTRL_FUNC(ADC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) ASPEED_PINCTRL_FUNC(ADC10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) ASPEED_PINCTRL_FUNC(ADC11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) ASPEED_PINCTRL_FUNC(ADC12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) ASPEED_PINCTRL_FUNC(ADC13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) ASPEED_PINCTRL_FUNC(ADC14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) ASPEED_PINCTRL_FUNC(ADC15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) ASPEED_PINCTRL_FUNC(ADC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) ASPEED_PINCTRL_FUNC(ADC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) ASPEED_PINCTRL_FUNC(ADC4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) ASPEED_PINCTRL_FUNC(ADC5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) ASPEED_PINCTRL_FUNC(ADC6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) ASPEED_PINCTRL_FUNC(ADC7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) ASPEED_PINCTRL_FUNC(ADC8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) ASPEED_PINCTRL_FUNC(ADC9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) ASPEED_PINCTRL_FUNC(BMCINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) ASPEED_PINCTRL_FUNC(DDCCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) ASPEED_PINCTRL_FUNC(DDCDAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) ASPEED_PINCTRL_FUNC(EXTRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) ASPEED_PINCTRL_FUNC(FLACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) ASPEED_PINCTRL_FUNC(FLBUSY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) ASPEED_PINCTRL_FUNC(FLWP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) ASPEED_PINCTRL_FUNC(GPID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) ASPEED_PINCTRL_FUNC(GPID0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) ASPEED_PINCTRL_FUNC(GPID2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) ASPEED_PINCTRL_FUNC(GPID4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) ASPEED_PINCTRL_FUNC(GPID6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) ASPEED_PINCTRL_FUNC(GPIE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) ASPEED_PINCTRL_FUNC(GPIE2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) ASPEED_PINCTRL_FUNC(GPIE4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) ASPEED_PINCTRL_FUNC(GPIE6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) ASPEED_PINCTRL_FUNC(I2C10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) ASPEED_PINCTRL_FUNC(I2C11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) ASPEED_PINCTRL_FUNC(I2C12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) ASPEED_PINCTRL_FUNC(I2C13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) ASPEED_PINCTRL_FUNC(I2C14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) ASPEED_PINCTRL_FUNC(I2C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) ASPEED_PINCTRL_FUNC(I2C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) ASPEED_PINCTRL_FUNC(I2C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) ASPEED_PINCTRL_FUNC(I2C6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) ASPEED_PINCTRL_FUNC(I2C7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) ASPEED_PINCTRL_FUNC(I2C8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) ASPEED_PINCTRL_FUNC(I2C9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) ASPEED_PINCTRL_FUNC(LPCPD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) ASPEED_PINCTRL_FUNC(LPCPME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) ASPEED_PINCTRL_FUNC(LPCRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) ASPEED_PINCTRL_FUNC(LPCSMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) ASPEED_PINCTRL_FUNC(MAC1LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) ASPEED_PINCTRL_FUNC(MAC2LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) ASPEED_PINCTRL_FUNC(MDIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) ASPEED_PINCTRL_FUNC(MDIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) ASPEED_PINCTRL_FUNC(NCTS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) ASPEED_PINCTRL_FUNC(NCTS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) ASPEED_PINCTRL_FUNC(NCTS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) ASPEED_PINCTRL_FUNC(NCTS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) ASPEED_PINCTRL_FUNC(NDCD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) ASPEED_PINCTRL_FUNC(NDCD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) ASPEED_PINCTRL_FUNC(NDCD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) ASPEED_PINCTRL_FUNC(NDCD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) ASPEED_PINCTRL_FUNC(NDSR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) ASPEED_PINCTRL_FUNC(NDSR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) ASPEED_PINCTRL_FUNC(NDSR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) ASPEED_PINCTRL_FUNC(NDSR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) ASPEED_PINCTRL_FUNC(NDTR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) ASPEED_PINCTRL_FUNC(NDTR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) ASPEED_PINCTRL_FUNC(NDTR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) ASPEED_PINCTRL_FUNC(NDTR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) ASPEED_PINCTRL_FUNC(NDTS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) ASPEED_PINCTRL_FUNC(NRI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) ASPEED_PINCTRL_FUNC(NRI2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) ASPEED_PINCTRL_FUNC(NRI3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) ASPEED_PINCTRL_FUNC(NRI4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) ASPEED_PINCTRL_FUNC(NRTS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) ASPEED_PINCTRL_FUNC(NRTS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) ASPEED_PINCTRL_FUNC(NRTS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) ASPEED_PINCTRL_FUNC(OSCCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) ASPEED_PINCTRL_FUNC(PWM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) ASPEED_PINCTRL_FUNC(PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) ASPEED_PINCTRL_FUNC(PWM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) ASPEED_PINCTRL_FUNC(PWM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) ASPEED_PINCTRL_FUNC(PWM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) ASPEED_PINCTRL_FUNC(PWM5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) ASPEED_PINCTRL_FUNC(PWM6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) ASPEED_PINCTRL_FUNC(PWM7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) ASPEED_PINCTRL_FUNC(RGMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) ASPEED_PINCTRL_FUNC(RGMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) ASPEED_PINCTRL_FUNC(RMII1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) ASPEED_PINCTRL_FUNC(RMII2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) ASPEED_PINCTRL_FUNC(ROM16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) ASPEED_PINCTRL_FUNC(ROM8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) ASPEED_PINCTRL_FUNC(ROMCS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) ASPEED_PINCTRL_FUNC(ROMCS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) ASPEED_PINCTRL_FUNC(ROMCS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) ASPEED_PINCTRL_FUNC(ROMCS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) ASPEED_PINCTRL_FUNC(RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) ASPEED_PINCTRL_FUNC(RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) ASPEED_PINCTRL_FUNC(RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) ASPEED_PINCTRL_FUNC(RXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) ASPEED_PINCTRL_FUNC(SALT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) ASPEED_PINCTRL_FUNC(SALT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) ASPEED_PINCTRL_FUNC(SALT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) ASPEED_PINCTRL_FUNC(SALT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) ASPEED_PINCTRL_FUNC(SD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) ASPEED_PINCTRL_FUNC(SD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) ASPEED_PINCTRL_FUNC(SGPMCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) ASPEED_PINCTRL_FUNC(SGPMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) ASPEED_PINCTRL_FUNC(SGPMLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) ASPEED_PINCTRL_FUNC(SGPMO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) ASPEED_PINCTRL_FUNC(SGPSCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) ASPEED_PINCTRL_FUNC(SGPSI0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) ASPEED_PINCTRL_FUNC(SGPSI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) ASPEED_PINCTRL_FUNC(SGPSLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) ASPEED_PINCTRL_FUNC(SIOONCTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) ASPEED_PINCTRL_FUNC(SIOPBI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) ASPEED_PINCTRL_FUNC(SIOPBO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) ASPEED_PINCTRL_FUNC(SIOPWREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) ASPEED_PINCTRL_FUNC(SIOPWRGD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) ASPEED_PINCTRL_FUNC(SIOS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) ASPEED_PINCTRL_FUNC(SIOS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) ASPEED_PINCTRL_FUNC(SIOSCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) ASPEED_PINCTRL_FUNC(SPI1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) ASPEED_PINCTRL_FUNC(SPI1DEBUG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) ASPEED_PINCTRL_FUNC(SPICS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) ASPEED_PINCTRL_FUNC(TIMER3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) ASPEED_PINCTRL_FUNC(TIMER4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) ASPEED_PINCTRL_FUNC(TIMER5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) ASPEED_PINCTRL_FUNC(TIMER6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) ASPEED_PINCTRL_FUNC(TIMER7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) ASPEED_PINCTRL_FUNC(TIMER8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) ASPEED_PINCTRL_FUNC(TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) ASPEED_PINCTRL_FUNC(TXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) ASPEED_PINCTRL_FUNC(TXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) ASPEED_PINCTRL_FUNC(TXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) ASPEED_PINCTRL_FUNC(UART6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) ASPEED_PINCTRL_FUNC(USB11D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) ASPEED_PINCTRL_FUNC(USB11H2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) ASPEED_PINCTRL_FUNC(USB2D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) ASPEED_PINCTRL_FUNC(USB2H1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) ASPEED_PINCTRL_FUNC(USBCKI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) ASPEED_PINCTRL_FUNC(VGABIOS_ROM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) ASPEED_PINCTRL_FUNC(VGAHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) ASPEED_PINCTRL_FUNC(VGAVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) ASPEED_PINCTRL_FUNC(VPI18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) ASPEED_PINCTRL_FUNC(VPI24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) ASPEED_PINCTRL_FUNC(VPI30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) ASPEED_PINCTRL_FUNC(VPO12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) ASPEED_PINCTRL_FUNC(VPO24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) ASPEED_PINCTRL_FUNC(WDTRST1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) ASPEED_PINCTRL_FUNC(WDTRST2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) static const struct aspeed_pin_config aspeed_g4_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) /* GPIO banks ranges [A, B], [D, J], [M, R] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D6, D5, SCU8C, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D6, D5, SCU8C, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J21, E18, SCU8C, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J21, E18, SCU8C, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, E15, SCU8C, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, E15, SCU8C, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D15, B14, SCU8C, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D15, B14, SCU8C, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D18, C17, SCU8C, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D18, C17, SCU8C, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A14, U18, SCU8C, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A14, U18, SCU8C, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A8, E7, SCU8C, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A8, E7, SCU8C, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C22, E20, SCU8C, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C22, E20, SCU8C, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J5, T1, SCU8C, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J5, T1, SCU8C, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U1, U5, SCU8C, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U1, U5, SCU8C, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V3, V5, SCU8C, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V3, V5, SCU8C, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, W4, AB2, SCU8C, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, W4, AB2, SCU8C, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V6, V7, SCU8C, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V6, V7, SCU8C, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y6, AB7, SCU8C, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y6, AB7, SCU8C, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, A5, SCU8C, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, A5, SCU8C, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) /* GPIOs T[0-5] (RGMII1 Tx pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, A12, A13, SCU90, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A12, A13, SCU90, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A12, A13, SCU90, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, D9, D10, SCU90, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D9, D10, SCU90, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D9, D10, SCU90, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E11, E10, SCU90, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E11, E10, SCU90, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) /* GPIOs V[2-7] (RGMII2 Rx pins) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C9, C8, SCU90, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C9, C8, SCU90, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) /* ADC pull-downs (SCUA8[19:4]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L5, L5, SCUA8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L5, L5, SCUA8, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L4, L4, SCUA8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L4, L4, SCUA8, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, L3, SCUA8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, L3, SCUA8, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L2, L2, SCUA8, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L2, L2, SCUA8, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L1, L1, SCUA8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M5, M5, SCUA8, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M5, M5, SCUA8, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M4, M4, SCUA8, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M4, M4, SCUA8, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M3, M3, SCUA8, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M3, M3, SCUA8, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M2, M2, SCUA8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M2, M2, SCUA8, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N5, N5, SCUA8, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N5, N5, SCUA8, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N4, N4, SCUA8, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N4, N4, SCUA8, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N3, N3, SCUA8, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N3, N3, SCUA8, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N2, N2, SCUA8, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N2, N2, SCUA8, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N1, N1, SCUA8, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N1, N1, SCUA8, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, P5, P5, SCUA8, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, P5, P5, SCUA8, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) * Debounce settings for GPIOs D and E passthrough mode are in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) * SCUA8[27:20] and so are managed by pinctrl. Normal GPIO debounce for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) * banks D and E is handled by the GPIO driver - GPIO passthrough is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) * treated like any other non-GPIO mux function. There is a catch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) * however, in that the debounce period is configured in the GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) * controller. Due to this tangle between GPIO and pinctrl we don't yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) * fully support pass-through debounce.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A18, D16, SCUA8, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B17, A17, SCUA8, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C16, B16, SCUA8, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A16, E15, SCUA8, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D15, C15, SCUA8, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E14, D14, SCUA8, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C14, B14, SCUA8, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) const struct aspeed_sig_expr *expr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) for (i = 0; i < expr->ndescs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) const struct aspeed_sig_desc *desc = &expr->descs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) u32 pattern = enable ? desc->enable : desc->disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) u32 val = (pattern << __ffs(desc->mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) if (!ctx->maps[desc->ip])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) * Strap registers are configured in hardware or by early-boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) * firmware. Treat them as read-only despite that we can write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) * them. This may mean that certain functions cannot be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) * deconfigured and is the reason we re-evaluate after writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) * all descriptor bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) * Port D and port E GPIO loopback modes are the only exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) * as those are commonly used with front-panel buttons to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) * normal operation of the host when the BMC is powered off or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) * fails to boot. Once the BMC has booted, the loopback mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) * must be disabled for the BMC to control host power-on and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) * reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) !(desc->mask & (BIT(21) | BIT(22))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) desc->mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) ret = aspeed_sig_expr_eval(ctx, expr, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) static const struct aspeed_pin_config_map aspeed_g4_pin_config_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) static const struct aspeed_pinmux_ops aspeed_g4_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) .set = aspeed_g4_sig_expr_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) .pins = aspeed_g4_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .npins = ARRAY_SIZE(aspeed_g4_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) .pinmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .ops = &aspeed_g4_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .groups = aspeed_g4_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) .ngroups = ARRAY_SIZE(aspeed_g4_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) .functions = aspeed_g4_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .nfunctions = ARRAY_SIZE(aspeed_g4_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) .configs = aspeed_g4_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) .nconfigs = ARRAY_SIZE(aspeed_g4_configs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .confmaps = aspeed_g4_pin_config_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) .nconfmaps = ARRAY_SIZE(aspeed_g4_pin_config_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) static const struct pinmux_ops aspeed_g4_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) .get_functions_count = aspeed_pinmux_get_fn_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) .get_function_name = aspeed_pinmux_get_fn_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) .get_function_groups = aspeed_pinmux_get_fn_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) .set_mux = aspeed_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) .gpio_request_enable = aspeed_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .strict = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) static const struct pinctrl_ops aspeed_g4_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) .get_groups_count = aspeed_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .get_group_name = aspeed_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .get_group_pins = aspeed_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .pin_dbg_show = aspeed_pinctrl_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) static const struct pinconf_ops aspeed_g4_conf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .pin_config_get = aspeed_pin_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .pin_config_set = aspeed_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) .pin_config_group_get = aspeed_pin_config_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) .pin_config_group_set = aspeed_pin_config_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) static struct pinctrl_desc aspeed_g4_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .name = "aspeed-g4-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .pins = aspeed_g4_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .npins = ARRAY_SIZE(aspeed_g4_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .pctlops = &aspeed_g4_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .pmxops = &aspeed_g4_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) .confops = &aspeed_g4_conf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) static int aspeed_g4_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) for (i = 0; i < ARRAY_SIZE(aspeed_g4_pins); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) aspeed_g4_pins[i].number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) return aspeed_pinctrl_probe(pdev, &aspeed_g4_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) &aspeed_g4_pinctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) static const struct of_device_id aspeed_g4_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) { .compatible = "aspeed,ast2400-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) * The aspeed,g4-pinctrl compatible has been removed the from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) * bindings, but keep the match in case of old devicetrees.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) { .compatible = "aspeed,g4-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) static struct platform_driver aspeed_g4_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .probe = aspeed_g4_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .name = "aspeed-g4-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .of_match_table = aspeed_g4_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) static int aspeed_g4_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) return platform_driver_register(&aspeed_g4_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) arch_initcall(aspeed_g4_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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