Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) config PINCTRL_ASPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 	depends on (ARCH_ASPEED || COMPILE_TEST) && OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	depends on MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	select PINMUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	select PINCONF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	select GENERIC_PINCONF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	select REGMAP_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) config PINCTRL_ASPEED_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	bool "Aspeed G4 SoC pin control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	select PINCTRL_ASPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	  Say Y here to enable pin controller support for Aspeed's 4th
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	  generation SoCs. GPIO is provided by a separate GPIO driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) config PINCTRL_ASPEED_G5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	bool "Aspeed G5 SoC pin control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	select PINCTRL_ASPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	  Say Y here to enable pin controller support for Aspeed's 5th
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	  generation SoCs. GPIO is provided by a separate GPIO driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) config PINCTRL_ASPEED_G6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	bool "Aspeed G6 SoC pin control"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	select PINCTRL_ASPEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	  Say Y here to enable pin controller support for Aspeed's 6th
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	  generation SoCs. GPIO is provided by a separate GPIO driver.