^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OWL S900 Pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: David Liu <liuwei@actions-semi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "pinctrl-owl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Pinctrl registers offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MFCTL0 (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MFCTL1 (0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MFCTL2 (0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MFCTL3 (0x004C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PAD_PULLCTL0 (0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PAD_PULLCTL1 (0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PAD_PULLCTL2 (0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PAD_ST0 (0x006C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PAD_ST1 (0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PAD_CTL (0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PAD_DRV0 (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PAD_DRV1 (0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PAD_DRV2 (0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PAD_SR0 (0x0270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PAD_SR1 (0x0274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PAD_SR2 (0x0278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define _GPIOA(offset) (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define _GPIOB(offset) (32 + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define _GPIOC(offset) (64 + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define _GPIOD(offset) (76 + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define _GPIOE(offset) (106 + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define _GPIOF(offset) (138 + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define NUM_GPIOS (_GPIOF(7) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define _PIN(offset) (NUM_GPIOS + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ETH_TXD0 _GPIOA(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ETH_TXD1 _GPIOA(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ETH_TXEN _GPIOA(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ETH_RXER _GPIOA(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ETH_CRS_DV _GPIOA(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ETH_RXD1 _GPIOA(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ETH_RXD0 _GPIOA(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ETH_REF_CLK _GPIOA(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ETH_MDC _GPIOA(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ETH_MDIO _GPIOA(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SIRQ0 _GPIOA(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SIRQ1 _GPIOA(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SIRQ2 _GPIOA(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define I2S_D0 _GPIOA(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2S_BCLK0 _GPIOA(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2S_LRCLK0 _GPIOA(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2S_MCLK0 _GPIOA(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2S_D1 _GPIOA(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2S_BCLK1 _GPIOA(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define I2S_LRCLK1 _GPIOA(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define I2S_MCLK1 _GPIOA(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ERAM_A5 _GPIOA(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ERAM_A6 _GPIOA(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ERAM_A7 _GPIOA(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ERAM_A8 _GPIOA(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ERAM_A9 _GPIOA(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ERAM_A10 _GPIOA(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ERAM_A11 _GPIOA(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SD0_D0 _GPIOA(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SD0_D1 _GPIOA(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SD0_D2 _GPIOA(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SD0_D3 _GPIOA(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SD1_D0 _GPIOB(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SD1_D1 _GPIOB(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SD1_D2 _GPIOB(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SD1_D3 _GPIOB(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SD0_CMD _GPIOB(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SD0_CLK _GPIOB(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SD1_CMD _GPIOB(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SD1_CLK _GPIOB(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SPI0_SCLK _GPIOB(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPI0_SS _GPIOB(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPI0_MISO _GPIOB(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPI0_MOSI _GPIOB(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define UART0_RX _GPIOB(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define UART0_TX _GPIOB(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define UART2_RX _GPIOB(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define UART2_TX _GPIOB(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define UART2_RTSB _GPIOB(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define UART2_CTSB _GPIOB(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define UART4_RX _GPIOB(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define UART4_TX _GPIOB(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define I2C0_SCLK _GPIOB(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define I2C0_SDATA _GPIOB(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define I2C1_SCLK _GPIOB(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define I2C1_SDATA _GPIOB(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define I2C2_SCLK _GPIOB(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define I2C2_SDATA _GPIOB(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CSI0_DN0 _GPIOB(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CSI0_DP0 _GPIOB(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CSI0_DN1 _GPIOB(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CSI0_DP1 _GPIOB(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CSI0_CN _GPIOB(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CSI0_CP _GPIOB(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CSI0_DN2 _GPIOC(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CSI0_DP2 _GPIOC(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CSI0_DN3 _GPIOC(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CSI0_DP3 _GPIOC(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SENSOR0_PCLK _GPIOC(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CSI1_DN0 _GPIOC(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CSI1_DP0 _GPIOC(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CSI1_DN1 _GPIOC(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CSI1_DP1 _GPIOC(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CSI1_CN _GPIOC(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CSI1_CP _GPIOC(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SENSOR0_CKOUT _GPIOC(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LVDS_OEP _GPIOD(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LVDS_OEN _GPIOD(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LVDS_ODP _GPIOD(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LVDS_ODN _GPIOD(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LVDS_OCP _GPIOD(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LVDS_OCN _GPIOD(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LVDS_OBP _GPIOD(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LVDS_OBN _GPIOD(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LVDS_OAP _GPIOD(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LVDS_OAN _GPIOD(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LVDS_EEP _GPIOD(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define LVDS_EEN _GPIOD(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define LVDS_EDP _GPIOD(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LVDS_EDN _GPIOD(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LVDS_ECP _GPIOD(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LVDS_ECN _GPIOD(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LVDS_EBP _GPIOD(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LVDS_EBN _GPIOD(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LVDS_EAP _GPIOD(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LVDS_EAN _GPIOD(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DSI_DP3 _GPIOD(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DSI_DN3 _GPIOD(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DSI_DP1 _GPIOD(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DSI_DN1 _GPIOD(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DSI_CP _GPIOD(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define DSI_CN _GPIOD(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DSI_DP0 _GPIOD(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DSI_DN0 _GPIOD(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DSI_DP2 _GPIOD(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DSI_DN2 _GPIOD(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define NAND0_D0 _GPIOE(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define NAND0_D1 _GPIOE(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define NAND0_D2 _GPIOE(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define NAND0_D3 _GPIOE(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define NAND0_D4 _GPIOE(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define NAND0_D5 _GPIOE(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define NAND0_D6 _GPIOE(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define NAND0_D7 _GPIOE(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define NAND0_DQS _GPIOE(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define NAND0_DQSN _GPIOE(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define NAND0_ALE _GPIOE(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define NAND0_CLE _GPIOE(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define NAND0_CEB0 _GPIOE(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define NAND0_CEB1 _GPIOE(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define NAND0_CEB2 _GPIOE(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define NAND0_CEB3 _GPIOE(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define NAND1_D0 _GPIOE(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define NAND1_D1 _GPIOE(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define NAND1_D2 _GPIOE(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define NAND1_D3 _GPIOE(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define NAND1_D4 _GPIOE(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define NAND1_D5 _GPIOE(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define NAND1_D6 _GPIOE(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define NAND1_D7 _GPIOE(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define NAND1_DQS _GPIOE(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define NAND1_DQSN _GPIOE(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define NAND1_ALE _GPIOE(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define NAND1_CLE _GPIOE(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define NAND1_CEB0 _GPIOE(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define NAND1_CEB1 _GPIOE(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define NAND1_CEB2 _GPIOE(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define NAND1_CEB3 _GPIOE(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PCM1_IN _GPIOF(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PCM1_CLK _GPIOF(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PCM1_SYNC _GPIOF(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PCM1_OUT _GPIOF(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define UART3_RX _GPIOF(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define UART3_TX _GPIOF(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define UART3_RTSB _GPIOF(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define UART3_CTSB _GPIOF(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* System */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SGPIO0 _PIN(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SGPIO1 _PIN(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SGPIO2 _PIN(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SGPIO3 _PIN(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define NUM_PADS (_PIN(3) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Pad names as specified in datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct pinctrl_pin_desc s900_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(ETH_TXD0, "eth_txd0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(ETH_TXD1, "eth_txd1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(ETH_TXEN, "eth_txen"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(ETH_RXER, "eth_rxer"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(ETH_RXD0, "eth_rxd0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(ETH_MDC, "eth_mdc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(ETH_MDIO, "eth_mdio"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(SIRQ0, "sirq0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(SIRQ1, "sirq1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(SIRQ2, "sirq2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(I2S_D0, "i2s_d0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(I2S_D1, "i2s_d1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(PCM1_IN, "pcm1_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(PCM1_CLK, "pcm1_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(PCM1_OUT, "pcm1_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(ERAM_A5, "eram_a5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(ERAM_A6, "eram_a6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(ERAM_A7, "eram_a7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(ERAM_A8, "eram_a8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(ERAM_A9, "eram_a9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(ERAM_A10, "eram_a10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(ERAM_A11, "eram_a11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(LVDS_OEP, "lvds_oep"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(LVDS_OEN, "lvds_oen"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(LVDS_ODP, "lvds_odp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(LVDS_ODN, "lvds_odn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(LVDS_OCP, "lvds_ocp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(LVDS_OCN, "lvds_ocn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(LVDS_OBP, "lvds_obp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(LVDS_OBN, "lvds_obn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(LVDS_OAP, "lvds_oap"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(LVDS_OAN, "lvds_oan"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(LVDS_EEP, "lvds_eep"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(LVDS_EEN, "lvds_een"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(LVDS_EDP, "lvds_edp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(LVDS_EDN, "lvds_edn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(LVDS_ECP, "lvds_ecp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(LVDS_ECN, "lvds_ecn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(LVDS_EBP, "lvds_ebp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(LVDS_EBN, "lvds_ebn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(LVDS_EAP, "lvds_eap"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(LVDS_EAN, "lvds_ean"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(SD0_D0, "sd0_d0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(SD0_D1, "sd0_d1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(SD0_D2, "sd0_d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(SD0_D3, "sd0_d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(SD1_D0, "sd1_d0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(SD1_D1, "sd1_d1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(SD1_D2, "sd1_d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(SD1_D3, "sd1_d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(SD0_CMD, "sd0_cmd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(SD0_CLK, "sd0_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(SD1_CMD, "sd1_cmd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(SD1_CLK, "sd1_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(SPI0_SCLK, "spi0_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(SPI0_SS, "spi0_ss"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(SPI0_MISO, "spi0_miso"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(SPI0_MOSI, "spi0_mosi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(UART0_RX, "uart0_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(UART0_TX, "uart0_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(UART2_RX, "uart2_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(UART2_TX, "uart2_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(UART3_RX, "uart3_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(UART3_TX, "uart3_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(UART4_RX, "uart4_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(UART4_TX, "uart4_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(CSI0_DN0, "csi0_dn0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(CSI0_DP0, "csi0_dp0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(CSI0_DN1, "csi0_dn1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(CSI0_DP1, "csi0_dp1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(CSI0_CN, "csi0_cn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(CSI0_CP, "csi0_cp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(CSI0_DN2, "csi0_dn2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(CSI0_DP2, "csi0_dp2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(CSI0_DN3, "csi0_dn3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(CSI0_DP3, "csi0_dp3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(DSI_DP3, "dsi_dp3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(DSI_DN3, "dsi_dn3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(DSI_DP1, "dsi_dp1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(DSI_DN1, "dsi_dn1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(DSI_CP, "dsi_cp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(DSI_CN, "dsi_cn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(DSI_DP0, "dsi_dp0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(DSI_DN0, "dsi_dn0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(DSI_DP2, "dsi_dp2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(DSI_DN2, "dsi_dn2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(CSI1_DN0, "csi1_dn0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(CSI1_DP0, "csi1_dp0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(CSI1_DN1, "csi1_dn1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(CSI1_DP1, "csi1_dp1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(CSI1_CN, "csi1_cn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(CSI1_CP, "csi1_cp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(NAND0_D0, "nand0_d0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(NAND0_D1, "nand0_d1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(NAND0_D2, "nand0_d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(NAND0_D3, "nand0_d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(NAND0_D4, "nand0_d4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(NAND0_D5, "nand0_d5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(NAND0_D6, "nand0_d6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(NAND0_D7, "nand0_d7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(NAND0_DQS, "nand0_dqs"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(NAND0_DQSN, "nand0_dqsn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(NAND0_ALE, "nand0_ale"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(NAND0_CLE, "nand0_cle"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(NAND0_CEB0, "nand0_ceb0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(NAND0_CEB1, "nand0_ceb1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(NAND0_CEB2, "nand0_ceb2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_PIN(NAND0_CEB3, "nand0_ceb3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(NAND1_D0, "nand1_d0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(NAND1_D1, "nand1_d1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(NAND1_D2, "nand1_d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(NAND1_D3, "nand1_d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(NAND1_D4, "nand1_d4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(NAND1_D5, "nand1_d5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(NAND1_D6, "nand1_d6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(NAND1_D7, "nand1_d7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(NAND1_DQS, "nand1_dqs"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_PIN(NAND1_DQSN, "nand1_dqsn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINCTRL_PIN(NAND1_ALE, "nand1_ale"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINCTRL_PIN(NAND1_CLE, "nand1_cle"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINCTRL_PIN(NAND1_CEB0, "nand1_ceb0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PINCTRL_PIN(NAND1_CEB1, "nand1_ceb1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINCTRL_PIN(NAND1_CEB2, "nand1_ceb2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINCTRL_PIN(NAND1_CEB3, "nand1_ceb3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINCTRL_PIN(SGPIO0, "sgpio0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINCTRL_PIN(SGPIO1, "sgpio1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PINCTRL_PIN(SGPIO2, "sgpio2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PINCTRL_PIN(SGPIO3, "sgpio3")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) enum s900_pinmux_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) S900_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) S900_MUX_ETH_SMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) S900_MUX_SPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) S900_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) S900_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) S900_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) S900_MUX_SENS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) S900_MUX_UART0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) S900_MUX_UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) S900_MUX_UART3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) S900_MUX_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) S900_MUX_UART5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) S900_MUX_UART6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) S900_MUX_I2S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) S900_MUX_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) S900_MUX_PCM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) S900_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) S900_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) S900_MUX_PWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) S900_MUX_PWM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) S900_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) S900_MUX_PWM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) S900_MUX_PWM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) S900_MUX_PWM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) S900_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) S900_MUX_SD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) S900_MUX_SD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) S900_MUX_SD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) S900_MUX_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) S900_MUX_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) S900_MUX_I2C2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) S900_MUX_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) S900_MUX_I2C4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) S900_MUX_I2C5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) S900_MUX_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) S900_MUX_USB20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) S900_MUX_USB30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) S900_MUX_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) S900_MUX_MIPI_CSI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) S900_MUX_MIPI_CSI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) S900_MUX_MIPI_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) S900_MUX_NAND0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) S900_MUX_NAND1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) S900_MUX_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) S900_MUX_SIRQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) S900_MUX_SIRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) S900_MUX_SIRQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) S900_MUX_AUX_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) S900_MUX_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) S900_MUX_RESERVED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* mfp0_22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static unsigned int lvds_oxx_uart4_mfp_pads[] = { LVDS_OAP, LVDS_OAN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static unsigned int lvds_oxx_uart4_mfp_funcs[] = { S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) S900_MUX_UART4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* mfp0_21_20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static unsigned int rmii_mdc_mfp_pads[] = { ETH_MDC };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static unsigned int rmii_mdc_mfp_funcs[] = { S900_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) S900_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) S900_MUX_RESERVED };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static unsigned int rmii_mdio_mfp_pads[] = { ETH_MDIO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static unsigned int rmii_mdio_mfp_funcs[] = { S900_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) S900_MUX_PWM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) S900_MUX_RESERVED };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* mfp0_19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static unsigned int sirq0_mfp_pads[] = { SIRQ0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static unsigned int sirq0_mfp_funcs[] = { S900_MUX_SIRQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) S900_MUX_PWM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static unsigned int sirq1_mfp_pads[] = { SIRQ1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static unsigned int sirq1_mfp_funcs[] = { S900_MUX_SIRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) S900_MUX_PWM1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* mfp0_18_16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static unsigned int rmii_txd0_mfp_pads[] = { ETH_TXD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static unsigned int rmii_txd0_mfp_funcs[] = { S900_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) S900_MUX_ETH_SMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) S900_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) S900_MUX_UART6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) S900_MUX_SENS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) S900_MUX_PWM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static unsigned int rmii_txd1_mfp_pads[] = { ETH_TXD1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static unsigned int rmii_txd1_mfp_funcs[] = { S900_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) S900_MUX_ETH_SMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) S900_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) S900_MUX_UART6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) S900_MUX_SENS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) S900_MUX_PWM1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* mfp0_15_13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static unsigned int rmii_txen_mfp_pads[] = { ETH_TXEN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static unsigned int rmii_txen_mfp_funcs[] = { S900_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) S900_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) S900_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) S900_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static unsigned int rmii_rxer_mfp_pads[] = { ETH_RXER };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static unsigned int rmii_rxer_mfp_funcs[] = { S900_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) S900_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) S900_MUX_PWM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) S900_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* mfp0_12_11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static unsigned int rmii_crs_dv_mfp_pads[] = { ETH_CRS_DV };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static unsigned int rmii_crs_dv_mfp_funcs[] = { S900_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) S900_MUX_ETH_SMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) S900_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) S900_MUX_UART4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* mfp0_10_8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static unsigned int rmii_rxd1_mfp_pads[] = { ETH_RXD1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static unsigned int rmii_rxd1_mfp_funcs[] = { S900_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) S900_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) S900_MUX_UART5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) S900_MUX_PWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) S900_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static unsigned int rmii_rxd0_mfp_pads[] = { ETH_RXD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static unsigned int rmii_rxd0_mfp_funcs[] = { S900_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) S900_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) S900_MUX_UART5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) S900_MUX_PWM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) S900_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* mfp0_7_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static unsigned int rmii_ref_clk_mfp_pads[] = { ETH_REF_CLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static unsigned int rmii_ref_clk_mfp_funcs[] = { S900_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) S900_MUX_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) S900_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) S900_MUX_RESERVED };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* mfp0_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static unsigned int i2s_d0_mfp_funcs[] = { S900_MUX_I2S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) S900_MUX_PCM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static unsigned int i2s_d1_mfp_funcs[] = { S900_MUX_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) S900_MUX_PCM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* mfp0_4_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static unsigned int i2s_lr_m_clk0_mfp_pads[] = { I2S_LRCLK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) I2S_MCLK0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static unsigned int i2s_lr_m_clk0_mfp_funcs[] = { S900_MUX_I2S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) S900_MUX_PCM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) S900_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) S900_MUX_RESERVED };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* mfp0_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static unsigned int i2s_bclk0_mfp_pads[] = { I2S_BCLK0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static unsigned int i2s_bclk0_mfp_funcs[] = { S900_MUX_I2S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) S900_MUX_PCM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static unsigned int i2s_bclk1_mclk1_mfp_pads[] = { I2S_BCLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) I2S_LRCLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) I2S_MCLK1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static unsigned int i2s_bclk1_mclk1_mfp_funcs[] = { S900_MUX_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) S900_MUX_PCM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* mfp0_1_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static unsigned int pcm1_in_out_mfp_pads[] = { PCM1_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PCM1_OUT };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static unsigned int pcm1_in_out_mfp_funcs[] = { S900_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) S900_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) S900_MUX_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) S900_MUX_UART4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static unsigned int pcm1_clk_mfp_funcs[] = { S900_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) S900_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) S900_MUX_PWM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) S900_MUX_UART4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static unsigned int pcm1_sync_mfp_funcs[] = { S900_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) S900_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) S900_MUX_PWM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) S900_MUX_UART4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* mfp1_31_29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static unsigned int eram_a5_mfp_pads[] = { ERAM_A5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static unsigned int eram_a5_mfp_funcs[] = { S900_MUX_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) S900_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) S900_MUX_PWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) S900_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static unsigned int eram_a6_mfp_pads[] = { ERAM_A6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static unsigned int eram_a6_mfp_funcs[] = { S900_MUX_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) S900_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) S900_MUX_PWM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) S900_MUX_SENS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static unsigned int eram_a7_mfp_pads[] = { ERAM_A7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static unsigned int eram_a7_mfp_funcs[] = { S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) S900_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) S900_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* mfp1_28_26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static unsigned int eram_a8_mfp_pads[] = { ERAM_A8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static unsigned int eram_a8_mfp_funcs[] = { S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) S900_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) S900_MUX_PWM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) S900_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static unsigned int eram_a9_mfp_pads[] = { ERAM_A9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static unsigned int eram_a9_mfp_funcs[] = { S900_MUX_USB20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) S900_MUX_UART5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) S900_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) S900_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static unsigned int eram_a10_mfp_pads[] = { ERAM_A10 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static unsigned int eram_a10_mfp_funcs[] = { S900_MUX_USB30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) S900_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) S900_MUX_PWM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) S900_MUX_SENS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) S900_MUX_RESERVED };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* mfp1_25_23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static unsigned int eram_a11_mfp_pads[] = { ERAM_A11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static unsigned int eram_a11_mfp_funcs[] = { S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) S900_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) S900_MUX_UART5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) S900_MUX_SENS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) S900_MUX_RESERVED };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* mfp1_22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static unsigned int lvds_oep_odn_mfp_pads[] = { LVDS_OEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) LVDS_OEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) LVDS_ODP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) LVDS_ODN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static unsigned int lvds_oep_odn_mfp_funcs[] = { S900_MUX_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) S900_MUX_UART2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static unsigned int lvds_ocp_obn_mfp_pads[] = { LVDS_OCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) LVDS_OCN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) LVDS_OBP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) LVDS_OBN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static unsigned int lvds_ocp_obn_mfp_funcs[] = { S900_MUX_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) S900_MUX_PCM1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static unsigned int lvds_oap_oan_mfp_pads[] = { LVDS_OAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) LVDS_OAN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static unsigned int lvds_oap_oan_mfp_funcs[] = { S900_MUX_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) S900_MUX_ERAM };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* mfp1_21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static unsigned int lvds_e_mfp_pads[] = { LVDS_EEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) LVDS_EEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) LVDS_EDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) LVDS_EDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) LVDS_ECP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) LVDS_ECN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) LVDS_EBP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) LVDS_EBN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) LVDS_EAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) LVDS_EAN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static unsigned int lvds_e_mfp_funcs[] = { S900_MUX_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) S900_MUX_ERAM };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* mfp1_5_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static unsigned int spi0_sclk_mosi_mfp_pads[] = { SPI0_SCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) SPI0_MOSI };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static unsigned int spi0_sclk_mosi_mfp_funcs[] = { S900_MUX_SPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) S900_MUX_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) S900_MUX_PCM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* mfp1_3_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static unsigned int spi0_ss_mfp_pads[] = { SPI0_SS };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static unsigned int spi0_ss_mfp_funcs[] = { S900_MUX_SPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) S900_MUX_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) S900_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) S900_MUX_PCM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) S900_MUX_PWM4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static unsigned int spi0_miso_mfp_pads[] = { SPI0_MISO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static unsigned int spi0_miso_mfp_funcs[] = { S900_MUX_SPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) S900_MUX_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) S900_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) S900_MUX_PCM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) S900_MUX_PWM5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* mfp2_23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static unsigned int uart2_rtsb_mfp_funcs[] = { S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) S900_MUX_UART0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* mfp2_22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static unsigned int uart2_ctsb_mfp_funcs[] = { S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) S900_MUX_UART0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* mfp2_21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static unsigned int uart3_rtsb_mfp_funcs[] = { S900_MUX_UART3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) S900_MUX_UART5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* mfp2_20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static unsigned int uart3_ctsb_mfp_funcs[] = { S900_MUX_UART3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) S900_MUX_UART5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* mfp2_19_17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static unsigned int sd0_d0_mfp_funcs[] = { S900_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) S900_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) S900_MUX_UART5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) S900_MUX_GPU };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* mfp2_16_14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static unsigned int sd0_d1_mfp_funcs[] = { S900_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) S900_MUX_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) S900_MUX_UART5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* mfp_13_11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) SD0_D3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static unsigned int sd0_d2_d3_mfp_funcs[] = { S900_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) S900_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) S900_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) S900_MUX_UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) S900_MUX_GPU };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* mfp2_10_9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0, SD1_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) SD1_D2, SD1_D3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static unsigned int sd1_d0_d3_mfp_funcs[] = { S900_MUX_SD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) S900_MUX_ERAM };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* mfp2_8_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static unsigned int sd0_cmd_mfp_funcs[] = { S900_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) S900_MUX_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) S900_MUX_JTAG };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* mfp2_6_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static unsigned int sd0_clk_mfp_funcs[] = { S900_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) S900_MUX_ERAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) S900_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) S900_MUX_GPU };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* mfp2_4_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static unsigned int sd1_cmd_clk_mfp_pads[] = { SD1_CMD, SD1_CLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static unsigned int sd1_cmd_clk_mfp_funcs[] = { S900_MUX_SD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) S900_MUX_ERAM };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* mfp2_2_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static unsigned int uart0_rx_mfp_pads[] = { UART0_RX };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static unsigned int uart0_rx_mfp_funcs[] = { S900_MUX_UART0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) S900_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) S900_MUX_I2C5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) S900_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) S900_MUX_I2S1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* mfp3_27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static unsigned int nand0_d0_ceb3_mfp_pads[] = { NAND0_D0, NAND0_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) NAND0_D2, NAND0_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) NAND0_D4, NAND0_D5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) NAND0_D6, NAND0_D7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) NAND0_DQSN, NAND0_CEB3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static unsigned int nand0_d0_ceb3_mfp_funcs[] = { S900_MUX_NAND0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) S900_MUX_SD2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* mfp3_21_19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static unsigned int uart0_tx_mfp_pads[] = { UART0_TX };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static unsigned int uart0_tx_mfp_funcs[] = { S900_MUX_UART0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) S900_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) S900_MUX_I2C5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) S900_MUX_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) S900_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) S900_MUX_I2S1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* mfp3_18_16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK, I2C0_SDATA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static unsigned int i2c0_mfp_funcs[] = { S900_MUX_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) S900_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) S900_MUX_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) S900_MUX_UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) S900_MUX_SPI1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* mfp3_15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static unsigned int csi0_cn_cp_mfp_pads[] = { CSI0_CN, CSI0_CP };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static unsigned int csi0_cn_cp_mfp_funcs[] = { S900_MUX_SENS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) S900_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* mfp3_14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static unsigned int csi0_dn0_dp3_mfp_pads[] = { CSI0_DN0, CSI0_DP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) CSI0_DN1, CSI0_DP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) CSI0_CN, CSI0_CP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) CSI0_DP2, CSI0_DN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) CSI0_DN3, CSI0_DP3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static unsigned int csi0_dn0_dp3_mfp_funcs[] = { S900_MUX_MIPI_CSI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) S900_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* mfp3_13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static unsigned int csi1_dn0_cp_mfp_pads[] = { CSI1_DN0, CSI1_DP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) CSI1_DN1, CSI1_DP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) CSI1_CN, CSI1_CP };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static unsigned int csi1_dn0_cp_mfp_funcs[] = { S900_MUX_MIPI_CSI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) S900_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* mfp3_12_dsi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static unsigned int dsi_dp3_dn1_mfp_pads[] = { DSI_DP3, DSI_DN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) DSI_DP1, DSI_DN1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static unsigned int dsi_dp3_dn1_mfp_funcs[] = { S900_MUX_MIPI_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) S900_MUX_UART2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static unsigned int dsi_cp_dn0_mfp_pads[] = { DSI_CP, DSI_CN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) DSI_DP0, DSI_DN0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static unsigned int dsi_cp_dn0_mfp_funcs[] = { S900_MUX_MIPI_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) S900_MUX_PCM1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static unsigned int dsi_dp2_dn2_mfp_pads[] = { DSI_DP2, DSI_DN2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static unsigned int dsi_dp2_dn2_mfp_funcs[] = { S900_MUX_MIPI_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) S900_MUX_UART4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* mfp3_11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static unsigned int nand1_d0_ceb1_mfp_pads[] = { NAND1_D0, NAND1_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) NAND1_D2, NAND1_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) NAND1_D4, NAND1_D5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) NAND1_D6, NAND1_D7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) NAND1_DQSN, NAND1_CEB1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static unsigned int nand1_d0_ceb1_mfp_funcs[] = { S900_MUX_NAND1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) S900_MUX_SD3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* mfp3_10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static unsigned int nand1_ceb3_mfp_pads[] = { NAND1_CEB3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static unsigned int nand1_ceb3_mfp_funcs[] = { S900_MUX_NAND1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) S900_MUX_PWM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static unsigned int nand1_ceb0_mfp_pads[] = { NAND1_CEB0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static unsigned int nand1_ceb0_mfp_funcs[] = { S900_MUX_NAND1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) S900_MUX_PWM1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* mfp3_9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static unsigned int csi1_dn0_dp0_mfp_pads[] = { CSI1_DN0, CSI1_DP0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static unsigned int csi1_dn0_dp0_mfp_funcs[] = { S900_MUX_SENS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) S900_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* mfp3_8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static unsigned int uart4_rx_tx_mfp_pads[] = { UART4_RX, UART4_TX };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static unsigned int uart4_rx_tx_mfp_funcs[] = { S900_MUX_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) S900_MUX_I2C4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* PADDRV group data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* drv0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static unsigned int sgpio3_drv_pads[] = { SGPIO3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static unsigned int sgpio2_drv_pads[] = { SGPIO2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static unsigned int sgpio1_drv_pads[] = { SGPIO1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static unsigned int sgpio0_drv_pads[] = { SGPIO0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static unsigned int rmii_tx_d0_d1_drv_pads[] = { ETH_TXD0, ETH_TXD1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static unsigned int rmii_txen_rxer_drv_pads[] = { ETH_TXEN, ETH_RXER };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static unsigned int rmii_crs_dv_drv_pads[] = { ETH_CRS_DV };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static unsigned int rmii_rx_d1_d0_drv_pads[] = { ETH_RXD1, ETH_RXD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static unsigned int rmii_ref_clk_drv_pads[] = { ETH_REF_CLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static unsigned int rmii_mdc_mdio_drv_pads[] = { ETH_MDC, ETH_MDIO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static unsigned int sirq_0_1_drv_pads[] = { SIRQ0, SIRQ1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static unsigned int sirq2_drv_pads[] = { SIRQ2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static unsigned int i2s_d0_d1_drv_pads[] = { I2S_D0, I2S_D1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static unsigned int i2s_lr_m_clk0_drv_pads[] = { I2S_LRCLK0, I2S_MCLK0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static unsigned int i2s_blk1_mclk1_drv_pads[] = { I2S_BCLK0, I2S_BCLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) I2S_LRCLK1, I2S_MCLK1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static unsigned int pcm1_in_out_drv_pads[] = { PCM1_IN, PCM1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) PCM1_SYNC, PCM1_OUT };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* drv1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static unsigned int lvds_oap_oan_drv_pads[] = { LVDS_OAP, LVDS_OAN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static unsigned int lvds_oep_odn_drv_pads[] = { LVDS_OEP, LVDS_OEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) LVDS_ODP, LVDS_ODN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static unsigned int lvds_ocp_obn_drv_pads[] = { LVDS_OCP, LVDS_OCN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) LVDS_OBP, LVDS_OBN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static unsigned int lvds_e_drv_pads[] = { LVDS_EEP, LVDS_EEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) LVDS_EDP, LVDS_EDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) LVDS_ECP, LVDS_ECN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) LVDS_EBP, LVDS_EBN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static unsigned int sd0_d3_d0_drv_pads[] = { SD0_D3, SD0_D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) SD0_D1, SD0_D0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static unsigned int sd1_d3_d0_drv_pads[] = { SD1_D3, SD1_D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) SD1_D1, SD1_D0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static unsigned int sd0_sd1_cmd_clk_drv_pads[] = { SD0_CLK, SD0_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) SD1_CLK, SD1_CMD };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static unsigned int spi0_sclk_mosi_drv_pads[] = { SPI0_SCLK, SPI0_MOSI };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static unsigned int spi0_ss_miso_drv_pads[] = { SPI0_SS, SPI0_MISO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static unsigned int uart0_rx_tx_drv_pads[] = { UART0_RX, UART0_TX };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static unsigned int uart4_rx_tx_drv_pads[] = { UART4_RX, UART4_TX };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static unsigned int uart2_drv_pads[] = { UART2_RX, UART2_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) UART2_RTSB, UART2_CTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static unsigned int uart3_drv_pads[] = { UART3_RX, UART3_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) UART3_RTSB, UART3_CTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* drv2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static unsigned int i2c0_drv_pads[] = { I2C0_SCLK, I2C0_SDATA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static unsigned int i2c1_drv_pads[] = { I2C1_SCLK, I2C1_SDATA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static unsigned int i2c2_drv_pads[] = { I2C2_SCLK, I2C2_SDATA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static unsigned int sensor0_drv_pads[] = { SENSOR0_PCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) SENSOR0_CKOUT };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* SR group data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* sr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static unsigned int sgpio3_sr_pads[] = { SGPIO3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static unsigned int sgpio2_sr_pads[] = { SGPIO2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static unsigned int sgpio1_sr_pads[] = { SGPIO1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static unsigned int sgpio0_sr_pads[] = { SGPIO0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static unsigned int rmii_tx_d0_d1_sr_pads[] = { ETH_TXD0, ETH_TXD1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static unsigned int rmii_txen_rxer_sr_pads[] = { ETH_TXEN, ETH_RXER };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static unsigned int rmii_crs_dv_sr_pads[] = { ETH_CRS_DV };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static unsigned int rmii_rx_d1_d0_sr_pads[] = { ETH_RXD1, ETH_RXD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static unsigned int rmii_ref_clk_sr_pads[] = { ETH_REF_CLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static unsigned int rmii_mdc_mdio_sr_pads[] = { ETH_MDC, ETH_MDIO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static unsigned int sirq_0_1_sr_pads[] = { SIRQ0, SIRQ1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static unsigned int sirq2_sr_pads[] = { SIRQ2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static unsigned int i2s_do_d1_sr_pads[] = { I2S_D0, I2S_D1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static unsigned int i2s_lr_m_clk0_sr_pads[] = { I2S_LRCLK0, I2S_MCLK0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static unsigned int i2s_bclk0_mclk1_sr_pads[] = { I2S_BCLK0, I2S_BCLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) I2S_LRCLK1, I2S_MCLK1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static unsigned int pcm1_in_out_sr_pads[] = { PCM1_IN, PCM1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PCM1_SYNC, PCM1_OUT };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* sr1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static unsigned int sd1_d3_d0_sr_pads[] = { SD1_D3, SD1_D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) SD1_D1, SD1_D0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static unsigned int sd0_sd1_clk_cmd_sr_pads[] = { SD0_CLK, SD0_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) SD1_CLK, SD1_CMD };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static unsigned int spi0_sclk_mosi_sr_pads[] = { SPI0_SCLK, SPI0_MOSI };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static unsigned int spi0_ss_miso_sr_pads[] = { SPI0_SS, SPI0_MISO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static unsigned int uart0_rx_tx_sr_pads[] = { UART0_RX, UART0_TX };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static unsigned int uart4_rx_tx_sr_pads[] = { UART4_RX, UART4_TX };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static unsigned int uart2_sr_pads[] = { UART2_RX, UART2_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) UART2_RTSB, UART2_CTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static unsigned int uart3_sr_pads[] = { UART3_RX, UART3_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) UART3_RTSB, UART3_CTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* sr2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static unsigned int i2c0_sr_pads[] = { I2C0_SCLK, I2C0_SDATA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static unsigned int i2c1_sr_pads[] = { I2C1_SCLK, I2C1_SDATA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static unsigned int i2c2_sr_pads[] = { I2C2_SCLK, I2C2_SDATA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static unsigned int sensor0_sr_pads[] = { SENSOR0_PCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) SENSOR0_CKOUT };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* Pinctrl groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static const struct owl_pingroup s900_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) MUX_PG(lvds_oxx_uart4_mfp, 0, 22, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) MUX_PG(rmii_mdc_mfp, 0, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) MUX_PG(rmii_mdio_mfp, 0, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) MUX_PG(sirq0_mfp, 0, 19, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) MUX_PG(sirq1_mfp, 0, 19, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) MUX_PG(rmii_txd0_mfp, 0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) MUX_PG(rmii_txd1_mfp, 0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) MUX_PG(rmii_txen_mfp, 0, 13, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) MUX_PG(rmii_rxer_mfp, 0, 13, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) MUX_PG(rmii_crs_dv_mfp, 0, 11, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) MUX_PG(rmii_rxd1_mfp, 0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) MUX_PG(rmii_rxd0_mfp, 0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) MUX_PG(rmii_ref_clk_mfp, 0, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) MUX_PG(i2s_d0_mfp, 0, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) MUX_PG(i2s_d1_mfp, 0, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) MUX_PG(i2s_lr_m_clk0_mfp, 0, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) MUX_PG(i2s_bclk0_mfp, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) MUX_PG(i2s_bclk1_mclk1_mfp, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) MUX_PG(pcm1_in_out_mfp, 0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) MUX_PG(pcm1_clk_mfp, 0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MUX_PG(pcm1_sync_mfp, 0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) MUX_PG(eram_a5_mfp, 1, 29, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) MUX_PG(eram_a6_mfp, 1, 29, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) MUX_PG(eram_a7_mfp, 1, 29, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) MUX_PG(eram_a8_mfp, 1, 26, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) MUX_PG(eram_a9_mfp, 1, 26, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) MUX_PG(eram_a10_mfp, 1, 26, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) MUX_PG(eram_a11_mfp, 1, 23, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) MUX_PG(lvds_oep_odn_mfp, 1, 22, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) MUX_PG(lvds_ocp_obn_mfp, 1, 22, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) MUX_PG(lvds_oap_oan_mfp, 1, 22, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) MUX_PG(lvds_e_mfp, 1, 21, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) MUX_PG(spi0_sclk_mosi_mfp, 1, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) MUX_PG(spi0_ss_mfp, 1, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) MUX_PG(spi0_miso_mfp, 1, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) MUX_PG(uart2_rtsb_mfp, 2, 23, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) MUX_PG(uart2_ctsb_mfp, 2, 22, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) MUX_PG(uart3_rtsb_mfp, 2, 21, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) MUX_PG(uart3_ctsb_mfp, 2, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) MUX_PG(sd0_d0_mfp, 2, 17, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) MUX_PG(sd0_d1_mfp, 2, 14, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) MUX_PG(sd0_d2_d3_mfp, 2, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) MUX_PG(sd1_d0_d3_mfp, 2, 9, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) MUX_PG(sd0_cmd_mfp, 2, 7, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) MUX_PG(sd0_clk_mfp, 2, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) MUX_PG(sd1_cmd_clk_mfp, 2, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) MUX_PG(uart0_rx_mfp, 2, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) MUX_PG(nand0_d0_ceb3_mfp, 3, 27, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) MUX_PG(uart0_tx_mfp, 3, 19, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) MUX_PG(i2c0_mfp, 3, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) MUX_PG(csi0_cn_cp_mfp, 3, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) MUX_PG(csi0_dn0_dp3_mfp, 3, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) MUX_PG(csi1_dn0_cp_mfp, 3, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) MUX_PG(dsi_dp3_dn1_mfp, 3, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) MUX_PG(dsi_cp_dn0_mfp, 3, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) MUX_PG(dsi_dp2_dn2_mfp, 3, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) MUX_PG(nand1_d0_ceb1_mfp, 3, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) MUX_PG(nand1_ceb3_mfp, 3, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) MUX_PG(nand1_ceb0_mfp, 3, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) MUX_PG(csi1_dn0_dp0_mfp, 3, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) MUX_PG(uart4_rx_tx_mfp, 3, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) DRV_PG(sgpio3_drv, 0, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) DRV_PG(sgpio2_drv, 0, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) DRV_PG(sgpio1_drv, 0, 26, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) DRV_PG(sgpio0_drv, 0, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) DRV_PG(rmii_tx_d0_d1_drv, 0, 22, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) DRV_PG(rmii_txen_rxer_drv, 0, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) DRV_PG(rmii_crs_dv_drv, 0, 18, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) DRV_PG(rmii_rx_d1_d0_drv, 0, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) DRV_PG(rmii_ref_clk_drv, 0, 14, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) DRV_PG(rmii_mdc_mdio_drv, 0, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) DRV_PG(sirq_0_1_drv, 0, 10, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) DRV_PG(sirq2_drv, 0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) DRV_PG(i2s_d0_d1_drv, 0, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) DRV_PG(i2s_lr_m_clk0_drv, 0, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) DRV_PG(i2s_blk1_mclk1_drv, 0, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) DRV_PG(pcm1_in_out_drv, 0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) DRV_PG(lvds_oap_oan_drv, 1, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) DRV_PG(lvds_oep_odn_drv, 1, 26, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) DRV_PG(lvds_ocp_obn_drv, 1, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) DRV_PG(lvds_e_drv, 1, 22, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) DRV_PG(sd0_d3_d0_drv, 1, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) DRV_PG(sd1_d3_d0_drv, 1, 18, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) DRV_PG(sd0_sd1_cmd_clk_drv, 1, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) DRV_PG(spi0_sclk_mosi_drv, 1, 14, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) DRV_PG(spi0_ss_miso_drv, 1, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) DRV_PG(uart0_rx_tx_drv, 1, 10, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) DRV_PG(uart4_rx_tx_drv, 1, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) DRV_PG(uart2_drv, 1, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) DRV_PG(uart3_drv, 1, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) DRV_PG(i2c0_drv, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) DRV_PG(i2c1_drv, 2, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) DRV_PG(i2c2_drv, 2, 26, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) DRV_PG(sensor0_drv, 2, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) SR_PG(sgpio3_sr, 0, 15, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) SR_PG(sgpio2_sr, 0, 14, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) SR_PG(sgpio1_sr, 0, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) SR_PG(sgpio0_sr, 0, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) SR_PG(rmii_tx_d0_d1_sr, 0, 11, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) SR_PG(rmii_txen_rxer_sr, 0, 10, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) SR_PG(rmii_crs_dv_sr, 0, 9, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) SR_PG(rmii_rx_d1_d0_sr, 0, 8, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) SR_PG(rmii_ref_clk_sr, 0, 7, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) SR_PG(rmii_mdc_mdio_sr, 0, 6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) SR_PG(sirq_0_1_sr, 0, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) SR_PG(sirq2_sr, 0, 4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) SR_PG(i2s_do_d1_sr, 0, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) SR_PG(i2s_lr_m_clk0_sr, 0, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) SR_PG(i2s_bclk0_mclk1_sr, 0, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) SR_PG(pcm1_in_out_sr, 0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) SR_PG(sd1_d3_d0_sr, 1, 25, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) SR_PG(sd0_sd1_clk_cmd_sr, 1, 24, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) SR_PG(spi0_sclk_mosi_sr, 1, 23, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) SR_PG(spi0_ss_miso_sr, 1, 22, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) SR_PG(uart0_rx_tx_sr, 1, 21, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) SR_PG(uart4_rx_tx_sr, 1, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) SR_PG(uart2_sr, 1, 19, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) SR_PG(uart3_sr, 1, 18, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) SR_PG(i2c0_sr, 2, 31, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) SR_PG(i2c1_sr, 2, 30, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) SR_PG(i2c2_sr, 2, 29, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) SR_PG(sensor0_sr, 2, 25, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static const char * const eram_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) "lvds_oxx_uart4_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) "eram_a5_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) "eram_a6_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) "eram_a7_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) "eram_a8_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) "eram_a9_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) "eram_a10_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) "eram_a11_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) "lvds_oap_oan_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) "lvds_e_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) "spi0_sclk_mosi_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) "spi0_ss_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) "spi0_miso_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) "sd0_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) "sd0_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) "sd0_d2_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) "sd1_d0_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) "sd0_cmd_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) "sd0_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) "sd1_cmd_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static const char * const eth_rmii_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) "rmii_mdc_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) "rmii_mdio_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) "rmii_txd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) "rmii_txd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) "rmii_txen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) "rmii_rxer_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) "rmii_crs_dv_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) "rmii_rxd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) "rmii_rxd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) "rmii_ref_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) "eth_smi_dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static const char * const eth_smii_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) "rmii_txd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) "rmii_txd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) "rmii_crs_dv_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) "eth_smi_dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static const char * const spi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) "spi0_sclk_mosi_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) "spi0_ss_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) "spi0_miso_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) "spi0_sclk_mosi_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) "spi0_ss_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) "spi0_miso_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const char * const spi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) "pcm1_in_out_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) "pcm1_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) "pcm1_sync_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "uart0_rx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) "i2c0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static const char * const spi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "rmii_txd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) "rmii_txd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) "rmii_crs_dv_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) "rmii_ref_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static const char * const spi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) "rmii_txen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) "rmii_rxer_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static const char * const sens0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) "rmii_txd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) "rmii_txd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) "rmii_txen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "rmii_rxer_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) "rmii_rxd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) "rmii_rxd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) "eram_a5_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) "eram_a6_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) "eram_a7_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) "eram_a8_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) "eram_a9_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) "csi0_cn_cp_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) "csi0_dn0_dp3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) "csi1_dn0_cp_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) "csi1_dn0_dp0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) static const char * const uart0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) "uart2_rtsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) "uart2_ctsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) "uart0_rx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static const char * const uart1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) "sd0_d2_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) "i2c0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static const char * const uart2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) "rmii_mdc_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) "rmii_mdio_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) "rmii_txen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) "rmii_rxer_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) "rmii_rxd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) "rmii_rxd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) "lvds_oep_odn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) "uart2_rtsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) "uart2_ctsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) "sd0_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) "sd0_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) "sd0_d2_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) "uart0_rx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) "uart0_tx_mfp_pads",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) "i2c0_mfp_pads",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) "dsi_dp3_dn1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) "uart2_dummy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static const char * const uart3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) "uart3_rtsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) "uart3_ctsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) "uart3_dummy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static const char * const uart4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) "lvds_oxx_uart4_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) "rmii_crs_dv_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) "rmii_ref_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) "pcm1_in_out_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) "pcm1_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) "pcm1_sync_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) "eram_a5_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) "eram_a6_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) "dsi_dp2_dn2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) "uart4_rx_tx_mfp_pads",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) "uart4_dummy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static const char * const uart5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) "rmii_rxd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "rmii_rxd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) "eram_a9_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) "eram_a11_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) "uart3_rtsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) "uart3_ctsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) "sd0_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) "sd0_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static const char * const uart6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) "rmii_txd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) "rmii_txd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) static const char * const i2s0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) "i2s_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) "i2s_lr_m_clk0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) "i2s_bclk0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) "i2s0_dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static const char * const i2s1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) "i2s_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) "i2s_bclk1_mclk1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) "spi0_ss_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) "spi0_miso_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) "uart0_rx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) "i2s1_dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static const char * const pcm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) "i2s_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) "i2s_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) "i2s_lr_m_clk0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) "i2s_bclk0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) "i2s_bclk1_mclk1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) "spi0_sclk_mosi_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) "spi0_ss_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) "spi0_miso_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static const char * const pcm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) "i2s_lr_m_clk0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) "pcm1_in_out_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) "pcm1_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) "pcm1_sync_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) "lvds_oep_odn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) "spi0_ss_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) "spi0_miso_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) "uart0_rx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) "dsi_cp_dn0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) "pcm1_dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static const char * const jtag_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) "eram_a5_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) "eram_a6_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) "eram_a7_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) "eram_a8_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) "eram_a10_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) "eram_a10_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) "sd0_d2_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) "sd0_cmd_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) "sd0_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static const char * const pwm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) "sirq0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) "rmii_txd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) "rmii_rxd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) "eram_a5_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) "nand1_ceb3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static const char * const pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) "sirq1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) "rmii_txd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) "rmii_rxd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) "eram_a6_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) "eram_a8_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) "nand1_ceb0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static const char * const pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) "rmii_mdc_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) "rmii_txen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) "eram_a9_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) "eram_a11_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static const char * const pwm3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) "rmii_mdio_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) "rmii_rxer_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) "eram_a10_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static const char * const pwm4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) "pcm1_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) "spi0_ss_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static const char * const pwm5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) "pcm1_sync_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) "spi0_miso_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static const char * const sd0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) "sd0_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) "sd0_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) "sd0_d2_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) "sd0_cmd_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) "sd0_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static const char * const sd1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) "sd1_d0_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) "sd1_cmd_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) "sd1_dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static const char * const sd2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) "nand0_d0_ceb3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static const char * const sd3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) "nand1_d0_ceb1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static const char * const i2c0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) "i2c0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static const char * const i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) "i2c0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) "i2c1_dummy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static const char * const i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) "i2c2_dummy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static const char * const i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) "pcm1_in_out_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) "spi0_sclk_mosi_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static const char * const i2c4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) "uart4_rx_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static const char * const i2c5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) "uart0_rx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) static const char * const lvds_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) "lvds_oep_odn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) "lvds_ocp_obn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) "lvds_oap_oan_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) "lvds_e_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static const char * const usb20_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) "eram_a9_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static const char * const usb30_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) "eram_a10_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static const char * const gpu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) "sd0_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) "sd0_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) "sd0_d2_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) "sd0_cmd_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) "sd0_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static const char * const mipi_csi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) "csi0_dn0_dp3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static const char * const mipi_csi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) "csi1_dn0_cp_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static const char * const mipi_dsi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) "dsi_dp3_dn1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) "dsi_cp_dn0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) "dsi_dp2_dn2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) "mipi_dsi_dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static const char * const nand0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) "nand0_d0_ceb3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) "nand0_dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static const char * const nand1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) "nand1_d0_ceb1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) "nand1_ceb3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) "nand1_ceb0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) "nand1_dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static const char * const spdif_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static const char * const sirq0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) "sirq0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) "sirq0_dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static const char * const sirq1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) "sirq1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) "sirq1_dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static const char * const sirq2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) "sirq2_dummy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static const struct owl_pinmux_func s900_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) [S900_MUX_ERAM] = FUNCTION(eram),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) [S900_MUX_ETH_RMII] = FUNCTION(eth_rmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) [S900_MUX_ETH_SMII] = FUNCTION(eth_smii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) [S900_MUX_SPI0] = FUNCTION(spi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) [S900_MUX_SPI1] = FUNCTION(spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) [S900_MUX_SPI2] = FUNCTION(spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) [S900_MUX_SPI3] = FUNCTION(spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) [S900_MUX_SENS0] = FUNCTION(sens0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) [S900_MUX_UART0] = FUNCTION(uart0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) [S900_MUX_UART1] = FUNCTION(uart1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) [S900_MUX_UART2] = FUNCTION(uart2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) [S900_MUX_UART3] = FUNCTION(uart3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) [S900_MUX_UART4] = FUNCTION(uart4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) [S900_MUX_UART5] = FUNCTION(uart5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) [S900_MUX_UART6] = FUNCTION(uart6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) [S900_MUX_I2S0] = FUNCTION(i2s0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) [S900_MUX_I2S1] = FUNCTION(i2s1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) [S900_MUX_PCM0] = FUNCTION(pcm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) [S900_MUX_PCM1] = FUNCTION(pcm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) [S900_MUX_JTAG] = FUNCTION(jtag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) [S900_MUX_PWM0] = FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) [S900_MUX_PWM1] = FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) [S900_MUX_PWM2] = FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) [S900_MUX_PWM3] = FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) [S900_MUX_PWM4] = FUNCTION(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) [S900_MUX_PWM5] = FUNCTION(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) [S900_MUX_SD0] = FUNCTION(sd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) [S900_MUX_SD1] = FUNCTION(sd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) [S900_MUX_SD2] = FUNCTION(sd2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) [S900_MUX_SD3] = FUNCTION(sd3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) [S900_MUX_I2C0] = FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) [S900_MUX_I2C1] = FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) [S900_MUX_I2C2] = FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) [S900_MUX_I2C3] = FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) [S900_MUX_I2C4] = FUNCTION(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) [S900_MUX_I2C5] = FUNCTION(i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) [S900_MUX_LVDS] = FUNCTION(lvds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) [S900_MUX_USB30] = FUNCTION(usb30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) [S900_MUX_USB20] = FUNCTION(usb20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) [S900_MUX_GPU] = FUNCTION(gpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) [S900_MUX_MIPI_CSI0] = FUNCTION(mipi_csi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) [S900_MUX_MIPI_CSI1] = FUNCTION(mipi_csi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) [S900_MUX_MIPI_DSI] = FUNCTION(mipi_dsi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) [S900_MUX_NAND0] = FUNCTION(nand0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) [S900_MUX_NAND1] = FUNCTION(nand1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) [S900_MUX_SPDIF] = FUNCTION(spdif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) [S900_MUX_SIRQ0] = FUNCTION(sirq0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) [S900_MUX_SIRQ1] = FUNCTION(sirq1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) [S900_MUX_SIRQ2] = FUNCTION(sirq2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* PAD_PULLCTL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static PAD_PULLCTL_CONF(ETH_RXER, 0, 18, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static PAD_PULLCTL_CONF(SIRQ0, 0, 16, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static PAD_PULLCTL_CONF(SIRQ1, 0, 14, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static PAD_PULLCTL_CONF(SIRQ2, 0, 12, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 10, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static PAD_PULLCTL_CONF(ERAM_A5, 0, 6, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static PAD_PULLCTL_CONF(ERAM_A6, 0, 4, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static PAD_PULLCTL_CONF(ERAM_A7, 0, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static PAD_PULLCTL_CONF(ERAM_A10, 0, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* PAD_PULLCTL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static PAD_PULLCTL_CONF(PCM1_IN, 1, 30, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static PAD_PULLCTL_CONF(PCM1_OUT, 1, 28, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static PAD_PULLCTL_CONF(SD0_D0, 1, 26, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static PAD_PULLCTL_CONF(SD0_D1, 1, 24, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static PAD_PULLCTL_CONF(SD0_D2, 1, 22, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static PAD_PULLCTL_CONF(SD0_D3, 1, 20, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static PAD_PULLCTL_CONF(SD0_CMD, 1, 18, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static PAD_PULLCTL_CONF(SD0_CLK, 1, 16, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static PAD_PULLCTL_CONF(SD1_CMD, 1, 14, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static PAD_PULLCTL_CONF(SD1_D0, 1, 12, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static PAD_PULLCTL_CONF(SD1_D1, 1, 10, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static PAD_PULLCTL_CONF(SD1_D2, 1, 8, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static PAD_PULLCTL_CONF(SD1_D3, 1, 6, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static PAD_PULLCTL_CONF(UART0_RX, 1, 4, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static PAD_PULLCTL_CONF(UART0_TX, 1, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* PAD_PULLCTL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 26, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 24, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 22, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 20, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 18, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 16, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static PAD_PULLCTL_CONF(NAND0_D0, 2, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static PAD_PULLCTL_CONF(NAND0_D1, 2, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static PAD_PULLCTL_CONF(NAND0_D2, 2, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static PAD_PULLCTL_CONF(NAND0_D3, 2, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static PAD_PULLCTL_CONF(NAND0_D4, 2, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static PAD_PULLCTL_CONF(NAND0_D5, 2, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) static PAD_PULLCTL_CONF(NAND0_D6, 2, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static PAD_PULLCTL_CONF(NAND0_D7, 2, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static PAD_PULLCTL_CONF(NAND0_DQSN, 2, 14, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static PAD_PULLCTL_CONF(NAND0_DQS, 2, 13, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static PAD_PULLCTL_CONF(NAND1_D0, 2, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static PAD_PULLCTL_CONF(NAND1_D1, 2, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static PAD_PULLCTL_CONF(NAND1_D2, 2, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static PAD_PULLCTL_CONF(NAND1_D3, 2, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static PAD_PULLCTL_CONF(NAND1_D4, 2, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static PAD_PULLCTL_CONF(NAND1_D5, 2, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static PAD_PULLCTL_CONF(NAND1_D6, 2, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static PAD_PULLCTL_CONF(NAND1_D7, 2, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static PAD_PULLCTL_CONF(NAND1_DQSN, 2, 11, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static PAD_PULLCTL_CONF(NAND1_DQS, 2, 10, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static PAD_PULLCTL_CONF(SGPIO2, 2, 8, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static PAD_PULLCTL_CONF(SGPIO3, 2, 6, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static PAD_PULLCTL_CONF(UART4_RX, 2, 4, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static PAD_PULLCTL_CONF(UART4_TX, 2, 2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /* PAD_ST0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static PAD_ST_CONF(UART0_RX, 0, 29, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static PAD_ST_CONF(ETH_MDC, 0, 28, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static PAD_ST_CONF(SGPIO2, 0, 18, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static PAD_ST_CONF(SGPIO3, 0, 17, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static PAD_ST_CONF(UART4_TX, 0, 16, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static PAD_ST_CONF(I2S_D1, 0, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static PAD_ST_CONF(UART0_TX, 0, 14, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static PAD_ST_CONF(SD0_CLK, 0, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static PAD_ST_CONF(ERAM_A5, 0, 11, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static PAD_ST_CONF(ERAM_A9, 0, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static PAD_ST_CONF(LVDS_OEP, 0, 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static PAD_ST_CONF(LVDS_ODN, 0, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static PAD_ST_CONF(LVDS_OAP, 0, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static PAD_ST_CONF(I2S_BCLK1, 0, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /* PAD_ST1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) static PAD_ST_CONF(UART4_RX, 1, 28, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static PAD_ST_CONF(UART3_RX, 1, 25, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static PAD_ST_CONF(UART2_RX, 1, 22, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static PAD_ST_CONF(ETH_RXER, 1, 18, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static PAD_ST_CONF(LVDS_OCP, 1, 16, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static PAD_ST_CONF(LVDS_OBP, 1, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static PAD_ST_CONF(LVDS_OBN, 1, 14, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static PAD_ST_CONF(PCM1_OUT, 1, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) static PAD_ST_CONF(PCM1_IN, 1, 10, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* Pad info table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) static const struct owl_padinfo s900_padinfo[NUM_PADS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) [ETH_MDC] = PAD_INFO_ST(ETH_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) [ETH_MDIO] = PAD_INFO(ETH_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) [I2S_D0] = PAD_INFO(I2S_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) [I2S_D1] = PAD_INFO_ST(I2S_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) [I2S_BCLK1] = PAD_INFO_ST(I2S_BCLK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) [PCM1_IN] = PAD_INFO_PULLCTL_ST(PCM1_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) [PCM1_SYNC] = PAD_INFO_ST(PCM1_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) [PCM1_OUT] = PAD_INFO_PULLCTL_ST(PCM1_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) [ERAM_A5] = PAD_INFO_PULLCTL_ST(ERAM_A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) [ERAM_A6] = PAD_INFO_PULLCTL(ERAM_A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) [ERAM_A7] = PAD_INFO_PULLCTL(ERAM_A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) [ERAM_A8] = PAD_INFO(ERAM_A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) [ERAM_A9] = PAD_INFO_ST(ERAM_A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) [ERAM_A10] = PAD_INFO_PULLCTL(ERAM_A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) [ERAM_A11] = PAD_INFO(ERAM_A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) [LVDS_OEP] = PAD_INFO_ST(LVDS_OEP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) [LVDS_OEN] = PAD_INFO(LVDS_OEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) [LVDS_ODP] = PAD_INFO(LVDS_ODP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) [LVDS_ODN] = PAD_INFO_ST(LVDS_ODN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) [LVDS_OCP] = PAD_INFO_ST(LVDS_OCP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) [LVDS_OCN] = PAD_INFO(LVDS_OCN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) [LVDS_OBP] = PAD_INFO_ST(LVDS_OBP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) [LVDS_OBN] = PAD_INFO_ST(LVDS_OBN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) [LVDS_OAN] = PAD_INFO(LVDS_OAN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) [LVDS_EEP] = PAD_INFO(LVDS_EEP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) [LVDS_EEN] = PAD_INFO(LVDS_EEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) [LVDS_EDP] = PAD_INFO(LVDS_EDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) [LVDS_EDN] = PAD_INFO(LVDS_EDN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) [LVDS_ECP] = PAD_INFO(LVDS_ECP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) [LVDS_ECN] = PAD_INFO(LVDS_ECN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) [LVDS_EBP] = PAD_INFO(LVDS_EBP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) [LVDS_EBN] = PAD_INFO(LVDS_EBN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) [LVDS_EAP] = PAD_INFO(LVDS_EAP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) [LVDS_EAN] = PAD_INFO(LVDS_EAN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) [SD1_D0] = PAD_INFO_PULLCTL(SD1_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) [SD1_D1] = PAD_INFO_PULLCTL(SD1_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) [SD1_D2] = PAD_INFO_PULLCTL(SD1_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) [SD1_D3] = PAD_INFO_PULLCTL(SD1_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) [SD1_CMD] = PAD_INFO_PULLCTL(SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) [SD1_CLK] = PAD_INFO(SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) [SPI0_SCLK] = PAD_INFO_PULLCTL_ST(SPI0_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) [SPI0_SS] = PAD_INFO_ST(SPI0_SS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) [SPI0_MISO] = PAD_INFO_ST(SPI0_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) [SPI0_MOSI] = PAD_INFO_PULLCTL_ST(SPI0_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) [UART2_RX] = PAD_INFO_ST(UART2_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) [UART2_TX] = PAD_INFO(UART2_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) [UART3_RX] = PAD_INFO_ST(UART3_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) [UART3_TX] = PAD_INFO(UART3_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) [UART4_RX] = PAD_INFO_PULLCTL_ST(UART4_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) [UART4_TX] = PAD_INFO_PULLCTL_ST(UART4_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) [CSI0_DN0] = PAD_INFO(CSI0_DN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) [CSI0_DP0] = PAD_INFO(CSI0_DP0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) [CSI0_DN1] = PAD_INFO(CSI0_DN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) [CSI0_DP1] = PAD_INFO(CSI0_DP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) [CSI0_CN] = PAD_INFO(CSI0_CN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) [CSI0_CP] = PAD_INFO(CSI0_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) [CSI0_DN2] = PAD_INFO(CSI0_DN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) [CSI0_DP2] = PAD_INFO(CSI0_DP2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) [CSI0_DN3] = PAD_INFO(CSI0_DN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) [CSI0_DP3] = PAD_INFO(CSI0_DP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) [DSI_DP3] = PAD_INFO(DSI_DP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) [DSI_DN3] = PAD_INFO(DSI_DN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) [DSI_DP1] = PAD_INFO(DSI_DP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) [DSI_DN1] = PAD_INFO(DSI_DN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) [DSI_CP] = PAD_INFO(DSI_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) [DSI_CN] = PAD_INFO(DSI_CN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) [DSI_DP0] = PAD_INFO(DSI_DP0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) [DSI_DN0] = PAD_INFO(DSI_DN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) [DSI_DP2] = PAD_INFO(DSI_DP2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) [DSI_DN2] = PAD_INFO(DSI_DN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) [SENSOR0_PCLK] = PAD_INFO(SENSOR0_PCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) [CSI1_DN0] = PAD_INFO(CSI1_DN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) [CSI1_DP0] = PAD_INFO(CSI1_DP0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) [CSI1_DN1] = PAD_INFO(CSI1_DN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) [CSI1_DP1] = PAD_INFO(CSI1_DP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) [CSI1_CN] = PAD_INFO(CSI1_CN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) [CSI1_CP] = PAD_INFO(CSI1_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) [NAND0_D0] = PAD_INFO_PULLCTL(NAND0_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) [NAND0_D1] = PAD_INFO_PULLCTL(NAND0_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) [NAND0_D2] = PAD_INFO_PULLCTL(NAND0_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) [NAND0_D3] = PAD_INFO_PULLCTL(NAND0_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) [NAND0_D4] = PAD_INFO_PULLCTL(NAND0_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) [NAND0_D5] = PAD_INFO_PULLCTL(NAND0_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) [NAND0_D6] = PAD_INFO_PULLCTL(NAND0_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) [NAND0_D7] = PAD_INFO_PULLCTL(NAND0_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) [NAND0_DQS] = PAD_INFO_PULLCTL(NAND0_DQS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) [NAND0_DQSN] = PAD_INFO_PULLCTL(NAND0_DQSN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) [NAND0_ALE] = PAD_INFO(NAND0_ALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) [NAND0_CLE] = PAD_INFO(NAND0_CLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) [NAND0_CEB0] = PAD_INFO(NAND0_CEB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) [NAND0_CEB1] = PAD_INFO(NAND0_CEB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) [NAND0_CEB2] = PAD_INFO(NAND0_CEB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) [NAND0_CEB3] = PAD_INFO(NAND0_CEB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) [NAND1_D0] = PAD_INFO_PULLCTL(NAND1_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) [NAND1_D1] = PAD_INFO_PULLCTL(NAND1_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) [NAND1_D2] = PAD_INFO_PULLCTL(NAND1_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) [NAND1_D3] = PAD_INFO_PULLCTL(NAND1_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) [NAND1_D4] = PAD_INFO_PULLCTL(NAND1_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) [NAND1_D5] = PAD_INFO_PULLCTL(NAND1_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) [NAND1_D6] = PAD_INFO_PULLCTL(NAND1_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) [NAND1_D7] = PAD_INFO_PULLCTL(NAND1_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) [NAND1_DQS] = PAD_INFO_PULLCTL(NAND1_DQS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) [NAND1_DQSN] = PAD_INFO_PULLCTL(NAND1_DQSN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) [NAND1_ALE] = PAD_INFO(NAND1_ALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) [NAND1_CLE] = PAD_INFO(NAND1_CLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) [NAND1_CEB0] = PAD_INFO(NAND1_CEB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) [NAND1_CEB1] = PAD_INFO(NAND1_CEB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) [NAND1_CEB2] = PAD_INFO(NAND1_CEB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) [NAND1_CEB3] = PAD_INFO(NAND1_CEB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) [SGPIO0] = PAD_INFO(SGPIO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) [SGPIO1] = PAD_INFO(SGPIO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) [SGPIO2] = PAD_INFO_PULLCTL_ST(SGPIO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) [SGPIO3] = PAD_INFO_PULLCTL_ST(SGPIO3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static const struct owl_gpio_port s900_gpio_ports[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x240, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x534, 0x204, 0x208, 0x23C, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) OWL_GPIO_PORT(C, 0x0018, 12, 0x0, 0x4, 0x8, 0x52C, 0x200, 0x204, 0x238, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) OWL_GPIO_PORT(D, 0x0024, 30, 0x0, 0x4, 0x8, 0x524, 0x1FC, 0x200, 0x234, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) OWL_GPIO_PORT(E, 0x0030, 32, 0x0, 0x4, 0x8, 0x51C, 0x1F8, 0x1FC, 0x230, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) OWL_GPIO_PORT(F, 0x00F0, 8, 0x0, 0x4, 0x8, 0x460, 0x140, 0x144, 0x178, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) enum s900_pinconf_pull {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) OWL_PINCONF_PULL_HIZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) OWL_PINCONF_PULL_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) OWL_PINCONF_PULL_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) OWL_PINCONF_PULL_HOLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static int s900_pad_pinconf_arg2val(const struct owl_padinfo *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) unsigned int param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) u32 *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) case PIN_CONFIG_BIAS_BUS_HOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) *arg = OWL_PINCONF_PULL_HOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) *arg = OWL_PINCONF_PULL_HIZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) *arg = OWL_PINCONF_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) *arg = OWL_PINCONF_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) *arg = (*arg >= 1 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static int s900_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) unsigned int param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) u32 *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) case PIN_CONFIG_BIAS_BUS_HOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) *arg = *arg == OWL_PINCONF_PULL_HOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) *arg = *arg == OWL_PINCONF_PULL_HIZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) *arg = *arg == OWL_PINCONF_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) *arg = *arg == OWL_PINCONF_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) *arg = *arg == 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) static struct owl_pinctrl_soc_data s900_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .padinfo = s900_padinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .pins = (const struct pinctrl_pin_desc *)s900_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .npins = ARRAY_SIZE(s900_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .functions = s900_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .nfunctions = ARRAY_SIZE(s900_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .groups = s900_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .ngroups = ARRAY_SIZE(s900_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .ngpios = NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .ports = s900_gpio_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .nports = ARRAY_SIZE(s900_gpio_ports),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .padctl_arg2val = s900_pad_pinconf_arg2val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .padctl_val2arg = s900_pad_pinconf_val2arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) static int s900_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) return owl_pinctrl_probe(pdev, &s900_pinctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static const struct of_device_id s900_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) { .compatible = "actions,s900-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static struct platform_driver s900_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .name = "pinctrl-s900",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .of_match_table = of_match_ptr(s900_pinctrl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .probe = s900_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) static int __init s900_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) return platform_driver_register(&s900_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) arch_initcall(s900_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) static void __exit s900_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) platform_driver_unregister(&s900_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) module_exit(s900_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) MODULE_AUTHOR("Actions Semi Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) MODULE_DESCRIPTION("Actions Semi S900 SoC Pinctrl Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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