^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Actions Semi S500 SoC Pinctrl driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Actions Semi Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pinctrl-owl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Pinctrl registers offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MFCTL0 (0x0040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MFCTL1 (0x0044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MFCTL2 (0x0048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MFCTL3 (0x004C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PAD_PULLCTL0 (0x0060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PAD_PULLCTL1 (0x0064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PAD_PULLCTL2 (0x0068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PAD_ST0 (0x006C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PAD_ST1 (0x0070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PAD_CTL (0x0074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PAD_DRV0 (0x0080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PAD_DRV1 (0x0084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PAD_DRV2 (0x0088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define _GPIOA(offset) (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define _GPIOB(offset) (32 + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define _GPIOC(offset) (64 + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define _GPIOD(offset) (96 + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define _GPIOE(offset) (128 + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NUM_GPIOS (_GPIOE(3) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define _PIN(offset) (NUM_GPIOS + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DNAND_DQS _GPIOA(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DNAND_DQSN _GPIOA(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ETH_TXD0 _GPIOA(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ETH_TXD1 _GPIOA(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ETH_TXEN _GPIOA(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ETH_RXER _GPIOA(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ETH_CRS_DV _GPIOA(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ETH_RXD1 _GPIOA(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ETH_RXD0 _GPIOA(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ETH_REF_CLK _GPIOA(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ETH_MDC _GPIOA(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ETH_MDIO _GPIOA(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SIRQ0 _GPIOA(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SIRQ1 _GPIOA(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SIRQ2 _GPIOA(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define I2S_D0 _GPIOA(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define I2S_BCLK0 _GPIOA(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define I2S_LRCLK0 _GPIOA(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define I2S_MCLK0 _GPIOA(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define I2S_D1 _GPIOA(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2S_BCLK1 _GPIOB(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2S_LRCLK1 _GPIOB(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2S_MCLK1 _GPIOB(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define KS_IN0 _GPIOB(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define KS_IN1 _GPIOB(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define KS_IN2 _GPIOB(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define KS_IN3 _GPIOB(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define KS_OUT0 _GPIOB(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define KS_OUT1 _GPIOB(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define KS_OUT2 _GPIOB(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LVDS_OEP _GPIOB(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LVDS_OEN _GPIOB(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LVDS_ODP _GPIOB(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LVDS_ODN _GPIOB(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LVDS_OCP _GPIOB(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LVDS_OCN _GPIOB(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LVDS_OBP _GPIOB(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LVDS_OBN _GPIOB(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LVDS_OAP _GPIOB(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LVDS_OAN _GPIOB(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LVDS_EEP _GPIOB(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LVDS_EEN _GPIOB(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LVDS_EDP _GPIOB(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LVDS_EDN _GPIOB(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LVDS_ECP _GPIOB(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LVDS_ECN _GPIOB(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LVDS_EBP _GPIOB(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define LVDS_EBN _GPIOB(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LVDS_EAP _GPIOB(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LVDS_EAN _GPIOB(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LCD0_D18 _GPIOB(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define LCD0_D17 _GPIOB(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DSI_DP3 _GPIOC(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DSI_DN3 _GPIOC(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DSI_DP1 _GPIOC(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DSI_DN1 _GPIOC(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DSI_CP _GPIOC(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DSI_CN _GPIOC(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DSI_DP0 _GPIOC(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DSI_DN0 _GPIOC(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DSI_DP2 _GPIOC(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DSI_DN2 _GPIOC(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SD0_D0 _GPIOC(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SD0_D1 _GPIOC(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SD0_D2 _GPIOC(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SD0_D3 _GPIOC(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SD1_D0 _GPIOC(14) /* SD0_D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SD1_D1 _GPIOC(15) /* SD0_D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SD1_D2 _GPIOC(16) /* SD0_D6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SD1_D3 _GPIOC(17) /* SD0_D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SD0_CMD _GPIOC(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SD0_CLK _GPIOC(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SD1_CMD _GPIOC(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SD1_CLK _GPIOC(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SPI0_SCLK _GPIOC(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SPI0_SS _GPIOC(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SPI0_MISO _GPIOC(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SPI0_MOSI _GPIOC(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define UART0_RX _GPIOC(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define UART0_TX _GPIOC(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define I2C0_SCLK _GPIOC(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define I2C0_SDATA _GPIOC(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SENSOR0_PCLK _GPIOC(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SENSOR0_CKOUT _GPIOD(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DNAND_ALE _GPIOD(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DNAND_CLE _GPIOD(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DNAND_CEB0 _GPIOD(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DNAND_CEB1 _GPIOD(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DNAND_CEB2 _GPIOD(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DNAND_CEB3 _GPIOD(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define UART2_RX _GPIOD(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define UART2_TX _GPIOD(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define UART2_RTSB _GPIOD(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define UART2_CTSB _GPIOD(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define UART3_RX _GPIOD(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define UART3_TX _GPIOD(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define UART3_RTSB _GPIOD(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define UART3_CTSB _GPIOD(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PCM1_IN _GPIOD(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PCM1_CLK _GPIOD(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PCM1_SYNC _GPIOD(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PCM1_OUT _GPIOD(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define I2C1_SCLK _GPIOE(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define I2C1_SDATA _GPIOE(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define I2C2_SCLK _GPIOE(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define I2C2_SDATA _GPIOE(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CSI_DN0 _PIN(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CSI_DP0 _PIN(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CSI_DN1 _PIN(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CSI_DP1 _PIN(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CSI_CN _PIN(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CSI_CP _PIN(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CSI_DN2 _PIN(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CSI_DP2 _PIN(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CSI_DN3 _PIN(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CSI_DP3 _PIN(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DNAND_D0 _PIN(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DNAND_D1 _PIN(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DNAND_D2 _PIN(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DNAND_D3 _PIN(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DNAND_D4 _PIN(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DNAND_D5 _PIN(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DNAND_D6 _PIN(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DNAND_D7 _PIN(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DNAND_WRB _PIN(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DNAND_RDB _PIN(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DNAND_RDBN _PIN(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define DNAND_RB _PIN(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PORB _PIN(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLKO_25M _PIN(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define BSEL _PIN(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PKG0 _PIN(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PKG1 _PIN(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PKG2 _PIN(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PKG3 _PIN(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define _FIRSTPAD _GPIOA(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define _LASTPAD PKG3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define NUM_PADS (_PIN(28) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct pinctrl_pin_desc s500_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(DNAND_DQS, "dnand_dqs"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(DNAND_DQSN, "dnand_dqsn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(ETH_TXD0, "eth_txd0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(ETH_TXD1, "eth_txd1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(ETH_TXEN, "eth_txen"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(ETH_RXER, "eth_rxer"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(ETH_RXD1, "eth_rxd1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(ETH_RXD0, "eth_rxd0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(ETH_MDC, "eth_mdc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(ETH_MDIO, "eth_mdio"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(SIRQ0, "sirq0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(SIRQ1, "sirq1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(SIRQ2, "sirq2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(I2S_D0, "i2s_d0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(I2S_D1, "i2s_d1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(KS_IN0, "ks_in0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(KS_IN1, "ks_in1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(KS_IN2, "ks_in2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(KS_IN3, "ks_in3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(KS_OUT0, "ks_out0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(KS_OUT1, "ks_out1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(KS_OUT2, "ks_out2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(LVDS_OEP, "lvds_oep"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(LVDS_OEN, "lvds_oen"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(LVDS_ODP, "lvds_odp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(LVDS_ODN, "lvds_odn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(LVDS_OCP, "lvds_ocp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(LVDS_OCN, "lvds_ocn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(LVDS_OBP, "lvds_obp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(LVDS_OBN, "lvds_obn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(LVDS_OAP, "lvds_oap"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(LVDS_OAN, "lvds_oan"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(LVDS_EEP, "lvds_eep"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(LVDS_EEN, "lvds_een"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(LVDS_EDP, "lvds_edp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(LVDS_EDN, "lvds_edn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(LVDS_ECP, "lvds_ecp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(LVDS_ECN, "lvds_ecn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(LVDS_EBP, "lvds_ebp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(LVDS_EBN, "lvds_ebn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(LVDS_EAP, "lvds_eap"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(LVDS_EAN, "lvds_ean"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(LCD0_D18, "lcd0_d18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(LCD0_D17, "lcd0_d17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(DSI_DP3, "dsi_dp3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(DSI_DN3, "dsi_dn3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(DSI_DP1, "dsi_dp1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(DSI_DN1, "dsi_dn1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(DSI_CP, "dsi_cp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(DSI_CN, "dsi_cn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(DSI_DP0, "dsi_dp0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(DSI_DN0, "dsi_dn0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(DSI_DP2, "dsi_dp2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(DSI_DN2, "dsi_dn2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(SD0_D0, "sd0_d0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(SD0_D1, "sd0_d1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(SD0_D2, "sd0_d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(SD0_D3, "sd0_d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(SD1_D0, "sd1_d0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(SD1_D1, "sd1_d1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(SD1_D2, "sd1_d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(SD1_D3, "sd1_d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(SD0_CMD, "sd0_cmd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(SD0_CLK, "sd0_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(SD1_CMD, "sd1_cmd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(SD1_CLK, "sd1_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(SPI0_SCLK, "spi0_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(SPI0_SS, "spi0_ss"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(SPI0_MISO, "spi0_miso"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(SPI0_MOSI, "spi0_mosi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(UART0_RX, "uart0_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(UART0_TX, "uart0_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(DNAND_ALE, "dnand_ale"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(DNAND_CLE, "dnand_cle"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(DNAND_CEB0, "dnand_ceb0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(DNAND_CEB1, "dnand_ceb1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(DNAND_CEB2, "dnand_ceb2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(DNAND_CEB3, "dnand_ceb3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(UART2_RX, "uart2_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(UART2_TX, "uart2_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(UART3_RX, "uart3_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(UART3_TX, "uart3_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(PCM1_IN, "pcm1_in"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(PCM1_CLK, "pcm1_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(PCM1_OUT, "pcm1_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(CSI_DN0, "csi_dn0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(CSI_DP0, "csi_dp0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(CSI_DN1, "csi_dn1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(CSI_DP1, "csi_dp1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(CSI_DN2, "csi_dn2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(CSI_DP2, "csi_dp2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(CSI_DN3, "csi_dn3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(CSI_DP3, "csi_dp3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(CSI_CN, "csi_cn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(CSI_CP, "csi_cp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(DNAND_D0, "dnand_d0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(DNAND_D1, "dnand_d1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(DNAND_D2, "dnand_d2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(DNAND_D3, "dnand_d3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(DNAND_D4, "dnand_d4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(DNAND_D5, "dnand_d5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(DNAND_D6, "dnand_d6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(DNAND_D7, "dnand_d7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(DNAND_RB, "dnand_rb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(DNAND_RDB, "dnand_rdb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(DNAND_RDBN, "dnand_rdbn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(DNAND_WRB, "dnand_wrb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(PORB, "porb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(CLKO_25M, "clko_25m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(BSEL, "bsel"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(PKG0, "pkg0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(PKG1, "pkg1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(PKG2, "pkg2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(PKG3, "pkg3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) enum s500_pinmux_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) S500_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) S500_MUX_ETH_SMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) S500_MUX_SPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) S500_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) S500_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) S500_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) S500_MUX_SENS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) S500_MUX_SENS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) S500_MUX_UART0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) S500_MUX_UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) S500_MUX_UART3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) S500_MUX_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) S500_MUX_UART5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) S500_MUX_UART6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) S500_MUX_I2S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) S500_MUX_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) S500_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) S500_MUX_PCM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) S500_MUX_KS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) S500_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) S500_MUX_PWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) S500_MUX_PWM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) S500_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) S500_MUX_PWM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) S500_MUX_PWM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) S500_MUX_PWM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) S500_MUX_P0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) S500_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) S500_MUX_SD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) S500_MUX_SD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) S500_MUX_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) S500_MUX_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*S500_MUX_I2C2,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) S500_MUX_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) S500_MUX_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) S500_MUX_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) S500_MUX_USB30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) S500_MUX_CLKO_25M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) S500_MUX_MIPI_CSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) S500_MUX_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) S500_MUX_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*S500_MUX_SIRQ0,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /*S500_MUX_SIRQ1,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*S500_MUX_SIRQ2,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) S500_MUX_TS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) S500_MUX_LCD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* MFPCTL group data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* mfp0_31_26 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* mfp0_25_23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static unsigned int lcd0_d18_mfp_pads[] = { LCD0_D18 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static unsigned int lcd0_d18_mfp_funcs[] = { S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) S500_MUX_SENS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) S500_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) S500_MUX_PWM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) S500_MUX_LCD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* mfp0_22_20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static unsigned int rmii_crs_dv_mfp_pads[] = { ETH_CRS_DV };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static unsigned int rmii_crs_dv_mfp_funcs[] = { S500_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) S500_MUX_ETH_SMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) S500_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) S500_MUX_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) S500_MUX_PWM4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* mfp0_18_16_eth_txd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static unsigned int rmii_txd0_mfp_pads[] = { ETH_TXD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static unsigned int rmii_txd0_mfp_funcs[] = { S500_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) S500_MUX_ETH_SMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) S500_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) S500_MUX_UART6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) S500_MUX_PWM4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* mfp0_18_16_eth_txd1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static unsigned int rmii_txd1_mfp_pads[] = { ETH_TXD1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static unsigned int rmii_txd1_mfp_funcs[] = { S500_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) S500_MUX_ETH_SMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) S500_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) S500_MUX_UART6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) S500_MUX_PWM5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* mfp0_15_13_rmii_txen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static unsigned int rmii_txen_mfp_pads[] = { ETH_TXEN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static unsigned int rmii_txen_mfp_funcs[] = { S500_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) S500_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) S500_MUX_PWM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* mfp0_15_13_rmii_rxen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static unsigned int rmii_rxen_mfp_pads[] = { ETH_RXER };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static unsigned int rmii_rxen_mfp_funcs[] = { S500_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) S500_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) S500_MUX_PWM1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* mfp0_12_11 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* mfp0_10_8_rmii_rxd1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static unsigned int rmii_rxd1_mfp_pads[] = { ETH_RXD1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static unsigned int rmii_rxd1_mfp_funcs[] = { S500_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) S500_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) S500_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) S500_MUX_UART5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* mfp0_10_8_rmii_rxd0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static unsigned int rmii_rxd0_mfp_pads[] = { ETH_RXD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static unsigned int rmii_rxd0_mfp_funcs[] = { S500_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) S500_MUX_SPI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) S500_MUX_PWM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) S500_MUX_UART5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* mfp0_7_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static unsigned int rmii_ref_clk_mfp_pads[] = { ETH_REF_CLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static unsigned int rmii_ref_clk_mfp_funcs[] = { S500_MUX_ETH_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) S500_MUX_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) S500_MUX_SPI2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) S500_MUX_ETH_SMII };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* mfp0_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static unsigned int i2s_d0_mfp_funcs[] = { S500_MUX_I2S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) S500_MUX_NOR };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* mfp0_4_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static unsigned int i2s_pcm1_mfp_pads[] = { I2S_LRCLK0, I2S_MCLK0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static unsigned int i2s_pcm1_mfp_funcs[] = { S500_MUX_I2S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) S500_MUX_PCM1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* mfp0_2_1_i2s0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static unsigned int i2s0_pcm0_mfp_pads[] = { I2S_BCLK0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static unsigned int i2s0_pcm0_mfp_funcs[] = { S500_MUX_I2S0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) S500_MUX_PCM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* mfp0_2_1_i2s1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static unsigned int i2s1_pcm0_mfp_pads[] = { I2S_BCLK1, I2S_LRCLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) I2S_MCLK1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static unsigned int i2s1_pcm0_mfp_funcs[] = { S500_MUX_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) S500_MUX_PCM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* mfp0_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static unsigned int i2s_d1_mfp_funcs[] = { S500_MUX_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) S500_MUX_NOR };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* mfp1_31_29_ks_in0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static unsigned int ks_in0_mfp_pads[] = { KS_IN0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static unsigned int ks_in0_mfp_funcs[] = { S500_MUX_KS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) S500_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) S500_MUX_PWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) S500_MUX_PWM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) S500_MUX_SENS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) S500_MUX_PWM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) S500_MUX_P0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* mfp1_31_29_ks_in1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static unsigned int ks_in1_mfp_pads[] = { KS_IN1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static unsigned int ks_in1_mfp_funcs[] = { S500_MUX_KS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) S500_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) S500_MUX_PWM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) S500_MUX_PWM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) S500_MUX_SENS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) S500_MUX_PWM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) S500_MUX_USB30 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* mfp1_31_29_ks_in2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static unsigned int ks_in2_mfp_pads[] = { KS_IN2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static unsigned int ks_in2_mfp_funcs[] = { S500_MUX_KS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) S500_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) S500_MUX_PWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) S500_MUX_PWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) S500_MUX_SENS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) S500_MUX_PWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) S500_MUX_P0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* mfp1_28_26_ks_in3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static unsigned int ks_in3_mfp_pads[] = { KS_IN3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static unsigned int ks_in3_mfp_funcs[] = { S500_MUX_KS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) S500_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) S500_MUX_PWM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) S500_MUX_SENS1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* mfp1_28_26_ks_out0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static unsigned int ks_out0_mfp_pads[] = { KS_OUT0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static unsigned int ks_out0_mfp_funcs[] = { S500_MUX_KS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) S500_MUX_UART5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) S500_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) S500_MUX_SENS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) S500_MUX_SD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* mfp1_28_26_ks_out1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static unsigned int ks_out1_mfp_pads[] = { KS_OUT1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static unsigned int ks_out1_mfp_funcs[] = { S500_MUX_KS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) S500_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) S500_MUX_PWM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) S500_MUX_SENS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) S500_MUX_SD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* mfp1_25_23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static unsigned int ks_out2_mfp_pads[] = { KS_OUT2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static unsigned int ks_out2_mfp_funcs[] = { S500_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) S500_MUX_KS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) S500_MUX_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) S500_MUX_UART5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) S500_MUX_SENS1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* mfp1_22_21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static unsigned int lvds_o_pn_mfp_pads[] = { LVDS_OEP, LVDS_OEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) LVDS_ODP, LVDS_ODN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) LVDS_OCP, LVDS_OCN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) LVDS_OBP, LVDS_OBN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) LVDS_OAP, LVDS_OAN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static unsigned int lvds_o_pn_mfp_funcs[] = { S500_MUX_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) S500_MUX_TS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) S500_MUX_LCD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* mfp1_20_19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static unsigned int dsi_dn0_mfp_pads[] = { DSI_DN0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static unsigned int dsi_dn0_mfp_funcs[] = { S500_MUX_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) S500_MUX_SPI0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* mfp1_18_17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static unsigned int dsi_dp2_mfp_pads[] = { DSI_DP2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static unsigned int dsi_dp2_mfp_funcs[] = { S500_MUX_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) S500_MUX_SPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) S500_MUX_SD1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* mfp1_16_14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static unsigned int lcd0_d17_mfp_pads[] = { LCD0_D17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static unsigned int lcd0_d17_mfp_funcs[] = { S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) S500_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) S500_MUX_SD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) S500_MUX_PWM3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) S500_MUX_LCD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* mfp1_13_12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static unsigned int dsi_dp3_mfp_pads[] = { DSI_DP3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static unsigned int dsi_dp3_mfp_funcs[] = { S500_MUX_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) S500_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) S500_MUX_SD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) S500_MUX_LCD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* mfp1_11_10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static unsigned int dsi_dn3_mfp_pads[] = { DSI_DN3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static unsigned int dsi_dn3_mfp_funcs[] = { S500_MUX_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) S500_MUX_SD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) S500_MUX_LCD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* mfp1_9_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static unsigned int dsi_dp0_mfp_pads[] = { DSI_DP0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static unsigned int dsi_dp0_mfp_funcs[] = { S500_MUX_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) S500_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) S500_MUX_SPI0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* mfp1_6_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static unsigned int lvds_ee_pn_mfp_pads[] = { LVDS_EEP, LVDS_EEN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static unsigned int lvds_ee_pn_mfp_funcs[] = { S500_MUX_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) S500_MUX_TS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) S500_MUX_LCD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* mfp1_4_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static unsigned int spi0_i2c_pcm_mfp_pads[] = { SPI0_SCLK, SPI0_MOSI };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static unsigned int spi0_i2c_pcm_mfp_funcs[] = { S500_MUX_SPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) S500_MUX_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) S500_MUX_PCM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* mfp1_2_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static unsigned int spi0_i2s_pcm_mfp_pads[] = { SPI0_SS, SPI0_MISO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static unsigned int spi0_i2s_pcm_mfp_funcs[] = { S500_MUX_SPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) S500_MUX_I2S1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) S500_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) S500_MUX_PCM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* mfp2_31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* mfp2_30_29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static unsigned int dsi_dnp1_cp_mfp_pads[] = { DSI_DP1, DSI_CP, DSI_CN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static unsigned int dsi_dnp1_cp_mfp_funcs[] = { S500_MUX_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) S500_MUX_SD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) S500_MUX_LCD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* mfp2_28_27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static unsigned int lvds_e_pn_mfp_pads[] = { LVDS_EDP, LVDS_EDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) LVDS_ECP, LVDS_ECN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) LVDS_EBP, LVDS_EBN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) LVDS_EAP, LVDS_EAN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static unsigned int lvds_e_pn_mfp_funcs[] = { S500_MUX_LVDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) S500_MUX_LCD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* mfp2_26_24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static unsigned int dsi_dn2_mfp_pads[] = { DSI_DN2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static unsigned int dsi_dn2_mfp_funcs[] = { S500_MUX_DSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) S500_MUX_SD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) S500_MUX_SPI0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* mfp2_23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static unsigned int uart2_rtsb_mfp_funcs[] = { S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) S500_MUX_UART0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* mfp2_22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static unsigned int uart2_ctsb_mfp_funcs[] = { S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) S500_MUX_UART0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* mfp2_21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static unsigned int uart3_rtsb_mfp_funcs[] = { S500_MUX_UART3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) S500_MUX_UART5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* mfp2_20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static unsigned int uart3_ctsb_mfp_funcs[] = { S500_MUX_UART3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) S500_MUX_UART5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* mfp2_19_17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static unsigned int sd0_d0_mfp_funcs[] = { S500_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) S500_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) S500_MUX_UART5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* mfp2_16_14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static unsigned int sd0_d1_mfp_funcs[] = { S500_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) S500_MUX_UART5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* mfp2_13_11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2, SD0_D3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static unsigned int sd0_d2_d3_mfp_funcs[] = { S500_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) S500_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) S500_MUX_UART1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* mfp2_10_9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0, SD1_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SD1_D2, SD1_D3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static unsigned int sd1_d0_d3_mfp_funcs[] = { S500_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) S500_MUX_SD1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* mfp2_8_7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static unsigned int sd0_cmd_mfp_funcs[] = { S500_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) S500_MUX_JTAG };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* mfp2_6_5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static unsigned int sd0_clk_mfp_funcs[] = { S500_MUX_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) S500_MUX_JTAG };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* mfp2_4_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static unsigned int sd1_cmd_mfp_pads[] = { SD1_CMD };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static unsigned int sd1_cmd_mfp_funcs[] = { S500_MUX_SD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) S500_MUX_NOR };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* mfp2_2_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static unsigned int uart0_rx_mfp_pads[] = { UART0_RX };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static unsigned int uart0_rx_mfp_funcs[] = { S500_MUX_UART0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) S500_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) S500_MUX_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) S500_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) S500_MUX_I2S1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* mfp3_31 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* mfp3_30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static unsigned int clko_25m_mfp_pads[] = { CLKO_25M };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static unsigned int clko_25m_mfp_funcs[] = { S500_MUX_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) S500_MUX_CLKO_25M };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* mfp3_29_28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static unsigned int csi_cn_cp_mfp_pads[] = { CSI_CN, CSI_CP };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static unsigned int csi_cn_cp_mfp_funcs[] = { S500_MUX_MIPI_CSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) S500_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /* mfp3_27_24 reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* mfp3_23_22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static unsigned int sens0_ckout_mfp_pads[] = { SENSOR0_CKOUT };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static unsigned int sens0_ckout_mfp_funcs[] = { S500_MUX_SENS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) S500_MUX_SENS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) S500_MUX_PWM1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* mfp3_21_19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static unsigned int uart0_tx_mfp_pads[] = { UART0_TX };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static unsigned int uart0_tx_mfp_funcs[] = { S500_MUX_UART0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) S500_MUX_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) S500_MUX_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) S500_MUX_SPDIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) S500_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) S500_MUX_I2S1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* mfp3_18_16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) I2C0_SDATA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static unsigned int i2c0_mfp_funcs[] = { S500_MUX_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) S500_MUX_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) S500_MUX_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) S500_MUX_UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) S500_MUX_SPI1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* mfp3_15_14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static unsigned int csi_dn_dp_mfp_pads[] = { CSI_DN0, CSI_DN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) CSI_DN2, CSI_DN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) CSI_DP0, CSI_DP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) CSI_DP2, CSI_DP3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static unsigned int csi_dn_dp_mfp_funcs[] = { S500_MUX_MIPI_CSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) S500_MUX_SENS0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* mfp3_13_12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static unsigned int sen0_pclk_mfp_pads[] = { SENSOR0_PCLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static unsigned int sen0_pclk_mfp_funcs[] = { S500_MUX_SENS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) S500_MUX_NOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) S500_MUX_PWM0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* mfp3_11_10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static unsigned int pcm1_in_mfp_pads[] = { PCM1_IN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static unsigned int pcm1_in_mfp_funcs[] = { S500_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) S500_MUX_SENS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) S500_MUX_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) S500_MUX_PWM4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* mfp3_9_8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static unsigned int pcm1_clk_mfp_funcs[] = { S500_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) S500_MUX_SENS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) S500_MUX_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) S500_MUX_PWM5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* mfp3_7_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static unsigned int pcm1_sync_mfp_funcs[] = { S500_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) S500_MUX_SENS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) S500_MUX_UART6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) S500_MUX_I2C3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* mfp3_5_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static unsigned int pcm1_out_mfp_pads[] = { PCM1_OUT };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static unsigned int pcm1_out_mfp_funcs[] = { S500_MUX_PCM1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) S500_MUX_SENS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) S500_MUX_UART6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) S500_MUX_I2C3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* mfp3_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static unsigned int dnand_data_wr_mfp_pads[] = { DNAND_D0, DNAND_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) DNAND_D2, DNAND_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) DNAND_D4, DNAND_D5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) DNAND_D6, DNAND_D7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) DNAND_RDB, DNAND_RDBN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static unsigned int dnand_data_wr_mfp_funcs[] = { S500_MUX_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) S500_MUX_SD2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* mfp3_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static unsigned int dnand_acle_ce0_mfp_pads[] = { DNAND_ALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) DNAND_CLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) DNAND_CEB0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) DNAND_CEB1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static unsigned int dnand_acle_ce0_mfp_funcs[] = { S500_MUX_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) S500_MUX_SPI2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* mfp3_1_0_nand_ceb2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static unsigned int nand_ceb2_mfp_pads[] = { DNAND_CEB2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static unsigned int nand_ceb2_mfp_funcs[] = { S500_MUX_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) S500_MUX_PWM5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* mfp3_1_0_nand_ceb3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static unsigned int nand_ceb3_mfp_pads[] = { DNAND_CEB3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static unsigned int nand_ceb3_mfp_funcs[] = { S500_MUX_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) S500_MUX_PWM4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* PADDRV group data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* paddrv0_29_28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static unsigned int sirq_drv_pads[] = { SIRQ0, SIRQ1, SIRQ2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) /* paddrv0_23_22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static unsigned int rmii_txd01_txen_drv_pads[] = { ETH_TXD0, ETH_TXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ETH_TXEN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* paddrv0_21_20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static unsigned int rmii_rxer_drv_pads[] = { ETH_RXER };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* paddrv0_19_18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static unsigned int rmii_crs_drv_pads[] = { ETH_CRS_DV };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* paddrv0_17_16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static unsigned int rmii_rxd10_drv_pads[] = { ETH_RXD0, ETH_RXD1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* paddrv0_15_14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static unsigned int rmii_ref_clk_drv_pads[] = { ETH_REF_CLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* paddrv0_13_12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static unsigned int smi_mdc_mdio_drv_pads[] = { ETH_MDC, ETH_MDIO };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* paddrv0_11_10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static unsigned int i2s_d0_drv_pads[] = { I2S_D0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* paddrv0_9_8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static unsigned int i2s_bclk0_drv_pads[] = { I2S_BCLK0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* paddrv0_7_6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static unsigned int i2s3_drv_pads[] = { I2S_LRCLK0, I2S_MCLK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) I2S_D1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* paddrv0_5_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static unsigned int i2s13_drv_pads[] = { I2S_BCLK1, I2S_LRCLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) I2S_MCLK1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* paddrv0_3_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static unsigned int pcm1_drv_pads[] = { PCM1_IN, PCM1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) PCM1_SYNC, PCM1_OUT };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* paddrv0_1_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static unsigned int ks_in_drv_pads[] = { KS_IN0, KS_IN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) KS_IN2, KS_IN3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* paddrv1_31_30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static unsigned int ks_out_drv_pads[] = { KS_OUT0, KS_OUT1, KS_OUT2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* paddrv1_29_28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static unsigned int lvds_all_drv_pads[] = { LVDS_OEP, LVDS_OEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) LVDS_ODP, LVDS_ODN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) LVDS_OCP, LVDS_OCN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) LVDS_OBP, LVDS_OBN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) LVDS_OAP, LVDS_OAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) LVDS_EEP, LVDS_EEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) LVDS_EDP, LVDS_EDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) LVDS_ECP, LVDS_ECN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) LVDS_EBP, LVDS_EBN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) LVDS_EAP, LVDS_EAN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* paddrv1_27_26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static unsigned int lcd_dsi_drv_pads[] = { DSI_DP3, DSI_DN3, DSI_DP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) DSI_DN1, DSI_CP, DSI_CN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* paddrv1_25_24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static unsigned int dsi_drv_pads[] = { DSI_DP0, DSI_DN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) DSI_DP2, DSI_DN2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* paddrv1_23_22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static unsigned int sd0_d0_d3_drv_pads[] = { SD0_D0, SD0_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) SD0_D2, SD0_D3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* paddrv1_21_20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static unsigned int sd1_d0_d3_drv_pads[] = { SD1_D0, SD1_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) SD1_D2, SD1_D3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* paddrv1_19_18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static unsigned int sd0_cmd_drv_pads[] = { SD0_CMD };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* paddrv1_17_16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static unsigned int sd0_clk_drv_pads[] = { SD0_CLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* paddrv1_15_14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static unsigned int sd1_cmd_drv_pads[] = { SD1_CMD };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* paddrv1_13_12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static unsigned int sd1_clk_drv_pads[] = { SD1_CLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* paddrv1_11_10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static unsigned int spi0_all_drv_pads[] = { SPI0_SCLK, SPI0_SS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) SPI0_MISO, SPI0_MOSI };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* paddrv2_31_30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static unsigned int uart0_rx_drv_pads[] = { UART0_RX };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) /* paddrv2_29_28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static unsigned int uart0_tx_drv_pads[] = { UART0_TX };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* paddrv2_27_26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static unsigned int uart2_all_drv_pads[] = { UART2_RX, UART2_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) UART2_RTSB, UART2_CTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* paddrv2_24_23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static unsigned int i2c0_all_drv_pads[] = { I2C0_SCLK, I2C0_SDATA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* paddrv2_22_21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static unsigned int i2c12_all_drv_pads[] = { I2C1_SCLK, I2C1_SDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) I2C2_SCLK, I2C2_SDATA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* paddrv2_19_18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static unsigned int sens0_pclk_drv_pads[] = { SENSOR0_PCLK };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* paddrv2_13_12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static unsigned int sens0_ckout_drv_pads[] = { SENSOR0_CKOUT };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* paddrv2_3_2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static unsigned int uart3_all_drv_pads[] = { UART3_RX, UART3_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) UART3_RTSB, UART3_CTSB };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* Pinctrl groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const struct owl_pingroup s500_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) MUX_PG(lcd0_d18_mfp, 0, 23, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) MUX_PG(rmii_crs_dv_mfp, 0, 20, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) MUX_PG(rmii_txd0_mfp, 0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) MUX_PG(rmii_txd1_mfp, 0, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) MUX_PG(rmii_txen_mfp, 0, 13, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) MUX_PG(rmii_rxen_mfp, 0, 13, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) MUX_PG(rmii_rxd1_mfp, 0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) MUX_PG(rmii_rxd0_mfp, 0, 8, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) MUX_PG(rmii_ref_clk_mfp, 0, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) MUX_PG(i2s_d0_mfp, 0, 5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) MUX_PG(i2s_pcm1_mfp, 0, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) MUX_PG(i2s0_pcm0_mfp, 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) MUX_PG(i2s1_pcm0_mfp, 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) MUX_PG(i2s_d1_mfp, 0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) MUX_PG(ks_in2_mfp, 1, 29, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) MUX_PG(ks_in1_mfp, 1, 29, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) MUX_PG(ks_in0_mfp, 1, 29, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) MUX_PG(ks_in3_mfp, 1, 26, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) MUX_PG(ks_out0_mfp, 1, 26, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) MUX_PG(ks_out1_mfp, 1, 26, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) MUX_PG(ks_out2_mfp, 1, 23, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) MUX_PG(lvds_o_pn_mfp, 1, 21, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) MUX_PG(dsi_dn0_mfp, 1, 19, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) MUX_PG(dsi_dp2_mfp, 1, 17, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) MUX_PG(lcd0_d17_mfp, 1, 14, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) MUX_PG(dsi_dp3_mfp, 1, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) MUX_PG(dsi_dn3_mfp, 1, 10, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) MUX_PG(dsi_dp0_mfp, 1, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) MUX_PG(lvds_ee_pn_mfp, 1, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) MUX_PG(spi0_i2c_pcm_mfp, 1, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) MUX_PG(spi0_i2s_pcm_mfp, 1, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) MUX_PG(dsi_dnp1_cp_mfp, 2, 29, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) MUX_PG(lvds_e_pn_mfp, 2, 27, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) MUX_PG(dsi_dn2_mfp, 2, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) MUX_PG(uart2_rtsb_mfp, 2, 23, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) MUX_PG(uart2_ctsb_mfp, 2, 22, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) MUX_PG(uart3_rtsb_mfp, 2, 21, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) MUX_PG(uart3_ctsb_mfp, 2, 20, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) MUX_PG(sd0_d0_mfp, 2, 17, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) MUX_PG(sd0_d1_mfp, 2, 14, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) MUX_PG(sd0_d2_d3_mfp, 2, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) MUX_PG(sd1_d0_d3_mfp, 2, 9, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) MUX_PG(sd0_cmd_mfp, 2, 7, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MUX_PG(sd0_clk_mfp, 2, 5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) MUX_PG(sd1_cmd_mfp, 2, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) MUX_PG(uart0_rx_mfp, 2, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) MUX_PG(clko_25m_mfp, 3, 30, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) MUX_PG(csi_cn_cp_mfp, 3, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) MUX_PG(sens0_ckout_mfp, 3, 22, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) MUX_PG(uart0_tx_mfp, 3, 19, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) MUX_PG(i2c0_mfp, 3, 16, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) MUX_PG(csi_dn_dp_mfp, 3, 14, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) MUX_PG(sen0_pclk_mfp, 3, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) MUX_PG(pcm1_in_mfp, 3, 10, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) MUX_PG(pcm1_clk_mfp, 3, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) MUX_PG(pcm1_sync_mfp, 3, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) MUX_PG(pcm1_out_mfp, 3, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) MUX_PG(dnand_data_wr_mfp, 3, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) MUX_PG(dnand_acle_ce0_mfp, 3, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) MUX_PG(nand_ceb2_mfp, 3, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) MUX_PG(nand_ceb3_mfp, 3, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) DRV_PG(sirq_drv, 0, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) DRV_PG(rmii_txd01_txen_drv, 0, 22, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) DRV_PG(rmii_rxer_drv, 0, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) DRV_PG(rmii_crs_drv, 0, 18, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) DRV_PG(rmii_rxd10_drv, 0, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) DRV_PG(rmii_ref_clk_drv, 0, 14, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) DRV_PG(smi_mdc_mdio_drv, 0, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) DRV_PG(i2s_d0_drv, 0, 10, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) DRV_PG(i2s_bclk0_drv, 0, 8, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) DRV_PG(i2s3_drv, 0, 6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) DRV_PG(i2s13_drv, 0, 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) DRV_PG(pcm1_drv, 0, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) DRV_PG(ks_in_drv, 0, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) DRV_PG(ks_out_drv, 1, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) DRV_PG(lvds_all_drv, 1, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) DRV_PG(lcd_dsi_drv, 1, 26, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) DRV_PG(dsi_drv, 1, 24, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) DRV_PG(sd0_d0_d3_drv, 1, 22, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) DRV_PG(sd1_d0_d3_drv, 1, 20, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) DRV_PG(sd0_cmd_drv, 1, 18, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) DRV_PG(sd0_clk_drv, 1, 16, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) DRV_PG(sd1_cmd_drv, 1, 14, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) DRV_PG(sd1_clk_drv, 1, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) DRV_PG(spi0_all_drv, 1, 10, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) DRV_PG(uart0_rx_drv, 2, 30, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) DRV_PG(uart0_tx_drv, 2, 28, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) DRV_PG(uart2_all_drv, 2, 26, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) DRV_PG(i2c0_all_drv, 2, 23, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) DRV_PG(i2c12_all_drv, 2, 21, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) DRV_PG(sens0_pclk_drv, 2, 18, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) DRV_PG(sens0_ckout_drv, 2, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) DRV_PG(uart3_all_drv, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static const char * const nor_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) "lcd0_d18_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) "i2s_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) "i2s0_pcm0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) "i2s1_pcm0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) "i2s_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) "ks_in2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) "ks_in1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) "ks_in0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) "ks_in3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) "ks_out0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) "ks_out1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) "ks_out2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) "lcd0_d17_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) "lvds_ee_pn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) "spi0_i2c_pcm_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) "spi0_i2s_pcm_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) "lvds_e_pn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) "sd0_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) "sd0_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) "sd0_d2_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) "sd1_d0_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) "sd0_cmd_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) "sd1_cmd_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) "sens0_ckout_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) "sen0_pclk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static const char * const eth_rmii_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) "rmii_crs_dv_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) "rmii_txd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) "rmii_txd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) "rmii_txen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) "rmii_rxen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "rmii_rxd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) "rmii_rxd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) "rmii_ref_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static const char * const eth_smii_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) "rmii_crs_dv_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) "rmii_txd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) "rmii_txd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) "rmii_ref_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static const char * const spi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) "dsi_dn0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) "dsi_dp2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) "dsi_dp0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) "spi0_i2c_pcm_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) "spi0_i2s_pcm_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) "dsi_dn2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static const char * const spi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) "uart0_rx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) "i2c0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static const char * const spi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) "rmii_crs_dv_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) "rmii_txd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) "rmii_txd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) "rmii_ref_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) "dnand_acle_ce0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static const char * const spi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) "rmii_txen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) "rmii_rxen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) "rmii_rxd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) "rmii_rxd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static const char * const sens0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) "csi_cn_cp_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) "sens0_ckout_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) "csi_dn_dp_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) "sen0_pclk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const char * const sens1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) "lcd0_d18_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) "ks_in2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) "ks_in1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) "ks_in0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) "ks_in3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) "ks_out0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) "ks_out1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) "ks_out2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) "sens0_ckout_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) "pcm1_in_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) "pcm1_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "pcm1_sync_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) "pcm1_out_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const char * const uart0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) "uart2_rtsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) "uart2_ctsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) "uart0_rx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const char * const uart1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) "sd0_d2_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) "i2c0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static const char * const uart2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) "rmii_txen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) "rmii_rxen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) "rmii_rxd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) "rmii_rxd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "dsi_dn0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) "dsi_dp2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) "dsi_dp0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) "dsi_dn2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) "uart2_rtsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) "uart2_ctsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) "sd0_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) "sd0_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) "sd0_d2_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "uart0_rx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) "i2c0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static const char * const uart3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "uart3_rtsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) "uart3_ctsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static const char * const uart4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) "rmii_crs_dv_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) "rmii_ref_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) "pcm1_in_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) "pcm1_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static const char * const uart5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) "rmii_rxd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) "rmii_rxd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) "ks_out0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) "ks_out2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) "uart3_rtsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) "uart3_ctsb_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) "sd0_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) "sd0_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static const char * const uart6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) "rmii_txd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) "rmii_txd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) "pcm1_sync_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) "pcm1_out_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static const char * const i2s0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) "i2s_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) "i2s_pcm1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) "i2s0_pcm0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static const char * const i2s1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) "i2s1_pcm0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) "i2s_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) "spi0_i2s_pcm_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) "uart0_rx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static const char * const pcm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) "i2s_pcm1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) "spi0_i2s_pcm_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) "uart0_rx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) "pcm1_in_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) "pcm1_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) "pcm1_sync_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) "pcm1_out_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static const char * const pcm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) "i2s0_pcm0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) "i2s1_pcm0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) "spi0_i2c_pcm_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) "spi0_i2s_pcm_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static const char * const ks_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) "ks_in2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) "ks_in1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) "ks_in0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) "ks_in3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) "ks_out0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) "ks_out1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "ks_out2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static const char * const jtag_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) "ks_in2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) "ks_in1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) "ks_in0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) "ks_in3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) "ks_out1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) "sd0_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) "sd0_d2_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) "sd0_cmd_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) "sd0_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static const char * const pwm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) "ks_in2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) "ks_in0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) "rmii_txen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) "sen0_pclk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static const char * const pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) "rmii_rxen_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) "ks_in1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) "ks_in3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) "sens0_ckout_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static const char * const pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) "lcd0_d18_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) "rmii_rxd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) "ks_out0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) "ks_out2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const char * const pwm3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) "rmii_rxd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) "ks_out1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) "lcd0_d17_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static const char * const pwm4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) "lcd0_d18_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) "rmii_crs_dv_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) "rmii_txd0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) "ks_in0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) "pcm1_in_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) "nand_ceb3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static const char * const pwm5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) "rmii_txd1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) "ks_in1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) "pcm1_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) "nand_ceb2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static const char * const p0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) "ks_in2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) "ks_in0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static const char * const sd0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) "ks_out0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) "ks_out1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) "ks_out2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) "lcd0_d17_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) "dsi_dp3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) "dsi_dp0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) "sd0_d0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) "sd0_d1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) "sd0_d2_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) "sd1_d0_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) "sd0_cmd_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) "sd0_clk_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static const char * const sd1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) "dsi_dp2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) "lcd0_d17_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) "dsi_dp3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) "dsi_dn3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) "dsi_dnp1_cp_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) "dsi_dn2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) "sd1_d0_d3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) "sd1_cmd_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static const char * const sd2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) "dnand_data_wr_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static const char * const i2c0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) "uart0_rx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) "i2c0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static const char * const i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) "i2c0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static const char * const i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) "spi0_i2c_pcm_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) "pcm1_sync_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) "pcm1_out_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static const char * const lvds_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) "lvds_o_pn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) "lvds_ee_pn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) "lvds_e_pn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static const char * const ts_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) "lvds_o_pn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) "lvds_ee_pn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static const char * const lcd0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) "lcd0_d18_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) "lcd0_d17_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) "lvds_o_pn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) "dsi_dp3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) "dsi_dn3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) "lvds_ee_pn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) "dsi_dnp1_cp_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) "lvds_e_pn_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static const char * const usb30_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) "ks_in1_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static const char * const clko_25m_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) "clko_25m_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static const char * const mipi_csi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) "csi_cn_cp_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) "csi_dn_dp_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static const char * const dsi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) "dsi_dn0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) "dsi_dp2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) "dsi_dp3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) "dsi_dn3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) "dsi_dp0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) "dsi_dnp1_cp_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) "dsi_dn2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static const char * const nand_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) "dnand_data_wr_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) "dnand_acle_ce0_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) "nand_ceb2_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) "nand_ceb3_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static const char * const spdif_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) "uart0_tx_mfp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static const struct owl_pinmux_func s500_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) [S500_MUX_NOR] = FUNCTION(nor),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) [S500_MUX_ETH_RMII] = FUNCTION(eth_rmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) [S500_MUX_ETH_SMII] = FUNCTION(eth_smii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) [S500_MUX_SPI0] = FUNCTION(spi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) [S500_MUX_SPI1] = FUNCTION(spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) [S500_MUX_SPI2] = FUNCTION(spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) [S500_MUX_SPI3] = FUNCTION(spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) [S500_MUX_SENS0] = FUNCTION(sens0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) [S500_MUX_SENS1] = FUNCTION(sens1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) [S500_MUX_UART0] = FUNCTION(uart0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) [S500_MUX_UART1] = FUNCTION(uart1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) [S500_MUX_UART2] = FUNCTION(uart2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) [S500_MUX_UART3] = FUNCTION(uart3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) [S500_MUX_UART4] = FUNCTION(uart4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) [S500_MUX_UART5] = FUNCTION(uart5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) [S500_MUX_UART6] = FUNCTION(uart6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) [S500_MUX_I2S0] = FUNCTION(i2s0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) [S500_MUX_I2S1] = FUNCTION(i2s1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) [S500_MUX_PCM1] = FUNCTION(pcm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) [S500_MUX_PCM0] = FUNCTION(pcm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) [S500_MUX_KS] = FUNCTION(ks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) [S500_MUX_JTAG] = FUNCTION(jtag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) [S500_MUX_PWM0] = FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) [S500_MUX_PWM1] = FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) [S500_MUX_PWM2] = FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) [S500_MUX_PWM3] = FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) [S500_MUX_PWM4] = FUNCTION(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) [S500_MUX_PWM5] = FUNCTION(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) [S500_MUX_P0] = FUNCTION(p0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) [S500_MUX_SD0] = FUNCTION(sd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) [S500_MUX_SD1] = FUNCTION(sd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) [S500_MUX_SD2] = FUNCTION(sd2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) [S500_MUX_I2C0] = FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) [S500_MUX_I2C1] = FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /*[S500_MUX_I2C2] = FUNCTION(i2c2),*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) [S500_MUX_I2C3] = FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) [S500_MUX_DSI] = FUNCTION(dsi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) [S500_MUX_LVDS] = FUNCTION(lvds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) [S500_MUX_USB30] = FUNCTION(usb30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) [S500_MUX_CLKO_25M] = FUNCTION(clko_25m),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) [S500_MUX_MIPI_CSI] = FUNCTION(mipi_csi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) [S500_MUX_NAND] = FUNCTION(nand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) [S500_MUX_SPDIF] = FUNCTION(spdif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /*[S500_MUX_SIRQ0] = FUNCTION(sirq0),*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /*[S500_MUX_SIRQ1] = FUNCTION(sirq1),*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /*[S500_MUX_SIRQ2] = FUNCTION(sirq2),*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) [S500_MUX_TS] = FUNCTION(ts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) [S500_MUX_LCD0] = FUNCTION(lcd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* PAD_ST0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static PAD_ST_CONF(UART0_RX, 0, 29, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static PAD_ST_CONF(ETH_TXEN, 0, 21, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static PAD_ST_CONF(ETH_TXD0, 0, 20, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static PAD_ST_CONF(DSI_DP0, 0, 16, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static PAD_ST_CONF(DSI_DN0, 0, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static PAD_ST_CONF(UART0_TX, 0, 14, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static PAD_ST_CONF(SD0_CLK, 0, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static PAD_ST_CONF(KS_IN0, 0, 11, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static PAD_ST_CONF(SENSOR0_PCLK, 0, 9, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static PAD_ST_CONF(KS_OUT0, 0, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static PAD_ST_CONF(KS_OUT1, 0, 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static PAD_ST_CONF(KS_OUT2, 0, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* PAD_ST1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) static PAD_ST_CONF(DSI_DP2, 1, 31, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static PAD_ST_CONF(DSI_DN2, 1, 30, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static PAD_ST_CONF(UART3_CTSB, 1, 27, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static PAD_ST_CONF(UART3_RTSB, 1, 26, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static PAD_ST_CONF(UART3_RX, 1, 25, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static PAD_ST_CONF(UART2_RTSB, 1, 24, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static PAD_ST_CONF(UART2_CTSB, 1, 23, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static PAD_ST_CONF(UART2_RX, 1, 22, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static PAD_ST_CONF(ETH_RXD0, 1, 21, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static PAD_ST_CONF(ETH_RXD1, 1, 20, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static PAD_ST_CONF(ETH_RXER, 1, 18, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static PAD_ST_CONF(ETH_TXD1, 1, 17, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static PAD_ST_CONF(LVDS_OAP, 1, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static PAD_ST_CONF(PCM1_CLK, 1, 11, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static PAD_ST_CONF(PCM1_IN, 1, 10, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static PAD_ST_CONF(SPI0_MISO, 1, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static PAD_ST_CONF(SPI0_SS, 1, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* PAD_PULLCTL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static PAD_PULLCTL_CONF(PCM1_SYNC, 0, 30, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static PAD_PULLCTL_CONF(PCM1_OUT, 0, 29, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static PAD_PULLCTL_CONF(KS_OUT2, 0, 28, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static PAD_PULLCTL_CONF(LCD0_D17, 0, 27, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static PAD_PULLCTL_CONF(DSI_DN3, 0, 26, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static PAD_PULLCTL_CONF(ETH_RXER, 0, 16, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static PAD_PULLCTL_CONF(SIRQ0, 0, 14, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static PAD_PULLCTL_CONF(SIRQ1, 0, 12, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static PAD_PULLCTL_CONF(SIRQ2, 0, 10, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 9, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static PAD_PULLCTL_CONF(KS_IN0, 0, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static PAD_PULLCTL_CONF(KS_IN1, 0, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static PAD_PULLCTL_CONF(KS_IN2, 0, 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static PAD_PULLCTL_CONF(KS_IN3, 0, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static PAD_PULLCTL_CONF(KS_OUT0, 0, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static PAD_PULLCTL_CONF(KS_OUT1, 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static PAD_PULLCTL_CONF(DSI_DP1, 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) /* PAD_PULLCTL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static PAD_PULLCTL_CONF(DSI_CP, 1, 31, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static PAD_PULLCTL_CONF(DSI_CN, 1, 30, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static PAD_PULLCTL_CONF(DSI_DN2, 1, 28, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static PAD_PULLCTL_CONF(DNAND_RDBN, 1, 25, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static PAD_PULLCTL_CONF(SD0_D0, 1, 17, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static PAD_PULLCTL_CONF(SD0_D1, 1, 16, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static PAD_PULLCTL_CONF(SD0_D2, 1, 15, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static PAD_PULLCTL_CONF(SD0_D3, 1, 14, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static PAD_PULLCTL_CONF(SD0_CMD, 1, 13, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static PAD_PULLCTL_CONF(SD0_CLK, 1, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static PAD_PULLCTL_CONF(SD1_CMD, 1, 11, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static PAD_PULLCTL_CONF(SD1_D0, 1, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static PAD_PULLCTL_CONF(SD1_D1, 1, 5, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static PAD_PULLCTL_CONF(SD1_D2, 1, 4, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static PAD_PULLCTL_CONF(SD1_D3, 1, 3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static PAD_PULLCTL_CONF(UART0_RX, 1, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static PAD_PULLCTL_CONF(UART0_TX, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static PAD_PULLCTL_CONF(CLKO_25M, 1, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) /* PAD_PULLCTL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 12, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 11, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 10, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 9, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static PAD_PULLCTL_CONF(DNAND_DQSN, 2, 5, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static PAD_PULLCTL_CONF(DNAND_DQS, 2, 3, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static PAD_PULLCTL_CONF(DNAND_D0, 2, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static PAD_PULLCTL_CONF(DNAND_D1, 2, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static PAD_PULLCTL_CONF(DNAND_D2, 2, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static PAD_PULLCTL_CONF(DNAND_D3, 2, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static PAD_PULLCTL_CONF(DNAND_D4, 2, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static PAD_PULLCTL_CONF(DNAND_D5, 2, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) static PAD_PULLCTL_CONF(DNAND_D6, 2, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static PAD_PULLCTL_CONF(DNAND_D7, 2, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* Pad info table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static struct owl_padinfo s500_padinfo[NUM_PADS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) [DNAND_DQS] = PAD_INFO_PULLCTL(DNAND_DQS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) [DNAND_DQSN] = PAD_INFO_PULLCTL(DNAND_DQSN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) [ETH_MDC] = PAD_INFO(ETH_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) [ETH_MDIO] = PAD_INFO(ETH_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) [I2S_D0] = PAD_INFO(I2S_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) [I2S_D1] = PAD_INFO(I2S_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) [I2S_BCLK1] = PAD_INFO(I2S_BCLK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) [KS_IN0] = PAD_INFO_PULLCTL_ST(KS_IN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) [KS_IN1] = PAD_INFO_PULLCTL(KS_IN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) [KS_IN2] = PAD_INFO_PULLCTL(KS_IN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) [KS_IN3] = PAD_INFO_PULLCTL(KS_IN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) [KS_OUT0] = PAD_INFO_PULLCTL_ST(KS_OUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) [KS_OUT1] = PAD_INFO_PULLCTL_ST(KS_OUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) [KS_OUT2] = PAD_INFO_PULLCTL_ST(KS_OUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) [LVDS_OEP] = PAD_INFO(LVDS_OEP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) [LVDS_OEN] = PAD_INFO(LVDS_OEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) [LVDS_ODP] = PAD_INFO(LVDS_ODP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) [LVDS_ODN] = PAD_INFO(LVDS_ODN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) [LVDS_OCP] = PAD_INFO(LVDS_OCP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) [LVDS_OCN] = PAD_INFO(LVDS_OCN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) [LVDS_OBP] = PAD_INFO(LVDS_OBP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) [LVDS_OBN] = PAD_INFO(LVDS_OBN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) [LVDS_OAN] = PAD_INFO(LVDS_OAN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) [LVDS_EEP] = PAD_INFO(LVDS_EEP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) [LVDS_EEN] = PAD_INFO(LVDS_EEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) [LVDS_EDP] = PAD_INFO(LVDS_EDP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) [LVDS_EDN] = PAD_INFO(LVDS_EDN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) [LVDS_ECP] = PAD_INFO(LVDS_ECP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) [LVDS_ECN] = PAD_INFO(LVDS_ECN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) [LVDS_EBP] = PAD_INFO(LVDS_EBP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) [LVDS_EBN] = PAD_INFO(LVDS_EBN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) [LVDS_EAP] = PAD_INFO(LVDS_EAP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) [LVDS_EAN] = PAD_INFO(LVDS_EAN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) [LCD0_D18] = PAD_INFO(LCD0_D18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) [LCD0_D17] = PAD_INFO_PULLCTL(LCD0_D17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) [DSI_DP3] = PAD_INFO(DSI_DP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) [DSI_DN3] = PAD_INFO_PULLCTL(DSI_DN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) [DSI_DP1] = PAD_INFO_PULLCTL(DSI_DP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) [DSI_DN1] = PAD_INFO(DSI_DN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) [DSI_CP] = PAD_INFO_PULLCTL(DSI_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) [DSI_CN] = PAD_INFO_PULLCTL(DSI_CN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) [DSI_DP0] = PAD_INFO_ST(DSI_DP0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) [DSI_DN0] = PAD_INFO_ST(DSI_DN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) [DSI_DP2] = PAD_INFO_ST(DSI_DP2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) [DSI_DN2] = PAD_INFO_PULLCTL_ST(DSI_DN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) [SD1_D0] = PAD_INFO_PULLCTL(SD1_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) [SD1_D1] = PAD_INFO_PULLCTL(SD1_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) [SD1_D2] = PAD_INFO_PULLCTL(SD1_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) [SD1_D3] = PAD_INFO_PULLCTL(SD1_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) [SD1_CMD] = PAD_INFO_PULLCTL(SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) [SD1_CLK] = PAD_INFO(SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) [SPI0_SCLK] = PAD_INFO_PULLCTL_ST(SPI0_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) [SPI0_SS] = PAD_INFO_ST(SPI0_SS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) [SPI0_MISO] = PAD_INFO_ST(SPI0_MISO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) [SPI0_MOSI] = PAD_INFO_PULLCTL_ST(SPI0_MOSI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) [SENSOR0_PCLK] = PAD_INFO_ST(SENSOR0_PCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) [DNAND_ALE] = PAD_INFO(DNAND_ALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) [DNAND_CLE] = PAD_INFO(DNAND_CLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) [DNAND_CEB0] = PAD_INFO(DNAND_CEB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) [DNAND_CEB1] = PAD_INFO(DNAND_CEB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) [DNAND_CEB2] = PAD_INFO(DNAND_CEB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) [DNAND_CEB3] = PAD_INFO(DNAND_CEB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) [UART2_RX] = PAD_INFO_ST(UART2_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) [UART2_TX] = PAD_INFO(UART2_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) [UART3_RX] = PAD_INFO_ST(UART3_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) [UART3_TX] = PAD_INFO(UART3_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) [PCM1_IN] = PAD_INFO_ST(PCM1_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) [PCM1_SYNC] = PAD_INFO_PULLCTL_ST(PCM1_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) [PCM1_OUT] = PAD_INFO_PULLCTL(PCM1_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) [CSI_DN0] = PAD_INFO(CSI_DN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) [CSI_DP0] = PAD_INFO(CSI_DP0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) [CSI_DN1] = PAD_INFO(CSI_DN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) [CSI_DP1] = PAD_INFO(CSI_DP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) [CSI_CN] = PAD_INFO(CSI_CN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) [CSI_CP] = PAD_INFO(CSI_CP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) [CSI_DN2] = PAD_INFO(CSI_DN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) [CSI_DP2] = PAD_INFO(CSI_DP2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) [CSI_DN3] = PAD_INFO(CSI_DN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) [CSI_DP3] = PAD_INFO(CSI_DP3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) [DNAND_D0] = PAD_INFO_PULLCTL(DNAND_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) [DNAND_D1] = PAD_INFO_PULLCTL(DNAND_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) [DNAND_D2] = PAD_INFO_PULLCTL(DNAND_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) [DNAND_D3] = PAD_INFO_PULLCTL(DNAND_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) [DNAND_D4] = PAD_INFO_PULLCTL(DNAND_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) [DNAND_D5] = PAD_INFO_PULLCTL(DNAND_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) [DNAND_D6] = PAD_INFO_PULLCTL(DNAND_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) [DNAND_D7] = PAD_INFO_PULLCTL(DNAND_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) [DNAND_WRB] = PAD_INFO(DNAND_WRB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) [DNAND_RDB] = PAD_INFO(DNAND_RDB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) [DNAND_RDBN] = PAD_INFO_PULLCTL(DNAND_RDBN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) [DNAND_RB] = PAD_INFO(DNAND_RB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) [PORB] = PAD_INFO(PORB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) [CLKO_25M] = PAD_INFO_PULLCTL(CLKO_25M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) [BSEL] = PAD_INFO(BSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) [PKG0] = PAD_INFO(PKG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) [PKG1] = PAD_INFO(PKG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) [PKG2] = PAD_INFO(PKG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) [PKG3] = PAD_INFO(PKG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) static const struct owl_gpio_port s500_gpio_ports[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x230, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x1F8, 0x204, 0x208, 0x22C, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) OWL_GPIO_PORT(C, 0x0018, 32, 0x0, 0x4, 0x8, 0x1EC, 0x200, 0x204, 0x228, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) OWL_GPIO_PORT(D, 0x0024, 32, 0x0, 0x4, 0x8, 0x1E0, 0x1FC, 0x200, 0x224, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) OWL_GPIO_PORT(E, 0x0030, 4, 0x0, 0x4, 0x8, 0x1D4, 0x1F8, 0x1FC, 0x220, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) enum s500_pinconf_pull {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) OWL_PINCONF_PULL_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) OWL_PINCONF_PULL_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static int s500_pad_pinconf_arg2val(const struct owl_padinfo *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) unsigned int param, u32 *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) *arg = OWL_PINCONF_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) *arg = OWL_PINCONF_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) *arg = (*arg >= 1 ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) static int s500_pad_pinconf_val2arg(const struct owl_padinfo *padinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) unsigned int param, u32 *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) *arg = *arg == OWL_PINCONF_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) *arg = *arg == OWL_PINCONF_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) *arg = *arg == 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static struct owl_pinctrl_soc_data s500_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .padinfo = s500_padinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .pins = (const struct pinctrl_pin_desc *)s500_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .npins = ARRAY_SIZE(s500_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .functions = s500_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .nfunctions = ARRAY_SIZE(s500_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .groups = s500_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .ngroups = ARRAY_SIZE(s500_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .ngpios = NUM_GPIOS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .ports = s500_gpio_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .nports = ARRAY_SIZE(s500_gpio_ports),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .padctl_arg2val = s500_pad_pinconf_arg2val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .padctl_val2arg = s500_pad_pinconf_val2arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static int s500_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return owl_pinctrl_probe(pdev, &s500_pinctrl_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static const struct of_device_id s500_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) { .compatible = "actions,s500-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static struct platform_driver s500_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .name = "pinctrl-s500",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .of_match_table = of_match_ptr(s500_pinctrl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .probe = s500_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static int __init s500_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) return platform_driver_register(&s500_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) arch_initcall(s500_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) static void __exit s500_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) platform_driver_unregister(&s500_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) module_exit(s500_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) MODULE_AUTHOR("Actions Semi Inc.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) MODULE_DESCRIPTION("Actions Semi S500 SoC Pinctrl Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags